blob: de888b0c6a7648402effb3eca0a9100e1f1da031 [file] [log] [blame]
Uwe Hermannddd5c9e2010-02-21 21:17:00 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Andrew Morgana0743832011-07-25 22:07:05 +000021#if defined(__i386__) || defined(__x86_64__)
22
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000023#include <stdlib.h>
24#include <string.h>
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000025#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000026#include "programmer.h"
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000027
28#define BIOS_ROM_ADDR 0x90
29#define BIOS_ROM_DATA 0x94
30
31#define REG_FLASH_ACCESS 0x58
32
33#define PCI_VENDOR_ID_HPT 0x1103
34
Carl-Daniel Hailfingera73fb492010-10-06 23:48:34 +000035const struct pcidev_status ata_hpt[] = {
Michael Karcher84486392010-02-24 00:04:40 +000036 {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},
37 {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"},
38 {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"},
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000039
40 {},
41};
42
David Hendricks8bb20212011-06-14 01:35:36 +000043static int atahpt_shutdown(void *data)
44{
45 /* Flash access is disabled automatically by PCI restore. */
46 pci_cleanup(pacc);
47 release_io_perms();
48 return 0;
49}
50
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000051int atahpt_init(void)
52{
53 uint32_t reg32;
54
55 get_io_perms();
56
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +000057 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt);
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000058
59 /* Enable flash access. */
60 reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS);
61 reg32 |= (1 << 24);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000062 rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000063
64 buses_supported = CHIP_BUSTYPE_PARALLEL;
65
David Hendricks8bb20212011-06-14 01:35:36 +000066 if (register_shutdown(atahpt_shutdown, NULL))
67 return 1;
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000068 return 0;
69}
70
71void atahpt_chip_writeb(uint8_t val, chipaddr addr)
72{
73 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
74 OUTB(val, io_base_addr + BIOS_ROM_DATA);
75}
76
77uint8_t atahpt_chip_readb(const chipaddr addr)
78{
79 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
80 return INB(io_base_addr + BIOS_ROM_DATA);
81}
Andrew Morgana0743832011-07-25 22:07:05 +000082
83#else
84#error PCI port I/O access is not supported on this architecture yet.
85#endif