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Uwe Hermannddd5c9e2010-02-21 21:17:00 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Andrew Morgana0743832011-07-25 22:07:05 +000021#if defined(__i386__) || defined(__x86_64__)
22
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000023#include <stdlib.h>
24#include <string.h>
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000025#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000026#include "programmer.h"
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000027
28#define BIOS_ROM_ADDR 0x90
29#define BIOS_ROM_DATA 0x94
30
31#define REG_FLASH_ACCESS 0x58
32
33#define PCI_VENDOR_ID_HPT 0x1103
34
Carl-Daniel Hailfingera73fb492010-10-06 23:48:34 +000035const struct pcidev_status ata_hpt[] = {
Michael Karcher84486392010-02-24 00:04:40 +000036 {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},
37 {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"},
38 {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"},
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000039
40 {},
41};
42
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000043static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
44 chipaddr addr);
45static uint8_t atahpt_chip_readb(const struct flashctx *flash,
46 const chipaddr addr);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000047static const struct par_programmer par_programmer_atahpt = {
48 .chip_readb = atahpt_chip_readb,
49 .chip_readw = fallback_chip_readw,
50 .chip_readl = fallback_chip_readl,
51 .chip_readn = fallback_chip_readn,
52 .chip_writeb = atahpt_chip_writeb,
53 .chip_writew = fallback_chip_writew,
54 .chip_writel = fallback_chip_writel,
55 .chip_writen = fallback_chip_writen,
56};
57
David Hendricks8bb20212011-06-14 01:35:36 +000058static int atahpt_shutdown(void *data)
59{
60 /* Flash access is disabled automatically by PCI restore. */
61 pci_cleanup(pacc);
62 release_io_perms();
63 return 0;
64}
65
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000066int atahpt_init(void)
67{
68 uint32_t reg32;
69
70 get_io_perms();
71
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +000072 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt);
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000073
74 /* Enable flash access. */
75 reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS);
76 reg32 |= (1 << 24);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000077 rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000078
David Hendricks8bb20212011-06-14 01:35:36 +000079 if (register_shutdown(atahpt_shutdown, NULL))
80 return 1;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000081
82 register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL);
83
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000084 return 0;
85}
86
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000087static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
88 chipaddr addr)
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000089{
90 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
91 OUTB(val, io_base_addr + BIOS_ROM_DATA);
92}
93
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000094static uint8_t atahpt_chip_readb(const struct flashctx *flash,
95 const chipaddr addr)
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000096{
97 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
98 return INB(io_base_addr + BIOS_ROM_DATA);
99}
Andrew Morgana0743832011-07-25 22:07:05 +0000100
101#else
102#error PCI port I/O access is not supported on this architecture yet.
103#endif