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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000018 *
Uwe Hermannd1107642007-08-29 17:52:32 +000019 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000022 */
23
24#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000025
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000026#define MAX_REFLASH_TRIES 0x10
27
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000028/* Check one byte for odd parity */
29uint8_t oddparity(uint8_t val)
30{
31 val = (val ^ (val >> 4)) & 0xf;
32 val = (val ^ (val >> 2)) & 0x3;
33 return (val ^ (val >> 1)) & 0x1;
34}
35
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000036void toggle_ready_jedec(chipaddr dst)
Uwe Hermann51582f22007-08-23 10:20:40 +000037{
38 unsigned int i = 0;
39 uint8_t tmp1, tmp2;
40
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000041 tmp1 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000042
43 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000044 tmp2 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000045 if (tmp1 == tmp2) {
46 break;
47 }
48 tmp1 = tmp2;
49 }
50}
51
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000052void data_polling_jedec(chipaddr dst, uint8_t data)
Uwe Hermann51582f22007-08-23 10:20:40 +000053{
54 unsigned int i = 0;
55 uint8_t tmp;
56
57 data &= 0x80;
58
59 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000060 tmp = chip_readb(dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000061 if (tmp == data) {
62 break;
63 }
64 }
65}
66
Michael Karcher972cec22009-11-26 14:50:52 +000067void start_program_jedec(chipaddr bios)
Uwe Hermann51582f22007-08-23 10:20:40 +000068{
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000069 chip_writeb(0xAA, bios + 0x5555);
70 chip_writeb(0x55, bios + 0x2AAA);
71 chip_writeb(0xA0, bios + 0x5555);
Uwe Hermann51582f22007-08-23 10:20:40 +000072}
73
Ollie Lho761bf1b2004-03-20 16:46:10 +000074int probe_jedec(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000075{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000076 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000077 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +000078 uint32_t largeid1, largeid2;
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +000079 uint32_t flashcontent1, flashcontent2;
Maciej Pijankac6e11112009-06-03 14:46:22 +000080 int probe_timing_enter, probe_timing_exit;
81
82 if (flash->probe_timing > 0)
83 probe_timing_enter = probe_timing_exit = flash->probe_timing;
84 else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */
85 probe_timing_enter = probe_timing_exit = 0;
86 } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */
87 printf_debug("Chip lacks correct probe timing information, "
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +000088 "using default 10mS/40uS. ");
Maciej Pijankac6e11112009-06-03 14:46:22 +000089 probe_timing_enter = 10000;
90 probe_timing_exit = 40;
91 } else {
92 printf("Chip has negative value in probe_timing, failing "
93 "without chip access\n");
94 return 0;
95 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000096
Ollie Lho761bf1b2004-03-20 16:46:10 +000097 /* Issue JEDEC Product ID Entry command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000098 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000099 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000100 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000101 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000102 chip_writeb(0x90, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000103 programmer_delay(probe_timing_enter);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000104
Ollie Lho761bf1b2004-03-20 16:46:10 +0000105 /* Read product ID */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000106 id1 = chip_readb(bios);
107 id2 = chip_readb(bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000108 largeid1 = id1;
109 largeid2 = id2;
110
111 /* Check if it is a continuation ID, this should be a while loop. */
112 if (id1 == 0x7F) {
113 largeid1 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000114 id1 = chip_readb(bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000115 largeid1 |= id1;
116 }
117 if (id2 == 0x7F) {
118 largeid2 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000119 id2 = chip_readb(bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000120 largeid2 |= id2;
121 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000122
Ollie Lho761bf1b2004-03-20 16:46:10 +0000123 /* Issue JEDEC Product ID Exit command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000124 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000125 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000126 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000127 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000128 chip_writeb(0xF0, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000129 programmer_delay(probe_timing_exit);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000130
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000131 printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000132 if (!oddparity(id1))
133 printf_debug(", id1 parity violation");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000134
135 /* Read the product ID location again. We should now see normal flash contents. */
136 flashcontent1 = chip_readb(bios);
137 flashcontent2 = chip_readb(bios + 0x01);
138
139 /* Check if it is a continuation ID, this should be a while loop. */
140 if (flashcontent1 == 0x7F) {
141 flashcontent1 <<= 8;
142 flashcontent1 |= chip_readb(bios + 0x100);
143 }
144 if (flashcontent2 == 0x7F) {
145 flashcontent2 <<= 8;
146 flashcontent2 |= chip_readb(bios + 0x101);
147 }
148
149 if (largeid1 == flashcontent1)
150 printf_debug(", id1 is normal flash content");
151 if (largeid2 == flashcontent2)
152 printf_debug(", id2 is normal flash content");
153
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000154 printf_debug("\n");
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000155 if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000156 return 1;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000157
Ollie Lho761bf1b2004-03-20 16:46:10 +0000158 return 0;
Ollie Lho73eca802004-03-19 22:10:07 +0000159}
160
Carl-Daniel Hailfingera06287c2009-09-23 22:01:33 +0000161int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize)
Ollie Lho73eca802004-03-19 22:10:07 +0000162{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000163 chipaddr bios = flash->virtual_memory;
164
Ollie Lho761bf1b2004-03-20 16:46:10 +0000165 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000166 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000167 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000168 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000169 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000170 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000171 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000172
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000173 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000174 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000175 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000176 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000177 chip_writeb(0x30, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000178 programmer_delay(10);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000179
Ollie Lho73eca802004-03-19 22:10:07 +0000180 /* wait for Toggle bit ready */
181 toggle_ready_jedec(bios);
182
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000183 if (check_erased_range(flash, page, pagesize)) {
184 fprintf(stderr,"ERASE FAILED!\n");
185 return -1;
186 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000187 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000188}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000189
Carl-Daniel Hailfingera06287c2009-09-23 22:01:33 +0000190int erase_block_jedec(struct flashchip *flash, unsigned int block, unsigned int blocksize)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000191{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000192 chipaddr bios = flash->virtual_memory;
193
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000194 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000195 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000196 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000197 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000198 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000199 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000200 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000201
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000202 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000203 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000204 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000205 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000206 chip_writeb(0x50, bios + block);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000207 programmer_delay(10);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000208
209 /* wait for Toggle bit ready */
210 toggle_ready_jedec(bios);
211
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000212 if (check_erased_range(flash, block, blocksize)) {
213 fprintf(stderr,"ERASE FAILED!\n");
214 return -1;
215 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000216 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000217}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000218
Ollie Lho761bf1b2004-03-20 16:46:10 +0000219int erase_chip_jedec(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000220{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000221 int total_size = flash->total_size * 1024;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000222 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000223
Ollie Lho761bf1b2004-03-20 16:46:10 +0000224 /* Issue the JEDEC Chip Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000225 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000226 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000227 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000228 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000229 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000230 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000231
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000232 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000233 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000234 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000235 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000236 chip_writeb(0x10, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000237 programmer_delay(10);
Ollie Lho73eca802004-03-19 22:10:07 +0000238
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000239 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000240
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000241 if (check_erased_range(flash, 0, total_size)) {
242 fprintf(stderr,"ERASE FAILED!\n");
243 return -1;
244 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000245 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000246}
247
Urja Rannikko0c854c02009-06-25 13:57:31 +0000248int write_page_write_jedec(struct flashchip *flash, uint8_t *src,
249 int start, int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000250{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000251 int i, tried = 0, failed;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000252 uint8_t *s = src;
Urja Rannikko0c854c02009-06-25 13:57:31 +0000253 chipaddr bios = flash->virtual_memory;
254 chipaddr dst = bios + start;
255 chipaddr d = dst;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000256
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000257retry:
Ollie Lho761bf1b2004-03-20 16:46:10 +0000258 /* Issue JEDEC Data Unprotect comand */
Michael Karcher972cec22009-11-26 14:50:52 +0000259 start_program_jedec(bios);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000260
Ollie Lho98bea8a2004-12-07 03:15:51 +0000261 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000262 for (i = 0; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000263 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000264 if (*src != 0xFF)
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000265 chip_writeb(*src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000266 dst++;
267 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000268 }
269
Ollie Lho761bf1b2004-03-20 16:46:10 +0000270 toggle_ready_jedec(dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000271
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000272 dst = d;
273 src = s;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000274 failed = verify_range(flash, src, start, page_size, NULL);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000275
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000276 if (failed && tried++ < MAX_REFLASH_TRIES) {
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000277 fprintf(stderr, "retrying.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000278 goto retry;
279 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000280 if (failed) {
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000281 fprintf(stderr, " page 0x%lx failed!\n",
282 (d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000283 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000284 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000285}
286
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000287int write_byte_program_jedec(chipaddr bios, uint8_t *src,
288 chipaddr dst)
Ollie Lho070647d2004-03-22 22:19:17 +0000289{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000290 int tried = 0, failed = 0;
Ollie Lho1b8b6602004-12-08 02:10:33 +0000291
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000292 /* If the data is 0xFF, don't program it and don't complain. */
Ollie Lho070647d2004-03-22 22:19:17 +0000293 if (*src == 0xFF) {
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000294 return 0;
Ollie Lho070647d2004-03-22 22:19:17 +0000295 }
Ollie Lho98bea8a2004-12-07 03:15:51 +0000296
Ollie Lho1b8b6602004-12-08 02:10:33 +0000297retry:
Ollie Lho070647d2004-03-22 22:19:17 +0000298 /* Issue JEDEC Byte Program command */
Michael Karcher972cec22009-11-26 14:50:52 +0000299 start_program_jedec(bios);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000300
301 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000302 chip_writeb(*src, dst);
Ollie Lho070647d2004-03-22 22:19:17 +0000303 toggle_ready_jedec(bios);
Ollie Lho8b8897a2004-03-27 00:18:15 +0000304
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000305 if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000306 goto retry;
307 }
Ollie Lho1b8b6602004-12-08 02:10:33 +0000308
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000309 if (tried >= MAX_REFLASH_TRIES)
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000310 failed = 1;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000311
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000312 return failed;
Ollie Lho070647d2004-03-22 22:19:17 +0000313}
314
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000315int write_sector_jedec(chipaddr bios, uint8_t *src,
316 chipaddr dst, unsigned int page_size)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000317{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000318 int i, failed = 0;
319 chipaddr olddst;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000320
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000321 olddst = dst;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000322 for (i = 0; i < page_size; i++) {
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000323 if (write_byte_program_jedec(bios, src, dst))
324 failed = 1;
Ollie Lho8b8897a2004-03-27 00:18:15 +0000325 dst++, src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000326 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000327 if (failed)
328 fprintf(stderr, " writing sector at 0x%lx failed!\n", olddst);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000329
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000330 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000331}
332
Ollie Lho184a4042005-11-26 21:55:36 +0000333int write_jedec(struct flashchip *flash, uint8_t *buf)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000334{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000335 int i, failed = 0;
Ollie Lho070647d2004-03-22 22:19:17 +0000336 int total_size = flash->total_size * 1024;
337 int page_size = flash->page_size;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000338
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000339 if (erase_chip_jedec(flash)) {
340 fprintf(stderr,"ERASE FAILED!\n");
341 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000342 }
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000343
Uwe Hermanna502dce2007-10-17 23:55:15 +0000344 printf("Programming page: ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000345 for (i = 0; i < total_size / page_size; i++) {
346 printf("%04d at address: 0x%08x", i, i * page_size);
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000347 if (write_page_write_jedec(flash, buf + i * page_size,
348 i * page_size, page_size))
349 failed = 1;
Ollie Lho070647d2004-03-22 22:19:17 +0000350 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000351 }
352 printf("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000353
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000354 return failed;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000355}