Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d22a1d4 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 5 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 10 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 15 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include "flash.h" |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 22 | #include "chipdrivers.h" |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 23 | |
Michael Karcher | 1c296ca | 2009-11-27 17:49:42 +0000 | [diff] [blame] | 24 | /* WARNING! |
| 25 | This chip uses the standard JEDEC Addresses in 16-bit mode as word |
| 26 | addresses. In byte mode, 0xAAA has to be used instead of 0x555 and |
| 27 | 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC |
| 28 | functions. */ |
| 29 | |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 30 | int write_page_m29f400bt(struct flashchip *flash, uint8_t *src, int start, int len) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 31 | { |
| 32 | int i; |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 33 | chipaddr bios = flash->virtual_memory; |
| 34 | chipaddr dst = flash->virtual_memory + start; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 35 | |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 36 | for (i = 0; i < len; i++) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 37 | chip_writeb(0xAA, bios + 0xAAA); |
| 38 | chip_writeb(0x55, bios + 0x555); |
| 39 | chip_writeb(0xA0, bios + 0xAAA); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 40 | |
| 41 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 42 | chip_writeb(*src, dst); |
Uwe Hermann | fd37414 | 2007-08-23 15:20:38 +0000 | [diff] [blame] | 43 | toggle_ready_jedec(dst); |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 44 | #if 0 |
| 45 | /* We only want to print something in the error case. */ |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 46 | msg_cerr("Value in the flash at address 0x%lx = %#x, want %#x\n", |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 47 | (dst - bios), chip_readb(dst), *src); |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 48 | #endif |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 49 | dst++; |
| 50 | src++; |
| 51 | } |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 52 | |
| 53 | /* FIXME: Ignore errors for now. */ |
| 54 | return 0; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 55 | } |
| 56 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 57 | int probe_m29f400bt(struct flashchip *flash) |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 58 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 59 | chipaddr bios = flash->virtual_memory; |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 60 | uint8_t id1, id2; |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 61 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 62 | chip_writeb(0xAA, bios + 0xAAA); |
| 63 | chip_writeb(0x55, bios + 0x555); |
| 64 | chip_writeb(0x90, bios + 0xAAA); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 65 | |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 66 | programmer_delay(10); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 67 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 68 | id1 = chip_readb(bios); |
Carl-Daniel Hailfinger | c2a1845 | 2007-12-31 01:18:26 +0000 | [diff] [blame] | 69 | /* The data sheet says id2 is at (bios + 0x01) and id2 listed in |
| 70 | * flash.h does not match. It should be possible to use JEDEC probe. |
| 71 | */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 72 | id2 = chip_readb(bios + 0x02); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 73 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 74 | chip_writeb(0xAA, bios + 0xAAA); |
| 75 | chip_writeb(0x55, bios + 0x555); |
| 76 | chip_writeb(0xF0, bios + 0xAAA); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 77 | |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 78 | programmer_delay(10); |
Ronald G. Minnich | d4228fd | 2003-02-28 17:21:38 +0000 | [diff] [blame] | 79 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 80 | msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); |
Ronald G. Minnich | d4228fd | 2003-02-28 17:21:38 +0000 | [diff] [blame] | 81 | |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 82 | if (id1 == flash->manufacture_id && id2 == flash->model_id) |
| 83 | return 1; |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 88 | int erase_m29f400bt(struct flashchip *flash) |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 89 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 90 | chipaddr bios = flash->virtual_memory; |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 91 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 92 | chip_writeb(0xAA, bios + 0xAAA); |
| 93 | chip_writeb(0x55, bios + 0x555); |
| 94 | chip_writeb(0x80, bios + 0xAAA); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 95 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 96 | chip_writeb(0xAA, bios + 0xAAA); |
| 97 | chip_writeb(0x55, bios + 0x555); |
| 98 | chip_writeb(0x10, bios + 0xAAA); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 99 | |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 100 | programmer_delay(10); |
Uwe Hermann | fd37414 | 2007-08-23 15:20:38 +0000 | [diff] [blame] | 101 | toggle_ready_jedec(bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 102 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 103 | if (check_erased_range(flash, 0, flash->total_size * 1024)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 104 | msg_cerr("ERASE FAILED!\n"); |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 105 | return -1; |
| 106 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 107 | return 0; |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 108 | } |
| 109 | |
Sean Nelson | 6b11ad2 | 2009-12-23 17:05:59 +0000 | [diff] [blame] | 110 | int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len) |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 111 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 112 | chipaddr bios = flash->virtual_memory; |
| 113 | chipaddr dst = bios + start; |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 114 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 115 | chip_writeb(0xAA, bios + 0xAAA); |
| 116 | chip_writeb(0x55, bios + 0x555); |
| 117 | chip_writeb(0x80, bios + 0xAAA); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 118 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 119 | chip_writeb(0xAA, bios + 0xAAA); |
| 120 | chip_writeb(0x55, bios + 0x555); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 121 | chip_writeb(0x30, dst); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 122 | |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 123 | programmer_delay(10); |
Uwe Hermann | fd37414 | 2007-08-23 15:20:38 +0000 | [diff] [blame] | 124 | toggle_ready_jedec(bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 125 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 126 | if (check_erased_range(flash, start, len)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 127 | msg_cerr("ERASE FAILED!\n"); |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 128 | return -1; |
| 129 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 130 | return 0; |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 131 | } |
| 132 | |
Sean Nelson | 6b11ad2 | 2009-12-23 17:05:59 +0000 | [diff] [blame] | 133 | int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int address, unsigned int blocklen) |
| 134 | { |
| 135 | if ((address != 0) || (blocklen != flash->total_size * 1024)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 136 | msg_cerr("%s called with incorrect arguments\n", |
Sean Nelson | 6b11ad2 | 2009-12-23 17:05:59 +0000 | [diff] [blame] | 137 | __func__); |
| 138 | return -1; |
| 139 | } |
| 140 | return erase_m29f400bt(flash); |
| 141 | } |
| 142 | |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame^] | 143 | /* chunksize is 1 */ |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 144 | int write_m29f400bt(struct flashchip *flash, uint8_t *buf) |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 145 | { |
Carl-Daniel Hailfinger | 184b95f | 2010-10-10 16:10:49 +0000 | [diff] [blame] | 146 | return write_page_m29f400bt(flash, buf, 0, flash->total_size * 1024); |
Ronald G. Minnich | b193490 | 2002-06-11 19:15:55 +0000 | [diff] [blame] | 147 | } |