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Ronald G. Minnichb1934902002-06-11 19:15:55 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnichb1934902002-06-11 19:15:55 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnichb1934902002-06-11 19:15:55 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnichb1934902002-06-11 19:15:55 +000019 */
20
21#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000022#include "chipdrivers.h"
Ronald G. Minnichb1934902002-06-11 19:15:55 +000023
Michael Karcher1c296ca2009-11-27 17:49:42 +000024/* WARNING!
25 This chip uses the standard JEDEC Addresses in 16-bit mode as word
26 addresses. In byte mode, 0xAAA has to be used instead of 0x555 and
27 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC
28 functions. */
29
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000030int write_page_m29f400bt(struct flashchip *flash, uint8_t *src, int start, int len)
Uwe Hermann51582f22007-08-23 10:20:40 +000031{
32 int i;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000033 chipaddr bios = flash->virtual_memory;
34 chipaddr dst = flash->virtual_memory + start;
Uwe Hermann51582f22007-08-23 10:20:40 +000035
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000036 for (i = 0; i < len; i++) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000037 chip_writeb(0xAA, bios + 0xAAA);
38 chip_writeb(0x55, bios + 0x555);
39 chip_writeb(0xA0, bios + 0xAAA);
Uwe Hermann51582f22007-08-23 10:20:40 +000040
41 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000042 chip_writeb(*src, dst);
Uwe Hermannfd374142007-08-23 15:20:38 +000043 toggle_ready_jedec(dst);
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000044#if 0
45 /* We only want to print something in the error case. */
Sean Nelsoned479d22010-03-24 23:14:32 +000046 msg_cerr("Value in the flash at address 0x%lx = %#x, want %#x\n",
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000047 (dst - bios), chip_readb(dst), *src);
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000048#endif
Uwe Hermann51582f22007-08-23 10:20:40 +000049 dst++;
50 src++;
51 }
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000052
53 /* FIXME: Ignore errors for now. */
54 return 0;
Uwe Hermann51582f22007-08-23 10:20:40 +000055}
56
Ollie Lho761bf1b2004-03-20 16:46:10 +000057int probe_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000058{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000059 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000060 uint8_t id1, id2;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000061
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000062 chip_writeb(0xAA, bios + 0xAAA);
63 chip_writeb(0x55, bios + 0x555);
64 chip_writeb(0x90, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000065
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000066 programmer_delay(10);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000067
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000068 id1 = chip_readb(bios);
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +000069 /* The data sheet says id2 is at (bios + 0x01) and id2 listed in
70 * flash.h does not match. It should be possible to use JEDEC probe.
71 */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000072 id2 = chip_readb(bios + 0x02);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000073
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000074 chip_writeb(0xAA, bios + 0xAAA);
75 chip_writeb(0x55, bios + 0x555);
76 chip_writeb(0xF0, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000077
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000078 programmer_delay(10);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000079
Sean Nelsoned479d22010-03-24 23:14:32 +000080 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000081
Ronald G. Minnichb1934902002-06-11 19:15:55 +000082 if (id1 == flash->manufacture_id && id2 == flash->model_id)
83 return 1;
84
85 return 0;
86}
87
Ollie Lho761bf1b2004-03-20 16:46:10 +000088int erase_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000089{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000090 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000091
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000092 chip_writeb(0xAA, bios + 0xAAA);
93 chip_writeb(0x55, bios + 0x555);
94 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000095
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000096 chip_writeb(0xAA, bios + 0xAAA);
97 chip_writeb(0x55, bios + 0x555);
98 chip_writeb(0x10, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000099
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000100 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +0000101 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000102
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000103 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000104 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000105 return -1;
106 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000107 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000108}
109
Sean Nelson6b11ad22009-12-23 17:05:59 +0000110int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000111{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000112 chipaddr bios = flash->virtual_memory;
113 chipaddr dst = bios + start;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000114
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000115 chip_writeb(0xAA, bios + 0xAAA);
116 chip_writeb(0x55, bios + 0x555);
117 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000118
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000119 chip_writeb(0xAA, bios + 0xAAA);
120 chip_writeb(0x55, bios + 0x555);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000121 chip_writeb(0x30, dst);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000122
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000123 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +0000124 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000125
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000126 if (check_erased_range(flash, start, len)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000127 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000128 return -1;
129 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000130 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000131}
132
Sean Nelson6b11ad22009-12-23 17:05:59 +0000133int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int address, unsigned int blocklen)
134{
135 if ((address != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000136 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson6b11ad22009-12-23 17:05:59 +0000137 __func__);
138 return -1;
139 }
140 return erase_m29f400bt(flash);
141}
142
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000143/* chunksize is 1 */
Ollie Lho184a4042005-11-26 21:55:36 +0000144int write_m29f400bt(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000145{
Carl-Daniel Hailfinger184b95f2010-10-10 16:10:49 +0000146 return write_page_m29f400bt(flash, buf, 0, flash->total_size * 1024);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000147}