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Mark Marshall90021f22010-12-03 14:48:11 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Mark Marshall
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Mark Marshall90021f22010-12-03 14:48:11 +000014 */
15
16#include <stdlib.h>
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000017#include <strings.h>
Mark Marshall90021f22010-12-03 14:48:11 +000018#include <string.h>
19#include "flash.h"
20#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000021#include "hwaccess.h"
Thomas Heijligena0655202021-12-14 16:36:05 +010022#include "hwaccess_x86_io.h"
Thomas Heijligen74b4aa02021-12-14 17:52:30 +010023#include "hwaccess_physmap.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010024#include "platform/pci.h"
Mark Marshall90021f22010-12-03 14:48:11 +000025
26#define PCI_VENDOR_ID_OGP 0x1227
27
28/* These are the register addresses for the OGD1 / OGA1. If they are
29 * different for later versions of the hardware then we will need
30 * logic to select between the different hardware versions. */
31#define OGA1_XP10_BPROM_SI 0x0040 /* W */
32#define OGA1_XP10_BPROM_SO 0x0040 /* R */
33#define OGA1_XP10_BPROM_CE_BAR 0x0044 /* W */
34#define OGA1_XP10_BPROM_SCK 0x0048 /* W */
35#define OGA1_XP10_BPROM_REG_SEL 0x004C /* W */
36#define OGA1_XP10_CPROM_SI 0x0050 /* W */
37#define OGA1_XP10_CPROM_SO 0x0050 /* R */
38#define OGA1_XP10_CPROM_CE_BAR 0x0054 /* W */
39#define OGA1_XP10_CPROM_SCK 0x0058 /* W */
40#define OGA1_XP10_CPROM_REG_SEL 0x005C /* W */
41
42static uint8_t *ogp_spibar;
43
44static uint32_t ogp_reg_sel;
45static uint32_t ogp_reg_siso;
46static uint32_t ogp_reg__ce;
47static uint32_t ogp_reg_sck;
48
Thomas Heijligencc853d82021-05-04 15:32:17 +020049static const struct dev_entry ogp_spi[] = {
Mark Marshall90021f22010-12-03 14:48:11 +000050 {PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"},
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000051
52 {0},
Mark Marshall90021f22010-12-03 14:48:11 +000053};
54
55static void ogp_request_spibus(void)
56{
57 pci_mmio_writel(1, ogp_spibar + ogp_reg_sel);
58}
59
60static void ogp_release_spibus(void)
61{
62 pci_mmio_writel(0, ogp_spibar + ogp_reg_sel);
63}
64
65static void ogp_bitbang_set_cs(int val)
66{
67 pci_mmio_writel(val, ogp_spibar + ogp_reg__ce);
68}
69
70static void ogp_bitbang_set_sck(int val)
71{
72 pci_mmio_writel(val, ogp_spibar + ogp_reg_sck);
73}
74
75static void ogp_bitbang_set_mosi(int val)
76{
77 pci_mmio_writel(val, ogp_spibar + ogp_reg_siso);
78}
79
80static int ogp_bitbang_get_miso(void)
81{
82 uint32_t tmp;
83
84 tmp = pci_mmio_readl(ogp_spibar + ogp_reg_siso);
85 return tmp & 0x1;
86}
87
88static const struct bitbang_spi_master bitbang_spi_master_ogp = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020089 .set_cs = ogp_bitbang_set_cs,
90 .set_sck = ogp_bitbang_set_sck,
91 .set_mosi = ogp_bitbang_set_mosi,
92 .get_miso = ogp_bitbang_get_miso,
93 .request_bus = ogp_request_spibus,
94 .release_bus = ogp_release_spibus,
95 .half_period = 0,
Mark Marshall90021f22010-12-03 14:48:11 +000096};
97
Thomas Heijligencc853d82021-05-04 15:32:17 +020098static int ogp_spi_init(void)
Mark Marshall90021f22010-12-03 14:48:11 +000099{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000100 struct pci_dev *dev = NULL;
Mark Marshall90021f22010-12-03 14:48:11 +0000101 char *type;
102
103 type = extract_programmer_param("rom");
104
105 if (!type) {
106 msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
107 "which flashchip you want to access.\n");
108 return 1;
109 } else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
110 ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL;
111 ogp_reg_siso = OGA1_XP10_BPROM_SI;
112 ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR;
113 ogp_reg_sck = OGA1_XP10_BPROM_SCK;
114 } else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
115 ogp_reg_sel = OGA1_XP10_CPROM_REG_SEL;
116 ogp_reg_siso = OGA1_XP10_CPROM_SI;
117 ogp_reg__ce = OGA1_XP10_CPROM_CE_BAR;
118 ogp_reg_sck = OGA1_XP10_CPROM_SCK;
119 } else {
120 msg_perr("Invalid or missing rom= parameter.\n");
Stefan Reinauera9c23422014-04-26 16:11:50 +0000121 free(type);
Mark Marshall90021f22010-12-03 14:48:11 +0000122 return 1;
123 }
Stefan Reinauera9c23422014-04-26 16:11:50 +0000124 free(type);
Mark Marshall90021f22010-12-03 14:48:11 +0000125
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000126 if (rget_io_perms())
127 return 1;
Mark Marshall90021f22010-12-03 14:48:11 +0000128
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000129 dev = pcidev_init(ogp_spi, PCI_BASE_ADDRESS_0);
130 if (!dev)
131 return 1;
Mark Marshall90021f22010-12-03 14:48:11 +0000132
Stefan Tauner0ccec8f2014-06-01 23:49:03 +0000133 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000134 if (!io_base_addr)
135 return 1;
136
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000137 ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096);
138 if (ogp_spibar == ERROR_PTR)
David Hendricks8bb20212011-06-14 01:35:36 +0000139 return 1;
140
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000141 if (register_spi_bitbang_master(&bitbang_spi_master_ogp))
Mark Marshall90021f22010-12-03 14:48:11 +0000142 return 1;
143
Mark Marshall90021f22010-12-03 14:48:11 +0000144 return 0;
145}
Thomas Heijligencc853d82021-05-04 15:32:17 +0200146
147const struct programmer_entry programmer_ogp_spi = {
148 .name = "ogp_spi",
149 .type = PCI,
150 .devs.dev = ogp_spi,
151 .init = ogp_spi_init,
152 .map_flash_region = fallback_map,
153 .unmap_flash_region = fallback_unmap,
154 .delay = internal_delay,
155};