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Mark Marshall90021f22010-12-03 14:48:11 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Mark Marshall
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Mark Marshall90021f22010-12-03 14:48:11 +000014 */
15
16#include <stdlib.h>
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000017#include <strings.h>
Mark Marshall90021f22010-12-03 14:48:11 +000018#include <string.h>
19#include "flash.h"
20#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000021#include "hwaccess.h"
Thomas Heijligena0655202021-12-14 16:36:05 +010022#include "hwaccess_x86_io.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010023#include "platform/pci.h"
Mark Marshall90021f22010-12-03 14:48:11 +000024
25#define PCI_VENDOR_ID_OGP 0x1227
26
27/* These are the register addresses for the OGD1 / OGA1. If they are
28 * different for later versions of the hardware then we will need
29 * logic to select between the different hardware versions. */
30#define OGA1_XP10_BPROM_SI 0x0040 /* W */
31#define OGA1_XP10_BPROM_SO 0x0040 /* R */
32#define OGA1_XP10_BPROM_CE_BAR 0x0044 /* W */
33#define OGA1_XP10_BPROM_SCK 0x0048 /* W */
34#define OGA1_XP10_BPROM_REG_SEL 0x004C /* W */
35#define OGA1_XP10_CPROM_SI 0x0050 /* W */
36#define OGA1_XP10_CPROM_SO 0x0050 /* R */
37#define OGA1_XP10_CPROM_CE_BAR 0x0054 /* W */
38#define OGA1_XP10_CPROM_SCK 0x0058 /* W */
39#define OGA1_XP10_CPROM_REG_SEL 0x005C /* W */
40
41static uint8_t *ogp_spibar;
42
43static uint32_t ogp_reg_sel;
44static uint32_t ogp_reg_siso;
45static uint32_t ogp_reg__ce;
46static uint32_t ogp_reg_sck;
47
Thomas Heijligencc853d82021-05-04 15:32:17 +020048static const struct dev_entry ogp_spi[] = {
Mark Marshall90021f22010-12-03 14:48:11 +000049 {PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"},
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000050
51 {0},
Mark Marshall90021f22010-12-03 14:48:11 +000052};
53
54static void ogp_request_spibus(void)
55{
56 pci_mmio_writel(1, ogp_spibar + ogp_reg_sel);
57}
58
59static void ogp_release_spibus(void)
60{
61 pci_mmio_writel(0, ogp_spibar + ogp_reg_sel);
62}
63
64static void ogp_bitbang_set_cs(int val)
65{
66 pci_mmio_writel(val, ogp_spibar + ogp_reg__ce);
67}
68
69static void ogp_bitbang_set_sck(int val)
70{
71 pci_mmio_writel(val, ogp_spibar + ogp_reg_sck);
72}
73
74static void ogp_bitbang_set_mosi(int val)
75{
76 pci_mmio_writel(val, ogp_spibar + ogp_reg_siso);
77}
78
79static int ogp_bitbang_get_miso(void)
80{
81 uint32_t tmp;
82
83 tmp = pci_mmio_readl(ogp_spibar + ogp_reg_siso);
84 return tmp & 0x1;
85}
86
87static const struct bitbang_spi_master bitbang_spi_master_ogp = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020088 .set_cs = ogp_bitbang_set_cs,
89 .set_sck = ogp_bitbang_set_sck,
90 .set_mosi = ogp_bitbang_set_mosi,
91 .get_miso = ogp_bitbang_get_miso,
92 .request_bus = ogp_request_spibus,
93 .release_bus = ogp_release_spibus,
94 .half_period = 0,
Mark Marshall90021f22010-12-03 14:48:11 +000095};
96
Thomas Heijligencc853d82021-05-04 15:32:17 +020097static int ogp_spi_init(void)
Mark Marshall90021f22010-12-03 14:48:11 +000098{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000099 struct pci_dev *dev = NULL;
Mark Marshall90021f22010-12-03 14:48:11 +0000100 char *type;
101
102 type = extract_programmer_param("rom");
103
104 if (!type) {
105 msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
106 "which flashchip you want to access.\n");
107 return 1;
108 } else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
109 ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL;
110 ogp_reg_siso = OGA1_XP10_BPROM_SI;
111 ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR;
112 ogp_reg_sck = OGA1_XP10_BPROM_SCK;
113 } else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
114 ogp_reg_sel = OGA1_XP10_CPROM_REG_SEL;
115 ogp_reg_siso = OGA1_XP10_CPROM_SI;
116 ogp_reg__ce = OGA1_XP10_CPROM_CE_BAR;
117 ogp_reg_sck = OGA1_XP10_CPROM_SCK;
118 } else {
119 msg_perr("Invalid or missing rom= parameter.\n");
Stefan Reinauera9c23422014-04-26 16:11:50 +0000120 free(type);
Mark Marshall90021f22010-12-03 14:48:11 +0000121 return 1;
122 }
Stefan Reinauera9c23422014-04-26 16:11:50 +0000123 free(type);
Mark Marshall90021f22010-12-03 14:48:11 +0000124
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000125 if (rget_io_perms())
126 return 1;
Mark Marshall90021f22010-12-03 14:48:11 +0000127
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000128 dev = pcidev_init(ogp_spi, PCI_BASE_ADDRESS_0);
129 if (!dev)
130 return 1;
Mark Marshall90021f22010-12-03 14:48:11 +0000131
Stefan Tauner0ccec8f2014-06-01 23:49:03 +0000132 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000133 if (!io_base_addr)
134 return 1;
135
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000136 ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096);
137 if (ogp_spibar == ERROR_PTR)
David Hendricks8bb20212011-06-14 01:35:36 +0000138 return 1;
139
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000140 if (register_spi_bitbang_master(&bitbang_spi_master_ogp))
Mark Marshall90021f22010-12-03 14:48:11 +0000141 return 1;
142
Mark Marshall90021f22010-12-03 14:48:11 +0000143 return 0;
144}
Thomas Heijligencc853d82021-05-04 15:32:17 +0200145
146const struct programmer_entry programmer_ogp_spi = {
147 .name = "ogp_spi",
148 .type = PCI,
149 .devs.dev = ogp_spi,
150 .init = ogp_spi_init,
151 .map_flash_region = fallback_map,
152 .unmap_flash_region = fallback_unmap,
153 .delay = internal_delay,
154};