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review.sourcearcade.org / flashprog / 63fd9026f1e82b67a65072fda862ba7af35839e1 / . / sst28sf040.c
blob: ca401648dd0fb9085cc1a24533ba02e9c604e77e [file] [log] [blame]
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]1/*
Uwe Hermannd1107642007-08-29 17:52:32 +0000[diff] [blame]2 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]3 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +0000[diff] [blame]4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005 coresystems GmbH <stepan@openbios.org>
Sean Nelson51c83fb2010-01-20 20:55:53 +0000[diff] [blame]6 * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]7 *
Uwe Hermannd1107642007-08-29 17:52:32 +0000[diff] [blame]8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]12 *
Uwe Hermannd1107642007-08-29 17:52:32 +0000[diff] [blame]13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]17 *
Uwe Hermannd1107642007-08-29 17:52:32 +0000[diff] [blame]18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]21 */
22
23#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +0000[diff] [blame]24#include "chipdrivers.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]25
26#define AUTO_PG_ERASE1 0x20
27#define AUTO_PG_ERASE2 0xD0
Ollie Lhocf29de82004-03-18 19:40:07 +0000[diff] [blame]28#define AUTO_PGRM 0x10
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]29#define CHIP_ERASE 0x30
30#define RESET 0xFF
31#define READ_ID 0x90
32
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000[diff] [blame^]33int protect_28sf040(struct flashctx *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]34{
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000[diff] [blame]35 chipaddr bios = flash->virtual_memory;
36
Stefan Reinauer9e72aa52009-09-16 08:18:08 +0000[diff] [blame]37 chip_readb(bios + 0x1823);
38 chip_readb(bios + 0x1820);
39 chip_readb(bios + 0x1822);
40 chip_readb(bios + 0x0418);
41 chip_readb(bios + 0x041B);
42 chip_readb(bios + 0x0419);
43 chip_readb(bios + 0x040A);
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000[diff] [blame]44
45 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]46}
47
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000[diff] [blame^]48int unprotect_28sf040(struct flashctx *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]49{
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000[diff] [blame]50 chipaddr bios = flash->virtual_memory;
51
Stefan Reinauer9e72aa52009-09-16 08:18:08 +0000[diff] [blame]52 chip_readb(bios + 0x1823);
53 chip_readb(bios + 0x1820);
54 chip_readb(bios + 0x1822);
55 chip_readb(bios + 0x0418);
56 chip_readb(bios + 0x041B);
57 chip_readb(bios + 0x0419);
58 chip_readb(bios + 0x041A);
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000[diff] [blame]59
60 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]61}
62
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000[diff] [blame^]63int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]64{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000[diff] [blame]65 chipaddr bios = flash->virtual_memory;
66
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000[diff] [blame]67 /* This command sequence is very similar to erase_block_82802ab. */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000[diff] [blame]68 chip_writeb(AUTO_PG_ERASE1, bios);
69 chip_writeb(AUTO_PG_ERASE2, bios + address);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]70
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000[diff] [blame]71 /* wait for Toggle bit ready */
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]72 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000[diff] [blame]73
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000[diff] [blame]74 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000[diff] [blame]75 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]76}
77
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000[diff] [blame]78/* chunksize is 1 */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000[diff] [blame^]79int write_28sf040(struct flashctx *flash, uint8_t *src, unsigned int start, unsigned int len)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]80{
81 int i;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000[diff] [blame]82 chipaddr bios = flash->virtual_memory;
83 chipaddr dst = flash->virtual_memory + start;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]84
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000[diff] [blame]85 for (i = 0; i < len; i++) {
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]86 /* transfer data from source to destination */
87 if (*src == 0xFF) {
88 dst++, src++;
89 /* If the data is 0xFF, don't program it */
90 continue;
91 }
92 /*issue AUTO PROGRAM command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000[diff] [blame]93 chip_writeb(AUTO_PGRM, dst);
94 chip_writeb(*src++, dst++);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]95
96 /* wait for Toggle bit ready */
97 toggle_ready_jedec(bios);
98 }
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000[diff] [blame]99
Uwe Hermannffec5f32007-08-23 16:08:21 +0000[diff] [blame]100 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]101}
102
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000[diff] [blame^]103static int erase_28sf040(struct flashctx *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]104{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000[diff] [blame]105 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]106
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000[diff] [blame]107 chip_writeb(CHIP_ERASE, bios);
108 chip_writeb(CHIP_ERASE, bios);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]109
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000[diff] [blame]110 programmer_delay(10);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]111 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000[diff] [blame]112
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000[diff] [blame]113 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000[diff] [blame]114 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000[diff] [blame]115}
116
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000[diff] [blame^]117int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
Sean Nelson51c83fb2010-01-20 20:55:53 +0000[diff] [blame]118{
119 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000[diff] [blame]120 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson51c83fb2010-01-20 20:55:53 +0000[diff] [blame]121 __func__);
122 return -1;
123 }
124 return erase_28sf040(flash);
125}