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Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010,2011 Carl-Daniel Hailfinger
5 * Written by Carl-Daniel Hailfinger for Angelbird Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000015 */
16
17/* Datasheets are not public (yet?) */
18
19#include <stdlib.h>
20#include "flash.h"
21#include "programmer.h"
Thomas Heijligena0655202021-12-14 16:36:05 +010022#include "hwaccess_x86_io.h"
Thomas Heijligen74b4aa02021-12-14 17:52:30 +010023#include "hwaccess_physmap.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010024#include "platform/pci.h"
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000025
Jacob Garberafc3ad62019-06-24 16:05:28 -060026static uint8_t *mv_bar;
27static uint16_t mv_iobar;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000028
Thomas Heijligencc853d82021-05-04 15:32:17 +020029static const struct dev_entry satas_mv[] = {
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000030 /* 88SX6041 and 88SX6042 are the same according to the datasheet. */
31 {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},
32
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000033 {0},
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000034};
35
36#define NVRAM_PARAM 0x1045c
37#define FLASH_PARAM 0x1046c
38#define EXPANSION_ROM_BAR_CONTROL 0x00d2c
39#define PCI_BAR2_CONTROL 0x00c08
40#define GPIO_PORT_CONTROL 0x104f0
41
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000042static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
43 chipaddr addr);
44static uint8_t satamv_chip_readb(const struct flashctx *flash,
45 const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000046static const struct par_master par_master_satamv = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020047 .chip_readb = satamv_chip_readb,
48 .chip_readw = fallback_chip_readw,
49 .chip_readl = fallback_chip_readl,
50 .chip_readn = fallback_chip_readn,
51 .chip_writeb = satamv_chip_writeb,
52 .chip_writew = fallback_chip_writew,
53 .chip_writel = fallback_chip_writel,
54 .chip_writen = fallback_chip_writen,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000055};
56
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000057/*
58 * Random notes:
59 * FCE# Flash Chip Enable
60 * FWE# Flash Write Enable
61 * FOE# Flash Output Enable
62 * FALE[1:0] Flash Address Latch Enable
63 * FAD[7:0] Flash Multiplexed Address/Data Bus
64 * FA[2:0] Flash Address Low
65 *
66 * GPIO[15,2] GPIO Port Mode
67 * GPIO[4:3] Flash Size
68 *
69 * 0xd2c Expansion ROM BAR Control
70 * 0xc08 PCI BAR2 (Flash/NVRAM) Control
71 * 0x1046c Flash Parameters
72 */
Thomas Heijligencc853d82021-05-04 15:32:17 +020073static int satamv_init(void)
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000074{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000075 struct pci_dev *dev = NULL;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000076 uintptr_t addr;
77 uint32_t tmp;
78
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000079 if (rget_io_perms())
80 return 1;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000081
82 /* BAR0 has all internal registers memory mapped. */
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000083 dev = pcidev_init(satas_mv, PCI_BASE_ADDRESS_0);
84 if (!dev)
85 return 1;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000086
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000087 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000088 if (!addr)
89 return 1;
90
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000091 mv_bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000092 if (mv_bar == ERROR_PTR)
Stefan Tauner55619552013-01-04 22:24:58 +000093 return 1;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000094
95 tmp = pci_mmio_readl(mv_bar + FLASH_PARAM);
96 msg_pspew("Flash Parameters:\n");
97 msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);
98 msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);
99 msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);
100 msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);
101 msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);
102 msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);
103 msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);
104 msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);
105 msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);
106 msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);
107 msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);
108 msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);
109 msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);
110 msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
111
112 tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL);
113 msg_pspew("Expansion ROM BAR Control:\n");
114 msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
115
116 /* Enable BAR2 mapping to flash */
117 tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL);
118 msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");
119 msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);
120 msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);
121 msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);
122 tmp &= 0xffffffc0;
123 tmp |= 0x0000001f;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000124 pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000125
126 /* Enable flash: GPIO Port Control Register 0x104f0 */
127 tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL);
128 msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);
129 if (((tmp >> 0) & 0x3) != 0x2)
130 msg_pinfo("Warning! Either the straps are incorrect or you "
131 "have no flash or someone overwrote the strap "
132 "values!\n");
133 tmp &= 0xfffffffc;
134 tmp |= 0x2;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000135 pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000136
137 /* Get I/O BAR location. */
Stefan Reinauer789ea5e2014-04-26 16:12:15 +0000138 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000139 if (!addr)
140 return 1;
141
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000142 /* Truncate to reachable range.
143 * FIXME: Check if the I/O BAR is actually reachable.
144 * This is an arch specific check.
145 */
Stefan Reinauer789ea5e2014-04-26 16:12:15 +0000146 mv_iobar = addr & 0xffff;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000147 msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
148
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000149 /* 512 kByte with two 8-bit latches, and
150 * 4 MByte with additional 3-bit latch. */
151 max_rom_decode.parallel = 4 * 1024 * 1024;
Anastasia Klimchukc1f2a472021-08-27 15:47:46 +1000152 return register_par_master(&par_master_satamv, BUS_PARALLEL, NULL);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000153}
154
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000155/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
156 * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
157 * This code only supports indirect accesses for now.
158 */
159
160/* Indirect access to via the I/O BAR1. */
161static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
162{
163 /* 0x80000000 selects BAR2 for remapping. */
164 OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
165 OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
166}
167
168/* Indirect access to via the I/O BAR1. */
169static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
170{
171 /* 0x80000000 selects BAR2 for remapping. */
172 OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
173 return INB(mv_iobar + 0x80 + (addr & 0x3));
174}
175
176/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000177static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
178 chipaddr addr)
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000179{
180 satamv_indirect_chip_writeb(val, addr);
181}
182
183/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000184static uint8_t satamv_chip_readb(const struct flashctx *flash,
185 const chipaddr addr)
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000186{
187 return satamv_indirect_chip_readb(addr);
188}
Andrew Morgana0743832011-07-25 22:07:05 +0000189
Thomas Heijligencc853d82021-05-04 15:32:17 +0200190const struct programmer_entry programmer_satamv = {
191 .name = "satamv",
192 .type = PCI,
193 .devs.dev = satas_mv,
194 .init = satamv_init,
Thomas Heijligencc853d82021-05-04 15:32:17 +0200195};