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Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000025#include "flash.h"
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000026#include "flashchips.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000027#include "chipdrivers.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000028#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000029
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000030enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000031
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +000032void spi_prettyprint_status_register(struct flashchip *flash);
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000033
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000034const struct spi_programmer spi_programmer[] = {
35 { /* SPI_CONTROLLER_NONE */
36 .command = NULL,
37 .multicommand = NULL,
38 .read = NULL,
39 .write_256 = NULL,
40 },
41
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +000042#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000043#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000044 { /* SPI_CONTROLLER_ICH7 */
45 .command = ich_spi_send_command,
46 .multicommand = ich_spi_send_multicommand,
47 .read = ich_spi_read,
48 .write_256 = ich_spi_write_256,
49 },
50
51 { /* SPI_CONTROLLER_ICH9 */
52 .command = ich_spi_send_command,
53 .multicommand = ich_spi_send_multicommand,
54 .read = ich_spi_read,
55 .write_256 = ich_spi_write_256,
56 },
57
58 { /* SPI_CONTROLLER_IT87XX */
59 .command = it8716f_spi_send_command,
60 .multicommand = default_spi_send_multicommand,
61 .read = it8716f_spi_chip_read,
62 .write_256 = it8716f_spi_chip_write_256,
63 },
64
65 { /* SPI_CONTROLLER_SB600 */
66 .command = sb600_spi_send_command,
67 .multicommand = default_spi_send_multicommand,
68 .read = sb600_spi_read,
69 .write_256 = sb600_spi_write_1,
70 },
71
72 { /* SPI_CONTROLLER_VIA */
73 .command = ich_spi_send_command,
74 .multicommand = ich_spi_send_multicommand,
75 .read = ich_spi_read,
76 .write_256 = ich_spi_write_256,
77 },
78
79 { /* SPI_CONTROLLER_WBSIO */
80 .command = wbsio_spi_send_command,
81 .multicommand = default_spi_send_multicommand,
82 .read = wbsio_spi_read,
83 .write_256 = wbsio_spi_write_1,
84 },
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +000085#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000086#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000087
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +000088#if CONFIG_FT2232_SPI == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000089 { /* SPI_CONTROLLER_FT2232 */
90 .command = ft2232_spi_send_command,
91 .multicommand = default_spi_send_multicommand,
92 .read = ft2232_spi_read,
93 .write_256 = ft2232_spi_write_256,
94 },
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +000095#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000096
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +000097#if CONFIG_DUMMY == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000098 { /* SPI_CONTROLLER_DUMMY */
99 .command = dummy_spi_send_command,
100 .multicommand = default_spi_send_multicommand,
Carl-Daniel Hailfinger1b0ba892010-06-20 10:58:32 +0000101 .read = dummy_spi_read,
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000102 .write_256 = NULL,
103 },
Carl-Daniel Hailfinger4740c6f2009-09-16 10:09:21 +0000104#endif
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000105
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000106#if CONFIG_BUSPIRATE_SPI == 1
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000107 { /* SPI_CONTROLLER_BUSPIRATE */
108 .command = buspirate_spi_send_command,
109 .multicommand = default_spi_send_multicommand,
110 .read = buspirate_spi_read,
Carl-Daniel Hailfinger408e47a2010-03-22 03:30:58 +0000111 .write_256 = buspirate_spi_write_256,
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000112 },
113#endif
114
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000115#if CONFIG_DEDIPROG == 1
Carl-Daniel Hailfingerd38fac82010-01-19 11:15:48 +0000116 { /* SPI_CONTROLLER_DEDIPROG */
117 .command = dediprog_spi_send_command,
118 .multicommand = default_spi_send_multicommand,
119 .read = dediprog_spi_read,
120 .write_256 = spi_chip_write_1,
121 },
122#endif
123
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000124 {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000125};
126
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000127const int spi_programmer_count = ARRAY_SIZE(spi_programmer);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000128
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000129int spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000130 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000131{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000132 if (!spi_programmer[spi_controller].command) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000133 msg_perr("%s called, but SPI is unsupported on this "
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000134 "hardware. Please report a bug at "
135 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000136 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000137 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000138
139 return spi_programmer[spi_controller].command(writecnt, readcnt,
140 writearr, readarr);
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000141}
142
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000143int spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000144{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000145 if (!spi_programmer[spi_controller].multicommand) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000146 msg_perr("%s called, but SPI is unsupported on this "
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000147 "hardware. Please report a bug at "
148 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000149 return 1;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000150 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000151
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000152 return spi_programmer[spi_controller].multicommand(cmds);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000153}
154
155int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
156 const unsigned char *writearr, unsigned char *readarr)
157{
158 struct spi_command cmd[] = {
159 {
160 .writecnt = writecnt,
161 .readcnt = readcnt,
162 .writearr = writearr,
163 .readarr = readarr,
164 }, {
165 .writecnt = 0,
166 .writearr = NULL,
167 .readcnt = 0,
168 .readarr = NULL,
169 }};
170
171 return spi_send_multicommand(cmd);
172}
173
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000174int default_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000175{
176 int result = 0;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000177 for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
178 result = spi_send_command(cmds->writecnt, cmds->readcnt,
179 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000180 }
181 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000182}
183
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000184int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000185{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000186 if (!spi_programmer[spi_controller].read) {
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000187 msg_perr("%s called, but SPI read is unsupported on this "
188 "hardware. Please report a bug at "
189 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000190 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000191 }
192
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000193 return spi_programmer[spi_controller].read(flash, buf, start, len);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000194}
195
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000196/*
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000197 * Program chip using page (256 bytes) programming.
198 * Some SPI masters can't do this, they use single byte programming instead.
199 */
Carl-Daniel Hailfinger8d497012009-05-09 02:34:18 +0000200int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000201{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000202 if (!spi_programmer[spi_controller].write_256) {
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000203 msg_perr("%s called, but SPI page write is unsupported on this "
204 "hardware. Please report a bug at "
205 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000206 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000207 }
208
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000209 return spi_programmer[spi_controller].write_256(flash, buf);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000210}
Peter Stugefd9217d2009-01-26 03:37:40 +0000211
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000212/*
213 * Get the lowest allowed address for read accesses. This often happens to
214 * be the lowest allowed address for all commands which take an address.
215 * This is a programmer limitation.
216 */
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000217uint32_t spi_get_valid_read_addr(void)
218{
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000219 switch (spi_controller) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000220#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000221#if defined(__i386__) || defined(__x86_64__)
222 case SPI_CONTROLLER_ICH7:
223 /* Return BBAR for ICH chipsets. */
224 return ichspi_bbar;
225#endif
226#endif
227 default:
228 return 0;
229 }
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000230}