blob: ec75a8aebd3904659dc3af29d78922553f22d144 [file] [log] [blame]
Stefan Tauner1e146392011-09-15 23:52:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
5 * Copyright (c) 2011 Stefan Tauner
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#if defined(__i386__) || defined(__x86_64__)
23
24#include "ich_descriptors.h"
Stefan Taunerb3850962011-12-24 00:00:32 +000025
26#ifdef ICH_DESCRIPTORS_FROM_DUMP
27
28#include <stdio.h>
29#define print(t, ...) printf(__VA_ARGS__)
30#define DESCRIPTOR_MODE_SIGNATURE 0x0ff0a55a
31/* The upper map is located in the word before the 256B-long OEM section at the
32 * end of the 4kB-long flash descriptor.
33 */
34#define UPPER_MAP_OFFSET (4096 - 256 - 4)
35#define getVTBA(flumap) (((flumap)->FLUMAP1 << 4) & 0x00000ff0)
36
37#else /* ICH_DESCRIPTORS_FROM_DUMP */
38
Stefan Tauner1e146392011-09-15 23:52:55 +000039#include "flash.h" /* for msg_* */
40#include "programmer.h"
41
Stefan Taunerb3850962011-12-24 00:00:32 +000042#endif /* ICH_DESCRIPTORS_FROM_DUMP */
43
44#ifndef min
45#define min(a, b) (a < b) ? a : b
46#endif
47
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +000048void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl)
Stefan Tauner1e146392011-09-15 23:52:55 +000049{
50 print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF);
51 print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF);
52 print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF);
53 print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +000054 print(verbosity, "EO=0x%x", (reg_val & VSCC_EO) >> VSCC_EO_OFF);
55 if (print_vcl)
56 print(verbosity, ", VCL=%d", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF);
57 print(verbosity, "\n");
Stefan Tauner1e146392011-09-15 23:52:55 +000058}
59
60#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0)
61#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0)
62#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0)
63#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0)
64#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0)
65
66void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc)
67{
68 prettyprint_ich_descriptor_content(&desc->content);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +000069 prettyprint_ich_descriptor_component(cs, desc);
Stefan Tauner1e146392011-09-15 23:52:55 +000070 prettyprint_ich_descriptor_region(desc);
71 prettyprint_ich_descriptor_master(&desc->master);
Stefan Taunerb3850962011-12-24 00:00:32 +000072#ifdef ICH_DESCRIPTORS_FROM_DUMP
73 if (cs >= CHIPSET_ICH8) {
74 prettyprint_ich_descriptor_upper_map(&desc->upper);
75 prettyprint_ich_descriptor_straps(cs, desc);
76 }
77#endif /* ICH_DESCRIPTORS_FROM_DUMP */
Stefan Tauner1e146392011-09-15 23:52:55 +000078}
79
80void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont)
81{
82 msg_pdbg2("=== Content Section ===\n");
83 msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG);
84 msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0);
85 msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1);
86 msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2);
87 msg_pdbg2("\n");
88
89 msg_pdbg2("--- Details ---\n");
Stefan Taunera1a14ec2012-08-13 08:45:13 +000090 msg_pdbg2("NR (Number of Regions): %5d\n", cont->NR + 1);
91 msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", getFRBA(cont));
92 msg_pdbg2("NC (Number of Components): %5d\n", cont->NC + 1);
93 msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", getFCBA(cont));
94 msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", cont->ISL);
95 msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", getFISBA(cont));
96 msg_pdbg2("NM (Number of Masters): %5d\n", cont->NM + 1);
97 msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", getFMBA(cont));
98 msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", cont->MSL);
99 msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", getFMSBA(cont));
Stefan Tauner1e146392011-09-15 23:52:55 +0000100 msg_pdbg2("\n");
101}
102
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000103static const char *pprint_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx)
104{
105 if (idx > 1) {
106 msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n");
107 return NULL;
108 }
109
110 if (desc->content.NC == 0 && idx > 0)
111 return "unused";
112
113 static const char * const size_str[] = {
114 "512 kB", /* 0000 */
115 "1 MB", /* 0001 */
116 "2 MB", /* 0010 */
117 "4 MB", /* 0011 */
118 "8 MB", /* 0100 */
119 "16 MB", /* 0101 */ /* Maximum up to Lynx Point (excl.) */
120 "32 MB", /* 0110 */
121 "64 MB", /* 0111 */
122 };
123
124 switch (cs) {
125 case CHIPSET_ICH8:
126 case CHIPSET_ICH9:
127 case CHIPSET_ICH10:
128 case CHIPSET_5_SERIES_IBEX_PEAK:
129 case CHIPSET_6_SERIES_COUGAR_POINT:
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000130 case CHIPSET_7_SERIES_PANTHER_POINT:
131 case CHIPSET_BAYTRAIL: {
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000132 uint8_t size_enc;
133 if (idx == 0) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000134 size_enc = desc->component.dens_old.comp1_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000135 } else {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000136 size_enc = desc->component.dens_old.comp2_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000137 }
138 if (size_enc > 5)
139 return "reserved";
140 return size_str[size_enc];
141 }
142 case CHIPSET_8_SERIES_LYNX_POINT:
143 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Duncan Laurie823096e2014-08-20 15:39:38 +0000144 case CHIPSET_8_SERIES_WELLSBURG:
145 case CHIPSET_9_SERIES_WILDCAT_POINT: {
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000146 uint8_t size_enc;
147 if (idx == 0) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000148 size_enc = desc->component.dens_new.comp1_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000149 } else {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000150 size_enc = desc->component.dens_new.comp2_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000151 }
152 if (size_enc > 7)
153 return "reserved";
154 return size_str[size_enc];
155 }
156 case CHIPSET_ICH_UNKNOWN:
157 default:
158 return "unknown";
159 }
160}
161
162static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
Stefan Tauner1e146392011-09-15 23:52:55 +0000163{
164 static const char * const freq_str[8] = {
165 "20 MHz", /* 000 */
166 "33 MHz", /* 001 */
167 "reserved", /* 010 */
168 "reserved", /* 011 */
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000169 "50 MHz", /* 100 */ /* New since Ibex Peak */
Stefan Tauner1e146392011-09-15 23:52:55 +0000170 "reserved", /* 101 */
171 "reserved", /* 110 */
172 "reserved" /* 111 */
173 };
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000174
175 switch (cs) {
176 case CHIPSET_ICH8:
177 case CHIPSET_ICH9:
178 case CHIPSET_ICH10:
179 if (value > 1)
180 return "reserved";
181 case CHIPSET_5_SERIES_IBEX_PEAK:
182 case CHIPSET_6_SERIES_COUGAR_POINT:
183 case CHIPSET_7_SERIES_PANTHER_POINT:
184 case CHIPSET_8_SERIES_LYNX_POINT:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000185 case CHIPSET_BAYTRAIL:
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000186 case CHIPSET_8_SERIES_LYNX_POINT_LP:
187 case CHIPSET_8_SERIES_WELLSBURG:
Duncan Laurie823096e2014-08-20 15:39:38 +0000188 case CHIPSET_9_SERIES_WILDCAT_POINT:
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000189 return freq_str[value];
190 case CHIPSET_ICH_UNKNOWN:
191 default:
192 return "unknown";
193 }
194}
195
196void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc)
197{
Stefan Tauner1e146392011-09-15 23:52:55 +0000198
199 msg_pdbg2("=== Component Section ===\n");
200 msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP);
201 msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL );
202 msg_pdbg2("\n");
203
204 msg_pdbg2("--- Details ---\n");
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000205 msg_pdbg2("Component 1 density: %s\n", pprint_density(cs, desc, 0));
Stefan Tauner1e146392011-09-15 23:52:55 +0000206 if (desc->content.NC)
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000207 msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1));
Stefan Tauner1e146392011-09-15 23:52:55 +0000208 else
209 msg_pdbg2("Component 2 is not used.\n");
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000210 msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.modes.freq_read));
211 msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_read_id));
212 msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_write));
213 msg_pdbg2("Fast Read is %ssupported.\n", desc->component.modes.fastread ? "" : "not ");
214 if (desc->component.modes.fastread)
Stefan Tauner1e146392011-09-15 23:52:55 +0000215 msg_pdbg2("Fast Read Clock Frequency: %s\n",
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000216 pprint_freq(cs, desc->component.modes.freq_fastread));
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000217 if (cs > CHIPSET_6_SERIES_COUGAR_POINT)
218 msg_pdbg2("Dual Output Fast Read Support: %sabled\n",
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000219 desc->component.modes.dual_output ? "dis" : "en");
Stefan Tauner1e146392011-09-15 23:52:55 +0000220 if (desc->component.FLILL == 0)
221 msg_pdbg2("No forbidden opcodes.\n");
222 else {
223 msg_pdbg2("Invalid instruction 0: 0x%02x\n",
224 desc->component.invalid_instr0);
225 msg_pdbg2("Invalid instruction 1: 0x%02x\n",
226 desc->component.invalid_instr1);
227 msg_pdbg2("Invalid instruction 2: 0x%02x\n",
228 desc->component.invalid_instr2);
229 msg_pdbg2("Invalid instruction 3: 0x%02x\n",
230 desc->component.invalid_instr3);
231 }
232 msg_pdbg2("\n");
233}
234
235static void pprint_freg(const struct ich_desc_region *reg, uint32_t i)
236{
237 static const char *const region_names[5] = {
238 "Descr.", "BIOS", "ME", "GbE", "Platf."
239 };
240 if (i >= 5) {
241 msg_pdbg2("%s: region index too high.\n", __func__);
242 return;
243 }
244 uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]);
245 uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]);
246 msg_pdbg2("Region %d (%-6s) ", i, region_names[i]);
247 if (base > limit)
248 msg_pdbg2("is unused.\n");
249 else
250 msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff);
251}
252
253void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc)
254{
255 uint8_t i;
256 uint8_t nr = desc->content.NR + 1;
257 msg_pdbg2("=== Region Section ===\n");
Stefan Tauner2abab942012-04-27 20:41:23 +0000258 if (nr > 5) {
Stefan Tauner1e146392011-09-15 23:52:55 +0000259 msg_pdbg2("%s: number of regions too high (%d).\n", __func__,
260 nr);
261 return;
262 }
Stefan Tauner0554ca52013-07-25 22:54:25 +0000263 for (i = 0; i < 5; i++)
Stefan Tauner1e146392011-09-15 23:52:55 +0000264 msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]);
265 msg_pdbg2("\n");
266
267 msg_pdbg2("--- Details ---\n");
Stefan Tauner0554ca52013-07-25 22:54:25 +0000268 for (i = 0; i < 5; i++)
Stefan Tauner1e146392011-09-15 23:52:55 +0000269 pprint_freg(&desc->region, i);
270 msg_pdbg2("\n");
271}
272
273void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr)
274{
275 msg_pdbg2("=== Master Section ===\n");
276 msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1);
277 msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2);
278 msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3);
279 msg_pdbg2("\n");
280
281 msg_pdbg2("--- Details ---\n");
282 msg_pdbg2(" Descr. BIOS ME GbE Platf.\n");
283 msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n",
284 (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ',
285 (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ',
286 (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ',
287 (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ',
288 (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' ');
289 msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n",
290 (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ',
291 (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ',
292 (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ',
293 (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ',
294 (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' ');
295 msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n",
296 (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ',
297 (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ',
298 (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ',
299 (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ',
300 (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' ');
301 msg_pdbg2("\n");
302}
303
Stefan Taunerb3850962011-12-24 00:00:32 +0000304#ifdef ICH_DESCRIPTORS_FROM_DUMP
305
306void prettyprint_ich_descriptor_straps_ich8(const struct ich_descriptors *desc)
307{
308 static const char * const str_GPIO12[4] = {
309 "GPIO12",
310 "LAN PHY Power Control Function (Native Output)",
311 "GLAN_DOCK# (Native Input)",
312 "invalid configuration",
313 };
314
315 msg_pdbg2("--- MCH details ---\n");
316 msg_pdbg2("ME B is %sabled.\n", desc->north.ich8.MDB ? "dis" : "en");
317 msg_pdbg2("\n");
318
319 msg_pdbg2("--- ICH details ---\n");
320 msg_pdbg2("ME SMBus Address 1: 0x%02x\n", desc->south.ich8.ASD);
321 msg_pdbg2("ME SMBus Address 2: 0x%02x\n", desc->south.ich8.ASD2);
322 msg_pdbg2("ME SMBus Controller is connected to the %s.\n",
323 desc->south.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins");
324 msg_pdbg2("SPI CS1 is used for %s.\n",
325 desc->south.ich8.SPICS1_LANPHYPC_SEL ?
326 "LAN PHY Power Control Function" :
327 "SPI Chip Select");
328 msg_pdbg2("GPIO12 is used as %s.\n",
329 str_GPIO12[desc->south.ich8.GPIO12_SEL]);
330 msg_pdbg2("PCIe Port 6 is used for %s.\n",
331 desc->south.ich8.GLAN_PCIE_SEL ? "integrated LAN" : "PCI Express");
332 msg_pdbg2("%sn BMC Mode: "
333 "Intel AMT SMBus Controller 1 is connected to %s.\n",
334 desc->south.ich8.BMCMODE ? "I" : "Not i",
335 desc->south.ich8.BMCMODE ? "SMLink" : "SMBus");
336 msg_pdbg2("TCO is in %s Mode.\n",
337 desc->south.ich8.TCOMODE ? "Advanced TCO" : "Legacy/Compatible");
338 msg_pdbg2("ME A is %sabled.\n",
339 desc->south.ich8.ME_DISABLE ? "dis" : "en");
340 msg_pdbg2("\n");
341}
342
343static void prettyprint_ich_descriptor_straps_56_pciecs(uint8_t conf, uint8_t off)
344{
345 msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1);
346
347 off *= 4;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000348 switch (conf){
Stefan Taunerb3850962011-12-24 00:00:32 +0000349 case 0:
350 msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off);
351 break;
352 case 1:
353 msg_pdbg2("1x2, 2x1 Port %d (x2), Port %d (disabled), "
354 "Ports %d, %d (x1)", 1+off, 2+off, 3+off, 4+off);
355 break;
356 case 2:
357 msg_pdbg2("2x2 Port %d (x2), Port %d (x2), Ports "
358 "%d, %d (disabled)", 1+off, 3+off, 2+off, 4+off);
359 break;
360 case 3:
361 msg_pdbg2("1x4 Port %d (x4), Ports %d-%d (disabled)",
362 1+off, 2+off, 4+off);
363 break;
364 }
365 msg_pdbg2("\n");
366}
367
368void prettyprint_ich_descriptor_pchstraps45678_56(const struct ich_desc_south_strap *s)
369{
370 /* PCHSTRP4 */
371 msg_pdbg2("Intel PHY is %s.\n",
372 (s->ibex.PHYCON == 2) ? "connected" :
373 (s->ibex.PHYCON == 0) ? "disconnected" : "reserved");
374 msg_pdbg2("GbE MAC SMBus address is %sabled.\n",
375 s->ibex.GBEMAC_SMBUS_ADDR_EN ? "en" : "dis");
376 msg_pdbg2("GbE MAC SMBus address: 0x%02x\n",
377 s->ibex.GBEMAC_SMBUS_ADDR);
378 msg_pdbg2("GbE PHY SMBus address: 0x%02x\n",
379 s->ibex.GBEPHY_SMBUS_ADDR);
380
381 /* PCHSTRP5 */
382 /* PCHSTRP6 */
383 /* PCHSTRP7 */
384 msg_pdbg2("Intel ME SMBus Subsystem Vendor ID: 0x%04x\n",
385 s->ibex.MESMA2UDID_VENDOR);
386 msg_pdbg2("Intel ME SMBus Subsystem Device ID: 0x%04x\n",
387 s->ibex.MESMA2UDID_VENDOR);
388
389 /* PCHSTRP8 */
390}
391
392void prettyprint_ich_descriptor_pchstraps111213_56(const struct ich_desc_south_strap *s)
393{
394 /* PCHSTRP11 */
395 msg_pdbg2("SMLink1 GP Address is %sabled.\n",
396 s->ibex.SML1GPAEN ? "en" : "dis");
397 msg_pdbg2("SMLink1 controller General Purpose Target address: 0x%02x\n",
398 s->ibex.SML1GPA);
399 msg_pdbg2("SMLink1 I2C Target address is %sabled.\n",
400 s->ibex.SML1I2CAEN ? "en" : "dis");
401 msg_pdbg2("SMLink1 I2C Target address: 0x%02x\n",
402 s->ibex.SML1I2CA);
403
404 /* PCHSTRP12 */
405 /* PCHSTRP13 */
406}
407
408void prettyprint_ich_descriptor_straps_ibex(const struct ich_desc_south_strap *s)
409{
Stefan Tauner67d163d2013-01-15 17:37:48 +0000410 static const uint8_t dec_t209min[4] = {
Stefan Taunerb3850962011-12-24 00:00:32 +0000411 100,
412 50,
413 5,
414 1
415 };
416
417 msg_pdbg2("--- PCH ---\n");
418
419 /* PCHSTRP0 */
420 msg_pdbg2("Chipset configuration Softstrap 2: %d\n", s->ibex.cs_ss2);
421 msg_pdbg2("Intel ME SMBus Select is %sabled.\n",
422 s->ibex.SMB_EN ? "en" : "dis");
423 msg_pdbg2("SMLink0 segment is %sabled.\n",
424 s->ibex.SML0_EN ? "en" : "dis");
425 msg_pdbg2("SMLink1 segment is %sabled.\n",
426 s->ibex.SML1_EN ? "en" : "dis");
427 msg_pdbg2("SMLink1 Frequency: %s\n",
428 (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved");
429 msg_pdbg2("Intel ME SMBus Frequency: %s\n",
430 (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved");
431 msg_pdbg2("SMLink0 Frequency: %s\n",
432 (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved");
433 msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ?
434 "LAN_PHY_PWR_CTRL" : "general purpose output");
435 msg_pdbg2("Chipset configuration Softstrap 1: %d\n", s->ibex.cs_ss1);
436 msg_pdbg2("DMI RequesterID Checks are %sabled.\n",
437 s->ibex.DMI_REQID_DIS ? "en" : "dis");
438 msg_pdbg2("BIOS Boot-Block size (BBBS): %d kB.\n",
439 1 << (6 + s->ibex.BBBS));
440
441 /* PCHSTRP1 */
442 msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3);
443
444 /* PCHSTRP2 */
445 msg_pdbg2("ME SMBus ASD address is %sabled.\n",
446 s->ibex.MESMASDEN ? "en" : "dis");
447 msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n",
448 s->ibex.MESMASDA);
449 msg_pdbg2("ME SMBus I2C address is %sabled.\n",
450 s->ibex.MESMI2CEN ? "en" : "dis");
451 msg_pdbg2("ME SMBus I2C target address: 0x%02x\n",
452 s->ibex.MESMI2CA);
453
454 /* PCHSTRP3 */
455 prettyprint_ich_descriptor_pchstraps45678_56(s);
456 /* PCHSTRP9 */
457 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 0);
458 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 1);
459 msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n",
460 s->ibex.PCIELR1 ? "" : "not ");
461 msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n",
462 s->ibex.PCIELR2 ? "" : "not ");
463 msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n",
464 s->ibex.DMILR ? "" : "not ");
465 msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1);
466 msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n",
467 s->ibex.PHY_PCIE_EN ? "en" : "dis");
468
469 /* PCHSTRP10 */
470 msg_pdbg2("Management Engine will boot from %sflash.\n",
471 s->ibex.ME_BOOT_FLASH ? "" : "ROM, then ");
472 msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->ibex.cs_ss5);
473 msg_pdbg2("Virtualization Engine Enable 1 is %sabled.\n",
474 s->ibex.VE_EN ? "en" : "dis");
475 msg_pdbg2("ME Memory-attached Debug Display Device is %sabled.\n",
476 s->ibex.MMDDE ? "en" : "dis");
477 msg_pdbg2("ME Memory-attached Debug Display Device address: 0x%02x\n",
478 s->ibex.MMADDR);
479 msg_pdbg2("Chipset configuration Softstrap 7: %d\n", s->ibex.cs_ss7);
480 msg_pdbg2("Integrated Clocking Configuration is %d.\n",
481 (s->ibex.ICC_SEL == 7) ? 0 : s->ibex.ICC_SEL);
482 msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a "
483 "reset.\n", s->ibex.MER_CL1 ? "" : "not ");
484
485 prettyprint_ich_descriptor_pchstraps111213_56(s);
486
487 /* PCHSTRP14 */
488 msg_pdbg2("Virtualization Engine Enable 2 is %sabled.\n",
489 s->ibex.VE_EN2 ? "en" : "dis");
490 msg_pdbg2("Virtualization Engine will boot from %sflash.\n",
491 s->ibex.VE_BOOT_FLASH ? "" : "ROM, then ");
492 msg_pdbg2("Braidwood SSD functionality is %sabled.\n",
493 s->ibex.BW_SSD ? "en" : "dis");
494 msg_pdbg2("Braidwood NVMHCI functionality is %sabled.\n",
495 s->ibex.NVMHCI_EN ? "en" : "dis");
496
497 /* PCHSTRP15 */
498 msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->ibex.cs_ss6);
499 msg_pdbg2("Integrated wired LAN Solution is %sabled.\n",
500 s->ibex.IWL_EN ? "en" : "dis");
501 msg_pdbg2("t209 min Timing: %d ms\n",
502 dec_t209min[s->ibex.t209min]);
503 msg_pdbg2("\n");
504}
505
506void prettyprint_ich_descriptor_straps_cougar(const struct ich_desc_south_strap *s)
507{
508 msg_pdbg2("--- PCH ---\n");
509
510 /* PCHSTRP0 */
511 msg_pdbg2("Chipset configuration Softstrap 1: %d\n", s->cougar.cs_ss1);
512 msg_pdbg2("Intel ME SMBus Select is %sabled.\n",
513 s->ibex.SMB_EN ? "en" : "dis");
514 msg_pdbg2("SMLink0 segment is %sabled.\n",
515 s->ibex.SML0_EN ? "en" : "dis");
516 msg_pdbg2("SMLink1 segment is %sabled.\n",
517 s->ibex.SML1_EN ? "en" : "dis");
518 msg_pdbg2("SMLink1 Frequency: %s\n",
519 (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved");
520 msg_pdbg2("Intel ME SMBus Frequency: %s\n",
521 (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved");
522 msg_pdbg2("SMLink0 Frequency: %s\n",
523 (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved");
524 msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ?
525 "LAN_PHY_PWR_CTRL" : "general purpose output");
526 msg_pdbg2("LinkSec is %sabled.\n",
527 s->cougar.LINKSEC_DIS ? "en" : "dis");
528 msg_pdbg2("DMI RequesterID Checks are %sabled.\n",
529 s->ibex.DMI_REQID_DIS ? "en" : "dis");
530 msg_pdbg2("BIOS Boot-Block size (BBBS): %d kB.\n",
531 1 << (6 + s->ibex.BBBS));
532
533 /* PCHSTRP1 */
534 msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3);
535 msg_pdbg2("Chipset configuration Softstrap 2: 0x%x\n", s->ibex.cs_ss2);
536
537 /* PCHSTRP2 */
538 msg_pdbg2("ME SMBus ASD address is %sabled.\n",
539 s->ibex.MESMASDEN ? "en" : "dis");
540 msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n",
541 s->ibex.MESMASDA);
542 msg_pdbg2("ME SMBus MCTP Address is %sabled.\n",
543 s->cougar.MESMMCTPAEN ? "en" : "dis");
544 msg_pdbg2("ME SMBus MCTP target address: 0x%02x\n",
545 s->cougar.MESMMCTPA);
546 msg_pdbg2("ME SMBus I2C address is %sabled.\n",
547 s->ibex.MESMI2CEN ? "en" : "dis");
548 msg_pdbg2("ME SMBus I2C target address: 0x%02x\n",
549 s->ibex.MESMI2CA);
550
551 /* PCHSTRP3 */
552 prettyprint_ich_descriptor_pchstraps45678_56(s);
553 /* PCHSTRP9 */
554 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 0);
555 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 1);
556 msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n",
557 s->ibex.PCIELR1 ? "" : "not ");
558 msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n",
559 s->ibex.PCIELR2 ? "" : "not ");
560 msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n",
561 s->ibex.DMILR ? "" : "not ");
562 msg_pdbg2("ME Debug status writes over SMBUS are %sabled.\n",
563 s->cougar.MDSMBE_EN ? "en" : "dis");
564 msg_pdbg2("ME Debug SMBus Emergency Mode address: 0x%02x (raw)\n",
565 s->cougar.MDSMBE_ADD);
566 msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1);
567 msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n",
568 s->ibex.PHY_PCIE_EN ? "en" : "dis");
569 msg_pdbg2("PCIe ports Subtractive Decode Agent is %sabled.\n",
570 s->cougar.SUB_DECODE_EN ? "en" : "dis");
571 msg_pdbg2("GPIO74 is used as %s.\n", s->cougar.PCHHOT_SML1ALERT_SEL ?
572 "PCHHOT#" : "SML1ALERT#");
573
574 /* PCHSTRP10 */
575 msg_pdbg2("Management Engine will boot from %sflash.\n",
576 s->ibex.ME_BOOT_FLASH ? "" : "ROM, then ");
577
578 msg_pdbg2("ME Debug SMBus Emergency Mode is %sabled.\n",
579 s->cougar.MDSMBE_EN ? "en" : "dis");
580 msg_pdbg2("ME Debug SMBus Emergency Mode Address: 0x%02x\n",
581 s->cougar.MDSMBE_ADD);
582
583 msg_pdbg2("Integrated Clocking Configuration used: %d\n",
584 s->cougar.ICC_SEL);
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000585 msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a reset.\n",
586 s->ibex.MER_CL1 ? "" : "not ");
Stefan Taunerb3850962011-12-24 00:00:32 +0000587 msg_pdbg2("ICC Profile is selected by %s.\n",
588 s->cougar.ICC_PRO_SEL ? "Softstraps" : "BIOS");
589 msg_pdbg2("Deep SX is %ssupported on the platform.\n",
590 s->cougar.Deep_SX_EN ? "not " : "");
591 msg_pdbg2("ME Debug LAN Emergency Mode is %sabled.\n",
592 s->cougar.ME_DBG_LAN ? "en" : "dis");
593
594 prettyprint_ich_descriptor_pchstraps111213_56(s);
595
596 /* PCHSTRP14 */
597 /* PCHSTRP15 */
598 msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->cougar.cs_ss6);
599 msg_pdbg2("Integrated wired LAN is %sabled.\n",
600 s->cougar.IWL_EN ? "en" : "dis");
601 msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->cougar.cs_ss5);
602 msg_pdbg2("SMLink1 provides temperature from %s.\n",
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000603 s->cougar.SMLINK1_THERM_SEL ? "PCH only" : "the CPU, PCH and DIMMs");
Stefan Taunerb3850962011-12-24 00:00:32 +0000604 msg_pdbg2("GPIO29 is used as %s.\n", s->cougar.SLP_LAN_GP29_SEL ?
605 "general purpose output" : "SLP_LAN#");
606
607 /* PCHSTRP16 */
608 /* PCHSTRP17 */
609 msg_pdbg2("Integrated Clock: %s Clock Mode\n",
610 s->cougar.ICML ? "Buffered Through" : "Full Integrated");
611 msg_pdbg2("\n");
612}
613
614void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc)
615{
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000616 unsigned int i, max_count;
Stefan Taunerb3850962011-12-24 00:00:32 +0000617 msg_pdbg2("=== Softstraps ===\n");
618
619 if (sizeof(desc->north.STRPs) / 4 + 1 < desc->content.MSL) {
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000620 max_count = sizeof(desc->north.STRPs) / 4 + 1;
621 msg_pdbg2("MSL (%u) is greater than the current maximum of %u entries.\n",
622 desc->content.MSL, max_count + 1);
623 msg_pdbg2("Only the first %u entries will be printed.\n", max_count);
Stefan Taunerb3850962011-12-24 00:00:32 +0000624 } else
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000625 max_count = desc->content.MSL;
Stefan Taunerb3850962011-12-24 00:00:32 +0000626
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000627 msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max_count);
628 for (i = 0; i < max_count; i++)
Stefan Taunerb3850962011-12-24 00:00:32 +0000629 msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]);
630 msg_pdbg2("\n");
631
632 if (sizeof(desc->south.STRPs) / 4 < desc->content.ISL) {
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000633 max_count = sizeof(desc->south.STRPs) / 4;
634 msg_pdbg2("ISL (%u) is greater than the current maximum of %u entries.\n",
635 desc->content.ISL, max_count);
636 msg_pdbg2("Only the first %u entries will be printed.\n", max_count);
Stefan Taunerb3850962011-12-24 00:00:32 +0000637 } else
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000638 max_count = desc->content.ISL;
Stefan Taunerb3850962011-12-24 00:00:32 +0000639
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000640 msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max_count);
641 for (i = 0; i < max_count; i++)
Stefan Taunerb3850962011-12-24 00:00:32 +0000642 msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]);
643 msg_pdbg2("\n");
644
645 switch (cs) {
646 case CHIPSET_ICH8:
647 if (sizeof(desc->north.ich8) / 4 != desc->content.MSL)
648 msg_pdbg2("Detailed North/MCH/PROC information is "
649 "probably not reliable, printing anyway.\n");
650 if (sizeof(desc->south.ich8) / 4 != desc->content.ISL)
651 msg_pdbg2("Detailed South/ICH/PCH information is "
652 "probably not reliable, printing anyway.\n");
653 prettyprint_ich_descriptor_straps_ich8(desc);
654 break;
655 case CHIPSET_5_SERIES_IBEX_PEAK:
656 /* PCH straps only. PROCSTRPs are unknown. */
657 if (sizeof(desc->south.ibex) / 4 != desc->content.ISL)
658 msg_pdbg2("Detailed South/ICH/PCH information is "
659 "probably not reliable, printing anyway.\n");
660 prettyprint_ich_descriptor_straps_ibex(&desc->south);
661 break;
662 case CHIPSET_6_SERIES_COUGAR_POINT:
663 /* PCH straps only. PROCSTRP0 is "reserved". */
664 if (sizeof(desc->south.cougar) / 4 != desc->content.ISL)
665 msg_pdbg2("Detailed South/ICH/PCH information is "
666 "probably not reliable, printing anyway.\n");
667 prettyprint_ich_descriptor_straps_cougar(&desc->south);
668 break;
669 case CHIPSET_ICH_UNKNOWN:
670 break;
671 default:
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000672 msg_pdbg2("The meaning of the descriptor straps are unknown yet.\n\n");
Stefan Taunerb3850962011-12-24 00:00:32 +0000673 break;
674 }
675}
676
677void prettyprint_rdid(uint32_t reg_val)
678{
679 uint8_t mid = reg_val & 0xFF;
680 uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00);
681 msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did);
682}
683
684void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap)
685{
686 int i;
687 msg_pdbg2("=== Upper Map Section ===\n");
688 msg_pdbg2("FLUMAP1 0x%08x\n", umap->FLUMAP1);
689 msg_pdbg2("\n");
690
691 msg_pdbg2("--- Details ---\n");
692 msg_pdbg2("VTL (length in DWORDS) = %d\n", umap->VTL);
693 msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap));
694 msg_pdbg2("\n");
695
696 msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2);
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000697 for (i = 0; i < umap->VTL/2; i++) {
Stefan Taunerb3850962011-12-24 00:00:32 +0000698 uint32_t jid = umap->vscc_table[i].JID;
699 uint32_t vscc = umap->vscc_table[i].VSCC;
700 msg_pdbg2(" JID%d = 0x%08x\n", i, jid);
701 msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc);
702 msg_pdbg2(" "); /* indention */
703 prettyprint_rdid(jid);
704 msg_pdbg2(" "); /* indention */
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000705 prettyprint_ich_reg_vscc(vscc, 0, false);
Stefan Taunerb3850962011-12-24 00:00:32 +0000706 }
707 msg_pdbg2("\n");
708}
709
710/* len is the length of dump in bytes */
711int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc)
712{
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000713 unsigned int i, max_count;
Stefan Taunerb3850962011-12-24 00:00:32 +0000714 uint8_t pch_bug_offset = 0;
715
716 if (dump == NULL || desc == NULL)
717 return ICH_RET_PARAM;
718
719 if (dump[0] != DESCRIPTOR_MODE_SIGNATURE) {
720 if (dump[4] == DESCRIPTOR_MODE_SIGNATURE)
721 pch_bug_offset = 4;
722 else
723 return ICH_RET_ERR;
724 }
725
726 /* map */
Nico Huber9e14aed2017-03-28 17:08:46 +0200727 if (len < (4 + pch_bug_offset) * 4)
Stefan Taunerb3850962011-12-24 00:00:32 +0000728 return ICH_RET_OOB;
729 desc->content.FLVALSIG = dump[0 + pch_bug_offset];
730 desc->content.FLMAP0 = dump[1 + pch_bug_offset];
731 desc->content.FLMAP1 = dump[2 + pch_bug_offset];
732 desc->content.FLMAP2 = dump[3 + pch_bug_offset];
733
734 /* component */
Nico Huber9e14aed2017-03-28 17:08:46 +0200735 if (len < getFCBA(&desc->content) + 3 * 4)
Stefan Taunerb3850962011-12-24 00:00:32 +0000736 return ICH_RET_OOB;
737 desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0];
738 desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1];
739 desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2];
740
741 /* region */
Nico Huber9e14aed2017-03-28 17:08:46 +0200742 if (len < getFRBA(&desc->content) + 5 * 4)
Stefan Taunerb3850962011-12-24 00:00:32 +0000743 return ICH_RET_OOB;
744 desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0];
745 desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1];
746 desc->region.FLREGs[2] = dump[(getFRBA(&desc->content) >> 2) + 2];
747 desc->region.FLREGs[3] = dump[(getFRBA(&desc->content) >> 2) + 3];
748 desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4];
749
750 /* master */
Nico Huber9e14aed2017-03-28 17:08:46 +0200751 if (len < getFMBA(&desc->content) + 3 * 4)
Stefan Taunerb3850962011-12-24 00:00:32 +0000752 return ICH_RET_OOB;
753 desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0];
754 desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1];
755 desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2];
756
757 /* upper map */
758 desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0];
759
760 /* VTL is 8 bits long. Quote from the Ibex Peak SPI programming guide:
761 * "Identifies the 1s based number of DWORDS contained in the VSCC
762 * Table. Each SPI component entry in the table is 2 DWORDS long." So
763 * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A
764 * check ensures that the maximum offset actually accessed is available.
765 */
Nico Huber9e14aed2017-03-28 17:08:46 +0200766 if (len < getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8))
Stefan Taunerb3850962011-12-24 00:00:32 +0000767 return ICH_RET_OOB;
768
769 for (i = 0; i < desc->upper.VTL/2; i++) {
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000770 desc->upper.vscc_table[i].JID = dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0];
771 desc->upper.vscc_table[i].VSCC = dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1];
Stefan Taunerb3850962011-12-24 00:00:32 +0000772 }
773
774 /* MCH/PROC (aka. North) straps */
775 if (len < getFMSBA(&desc->content) + desc->content.MSL * 4)
776 return ICH_RET_OOB;
777
778 /* limit the range to be written */
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000779 max_count = min(sizeof(desc->north.STRPs) / 4, desc->content.MSL);
780 for (i = 0; i < max_count; i++)
781 desc->north.STRPs[i] = dump[(getFMSBA(&desc->content) >> 2) + i];
Stefan Taunerb3850962011-12-24 00:00:32 +0000782
783 /* ICH/PCH (aka. South) straps */
784 if (len < getFISBA(&desc->content) + desc->content.ISL * 4)
785 return ICH_RET_OOB;
786
787 /* limit the range to be written */
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000788 max_count = min(sizeof(desc->south.STRPs) / 4, desc->content.ISL);
789 for (i = 0; i < max_count; i++)
790 desc->south.STRPs[i] = dump[(getFISBA(&desc->content) >> 2) + i];
Stefan Taunerb3850962011-12-24 00:00:32 +0000791
792 return ICH_RET_OK;
793}
794
795#else /* ICH_DESCRIPTORS_FROM_DUMP */
796
Stefan Taunerd0c5dc22011-10-20 12:57:14 +0000797/** Returns the integer representation of the component density with index
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000798\em idx in bytes or -1 if the correct size can not be determined. */
799int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +0000800{
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000801 if (idx > 1) {
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000802 msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n");
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000803 return -1;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +0000804 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000805
806 if (desc->content.NC == 0 && idx > 0)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +0000807 return 0;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000808
809 uint8_t size_enc;
810 uint8_t size_max;
811
812 switch (cs) {
813 case CHIPSET_ICH8:
814 case CHIPSET_ICH9:
815 case CHIPSET_ICH10:
816 case CHIPSET_5_SERIES_IBEX_PEAK:
817 case CHIPSET_6_SERIES_COUGAR_POINT:
818 case CHIPSET_7_SERIES_PANTHER_POINT:
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000819 case CHIPSET_BAYTRAIL:
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000820 if (idx == 0) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000821 size_enc = desc->component.dens_old.comp1_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000822 } else {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000823 size_enc = desc->component.dens_old.comp2_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000824 }
825 size_max = 5;
826 break;
827 case CHIPSET_8_SERIES_LYNX_POINT:
828 case CHIPSET_8_SERIES_LYNX_POINT_LP:
829 case CHIPSET_8_SERIES_WELLSBURG:
Duncan Laurie823096e2014-08-20 15:39:38 +0000830 case CHIPSET_9_SERIES_WILDCAT_POINT:
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000831 if (idx == 0) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000832 size_enc = desc->component.dens_new.comp1_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000833 } else {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000834 size_enc = desc->component.dens_new.comp2_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000835 }
836 size_max = 7;
837 break;
838 case CHIPSET_ICH_UNKNOWN:
839 default:
840 msg_pwarn("Density encoding is unknown on this chipset.\n");
841 return -1;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +0000842 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000843
844 if (size_enc > size_max) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000845 msg_perr("Density of ICH SPI component with index %d is invalid.\n"
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000846 "Encoded density is 0x%x while maximum allowed is 0x%x.\n",
847 idx, size_enc, size_max);
848 return -1;
849 }
850
Stefan Taunerd0c5dc22011-10-20 12:57:14 +0000851 return (1 << (19 + size_enc));
852}
853
Stefan Tauner1e146392011-09-15 23:52:55 +0000854static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar)
855{
856 uint32_t control = 0;
857 control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS;
858 control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI;
859 mmio_le_writel(control, spibar + ICH9_REG_FDOC);
860 return mmio_le_readl(spibar + ICH9_REG_FDOD);
861}
862
863int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc)
864{
865 uint8_t i;
866 uint8_t nr;
867 struct ich_desc_region *r = &desc->region;
868
869 /* Test if bit-fields are working as expected.
870 * FIXME: Replace this with dynamic bitfield fixup
871 */
872 for (i = 0; i < 4; i++)
873 desc->region.FLREGs[i] = 0x5A << (i * 8);
874 if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 ||
875 r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 ||
876 r->reg2_base != 0x0000 || r->reg2_limit != 0x005A ||
877 r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) {
878 msg_pdbg("The combination of compiler and CPU architecture used"
879 "does not lay out bit-fields as expected, sorry.\n");
880 msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base);
881 msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit);
882 msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base);
883 msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit);
884 msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base);
885 msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit);
886 msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base);
887 msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit);
888 return ICH_RET_ERR;
889 }
890
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000891 msg_pdbg2("Reading flash descriptors mapped by the chipset via FDOC/FDOD...");
Stefan Tauner1e146392011-09-15 23:52:55 +0000892 /* content section */
893 desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar);
894 desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar);
895 desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar);
896 desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar);
897
898 /* component section */
899 desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar);
900 desc->component.FLILL = read_descriptor_reg(1, 1, spibar);
901 desc->component.FLPB = read_descriptor_reg(1, 2, spibar);
902
903 /* region section */
904 nr = desc->content.NR + 1;
Stefan Tauner2abab942012-04-27 20:41:23 +0000905 if (nr > 5) {
Stefan Tauner1e146392011-09-15 23:52:55 +0000906 msg_pdbg2("%s: number of regions too high (%d) - failed\n",
907 __func__, nr);
908 return ICH_RET_ERR;
909 }
Stefan Tauner0554ca52013-07-25 22:54:25 +0000910 for (i = 0; i < 5; i++)
Stefan Tauner1e146392011-09-15 23:52:55 +0000911 desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar);
912
913 /* master section */
914 desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar);
915 desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar);
916 desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar);
917
918 /* Accessing the strap section via FDOC/D is only possible on ICH8 and
919 * reading the upper map is impossible on all chipsets, so don't bother.
920 */
921
922 msg_pdbg2(" done.\n");
923 return ICH_RET_OK;
924}
Stefan Taunerb3850962011-12-24 00:00:32 +0000925#endif /* ICH_DESCRIPTORS_FROM_DUMP */
Stefan Tauner1e146392011-09-15 23:52:55 +0000926#endif /* defined(__i386__) || defined(__x86_64__) */