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Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Dominik Geyerb46acba2008-05-16 12:55:55 +00009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000023 */
24
25/*
26 * This module is designed for supporting the devices
27 * ST M25P40
28 * ST M25P80
29 * ST M25P16
30 * ST M25P32 already tested
31 * ST M25P64
32 * AT 25DF321 already tested
Helge Wagner738e2522010-10-05 22:06:05 +000033 * ... and many more SPI flash devices
Dominik Geyerb46acba2008-05-16 12:55:55 +000034 *
35 */
36
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000037#if defined(__i386__) || defined(__x86_64__)
38
Dominik Geyerb46acba2008-05-16 12:55:55 +000039#include <string.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000040#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000041#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000042#include "programmer.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000043#include "spi.h"
44
Stefan Reinauera9424d52008-06-27 16:28:34 +000045/* ICH9 controller register definition */
46#define ICH9_REG_FADDR 0x08 /* 32 Bits */
47#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
48
49#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000050#define SSFS_SCIP 0x00000001
51#define SSFS_CDS 0x00000004
52#define SSFS_FCERR 0x00000008
53#define SSFS_AEL 0x00000010
Stefan Reinauera9424d52008-06-27 16:28:34 +000054
55#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000056#define SSFC_SCGO 0x00000200
57#define SSFC_ACS 0x00000400
58#define SSFC_SPOP 0x00000800
59#define SSFC_COP 0x00001000
60#define SSFC_DBC 0x00010000
61#define SSFC_DS 0x00400000
62#define SSFC_SME 0x00800000
63#define SSFC_SCF 0x01000000
64#define SSFC_SCF_20MHZ 0x00000000
65#define SSFC_SCF_33MHZ 0x01000000
Stefan Reinauera9424d52008-06-27 16:28:34 +000066
67#define ICH9_REG_PREOP 0x94 /* 16 Bits */
68#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
69#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000070
71// ICH9R SPI commands
72#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
73#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
74#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
75#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
76
Stefan Reinauera9424d52008-06-27 16:28:34 +000077// ICH7 registers
78#define ICH7_REG_SPIS 0x00 /* 16 Bits */
79#define SPIS_SCIP 0x00000001
80#define SPIS_CDS 0x00000004
81#define SPIS_FCERR 0x00000008
82
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000083/* VIA SPI is compatible with ICH7, but maxdata
84 to transfer is 16 bytes.
85
86 DATA byte count on ICH7 is 8:13, on VIA 8:11
87
88 bit 12 is port select CS0 CS1
89 bit 13 is FAST READ enable
90 bit 7 is used with fast read and one shot controls CS de-assert?
91*/
92
Stefan Reinauera9424d52008-06-27 16:28:34 +000093#define ICH7_REG_SPIC 0x02 /* 16 Bits */
94#define SPIC_SCGO 0x0002
95#define SPIC_ACS 0x0004
96#define SPIC_SPOP 0x0008
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000097#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +000098
99#define ICH7_REG_SPIA 0x04 /* 32 Bits */
100#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
101#define ICH7_REG_PREOP 0x54 /* 16 Bits */
102#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
103#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
104
FENG yu ningc05a2952008-12-08 18:16:58 +0000105/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000106static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000107
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000108uint32_t ichspi_bbar = 0;
109
Michael Karchera4448d92010-07-22 18:04:15 +0000110static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000111
Dominik Geyerb46acba2008-05-16 12:55:55 +0000112typedef struct _OPCODE {
113 uint8_t opcode; //This commands spi opcode
114 uint8_t spi_type; //This commands spi type
115 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
116} OPCODE;
117
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000118/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000119 * Preop 1: Write Enable
120 * Preop 2: Write Status register enable
121 *
122 * OP 0: Write address
123 * OP 1: Read Address
124 * OP 2: ERASE block
125 * OP 3: Read Status register
126 * OP 4: Read ID
127 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000128 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000129 * OP 7: Chip erase
130 */
131typedef struct _OPCODES {
132 uint8_t preop[2];
133 OPCODE opcode[8];
134} OPCODES;
135
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000136static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000137
138/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000139static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000140{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000141 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000142}
143
Uwe Hermann09e04f72009-05-16 22:36:00 +0000144static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000145{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000146 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000147}
148
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000149#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X)
150#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X)
151#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000152
Dominik Geyerb46acba2008-05-16 12:55:55 +0000153/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000154static int find_opcode(OPCODES *op, uint8_t opcode);
155static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000156static int generate_opcodes(OPCODES * op);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000157static int program_opcodes(OPCODES * op);
Stefan Reinauer43119562008-11-02 19:51:50 +0000158static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000159 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000160
FENG yu ningf041e9b2008-12-15 02:32:11 +0000161/* for pairing opcodes with their required preop */
162struct preop_opcode_pair {
163 uint8_t preop;
164 uint8_t opcode;
165};
166
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000167/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000168const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000169 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
170 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
171 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
172 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
173 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
174 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000175 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
176 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000177 {JEDEC_EWSR, JEDEC_WRSR},
178 {0,}
179};
180
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000181/* Reasonable default configuration. Needs ad-hoc modifications if we
182 * encounter unlisted opcodes. Fun.
183 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000184static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000185 {
186 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000187 JEDEC_EWSR,
188 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000189 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000190 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000191 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000192 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000193 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000194 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000195 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000196 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000197 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
198 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000199};
200
Helge Wagner738e2522010-10-05 22:06:05 +0000201/* List of opcodes with their corresponding spi_type
202 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
203 * is needed which is currently not in the chipset OPCODE table
204 */
205static OPCODE POSSIBLE_OPCODES[] = {
206 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
207 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
208 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
209 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
210 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
211 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
212 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
213 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
214 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
215 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
216 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
217};
218
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000219static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000220
Helge Wagner738e2522010-10-05 22:06:05 +0000221static uint8_t lookup_spi_type(uint8_t opcode)
222{
223 int a;
224
225 for (a = 0; a < sizeof(POSSIBLE_OPCODES)/sizeof(POSSIBLE_OPCODES[0]); a++) {
226 if (POSSIBLE_OPCODES[a].opcode == opcode)
227 return POSSIBLE_OPCODES[a].spi_type;
228 }
229
230 return 0xFF;
231}
232
233static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
234{
235 uint8_t spi_type;
236
237 spi_type = lookup_spi_type(opcode);
238 if (spi_type > 3) {
239 /* Try to guess spi type from read/write sizes.
240 * The following valid writecnt/readcnt combinations exist:
241 * writecnt = 4, readcnt >= 0
242 * writecnt = 1, readcnt >= 0
243 * writecnt >= 4, readcnt = 0
244 * writecnt >= 1, readcnt = 0
245 * writecnt >= 1 is guaranteed for all commands.
246 */
247 if (readcnt == 0)
248 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
249 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
250 * bytes are actual the address, they go to the bus anyhow
251 */
252 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
253 else if (writecnt == 1) // and readcnt is > 0
254 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
255 else if (writecnt == 4) // and readcnt is > 0
256 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
257 // else we have an invalid case, will be handled below
258 }
259 if (spi_type <= 3) {
260 int oppos=2; // use original JEDEC_BE_D8 offset
261 curopcodes->opcode[oppos].opcode = opcode;
262 curopcodes->opcode[oppos].spi_type = spi_type;
263 program_opcodes(curopcodes);
264 oppos = find_opcode(curopcodes, opcode);
265 msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
266 return oppos;
267 }
268 return -1;
269}
270
Uwe Hermann09e04f72009-05-16 22:36:00 +0000271static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000272{
273 int a;
274
275 for (a = 0; a < 8; a++) {
276 if (op->opcode[a].opcode == opcode)
277 return a;
278 }
279
280 return -1;
281}
282
Uwe Hermann09e04f72009-05-16 22:36:00 +0000283static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000284{
285 int a;
286
287 for (a = 0; a < 2; a++) {
288 if (op->preop[a] == preop)
289 return a;
290 }
291
292 return -1;
293}
294
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000295/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000296static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000297{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000298 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000299 uint16_t preop, optype;
300 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000301
302 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000303 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000304 return -1;
305 }
306
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000307 switch (spi_controller) {
308 case SPI_CONTROLLER_ICH7:
309 case SPI_CONTROLLER_VIA:
FENG yu ningc05a2952008-12-08 18:16:58 +0000310 preop = REGREAD16(ICH7_REG_PREOP);
311 optype = REGREAD16(ICH7_REG_OPTYPE);
312 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
313 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
314 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000315 case SPI_CONTROLLER_ICH9:
FENG yu ningc05a2952008-12-08 18:16:58 +0000316 preop = REGREAD16(ICH9_REG_PREOP);
317 optype = REGREAD16(ICH9_REG_OPTYPE);
318 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
319 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
320 break;
321 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000322 msg_perr("%s: unsupported chipset\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000323 return -1;
324 }
325
326 op->preop[0] = (uint8_t) preop;
327 op->preop[1] = (uint8_t) (preop >> 8);
328
329 for (a = 0; a < 8; a++) {
330 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
331 optype >>= 2;
332 }
333
334 for (a = 0; a < 4; a++) {
335 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
336 opmenu[0] >>= 8;
337 }
338
339 for (a = 4; a < 8; a++) {
340 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
341 opmenu[1] >>= 8;
342 }
343
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000344 /* No preopcodes used by default. */
345 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000346 op->opcode[a].atomic = 0;
347
FENG yu ningc05a2952008-12-08 18:16:58 +0000348 return 0;
349}
350
Dominik Geyerb46acba2008-05-16 12:55:55 +0000351int program_opcodes(OPCODES * op)
352{
353 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000354 uint16_t preop, optype;
355 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000356
357 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000358 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000359 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000360 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000361 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000362
Stefan Reinauera9424d52008-06-27 16:28:34 +0000363 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000364 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000365 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000366 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000367 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000368
Stefan Reinauera9424d52008-06-27 16:28:34 +0000369 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000370 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000371 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000372 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000373 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000374
Dominik Geyerb46acba2008-05-16 12:55:55 +0000375 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000376 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000377 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000378 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000379 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000380
Sean Nelson316a29f2010-05-07 20:09:04 +0000381 msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000382 switch (spi_controller) {
383 case SPI_CONTROLLER_ICH7:
384 case SPI_CONTROLLER_VIA:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000385 REGWRITE16(ICH7_REG_PREOP, preop);
386 REGWRITE16(ICH7_REG_OPTYPE, optype);
387 REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
388 REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
389 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000390 case SPI_CONTROLLER_ICH9:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000391 REGWRITE16(ICH9_REG_PREOP, preop);
392 REGWRITE16(ICH9_REG_OPTYPE, optype);
393 REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
394 REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
395 break;
396 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000397 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000398 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000399 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000400
401 return 0;
402}
403
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000404/*
405 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
406 * it didn't stick.
407 */
408void ich_set_bbar(uint32_t minaddr)
409{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000410#define BBAR_MASK 0x00ffff00
411 minaddr &= BBAR_MASK;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000412 switch (spi_controller) {
413 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000414 case SPI_CONTROLLER_VIA:
415 ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK;
416 if (ichspi_bbar)
417 msg_pdbg("Reserved bits in BBAR not zero: 0x%04x",
418 ichspi_bbar);
419 ichspi_bbar |= minaddr;
420 mmio_writel(ichspi_bbar, ich_spibar + 0x50);
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000421 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000422 /* We don't have any option except complaining. */
423 if (ichspi_bbar != minaddr)
424 msg_perr("Setting BBAR failed!\n");
425 break;
426 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000427 ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK;
428 if (ichspi_bbar)
429 msg_pdbg("Reserved bits in BBAR not zero: 0x%04x",
430 ichspi_bbar);
431 ichspi_bbar |= minaddr;
432 mmio_writel(ichspi_bbar, ich_spibar + 0xA0);
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000433 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000434 /* We don't have any option except complaining. */
435 if (ichspi_bbar != minaddr)
436 msg_perr("Setting BBAR failed!\n");
437 break;
438 default:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000439 msg_perr("Unknown chipset for BBAR setting!\n");
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000440 break;
441 }
442}
443
FENG yu ningf041e9b2008-12-15 02:32:11 +0000444/* This function generates OPCODES from or programs OPCODES to ICH according to
445 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000446 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000447 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000448 */
Michael Karchera4448d92010-07-22 18:04:15 +0000449static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000450{
451 int rc = 0;
452 OPCODES *curopcodes_done;
453
454 if (curopcodes)
455 return 0;
456
457 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000458 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000459 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000460 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000461 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000462 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000463 curopcodes_done = &O_ST_M25P;
464 rc = program_opcodes(curopcodes_done);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000465 /* Technically not part of opcode init, but it allows opcodes
466 * to run without transaction errors by setting the lowest
467 * allowed address to zero.
468 */
469 ich_set_bbar(0);
FENG yu ningc05a2952008-12-08 18:16:58 +0000470 }
471
472 if (rc) {
473 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000474 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000475 return 1;
476 } else {
477 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000478 msg_pdbg("done\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000479 return 0;
480 }
481}
482
Stefan Reinauer43119562008-11-02 19:51:50 +0000483static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000484 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000485{
486 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000487 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000488 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000489 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000490 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000491 uint64_t opmenu;
492 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000493
494 /* Is it a write command? */
495 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
496 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
497 write_cmd = 1;
498 }
499
500 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000501 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000502
503 /* Program data into FDATA0 to N */
504 if (write_cmd && (datalength != 0)) {
505 temp32 = 0;
506 for (a = 0; a < datalength; a++) {
507 if ((a % 4) == 0) {
508 temp32 = 0;
509 }
510
511 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
512
513 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000514 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
515 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000516 }
517 }
518 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000519 REGWRITE32(ICH7_REG_SPID0 +
520 ((a - 1) - ((a - 1) % 4)), temp32);
521 }
522
523 }
524
525 /* Assemble SPIS */
526 temp16 = 0;
527 /* clear error status registers */
528 temp16 |= (SPIS_CDS + SPIS_FCERR);
529 REGWRITE16(ICH7_REG_SPIS, temp16);
530
531 /* Assemble SPIC */
532 temp16 = 0;
533
534 if (datalength != 0) {
535 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000536 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000537 }
538
539 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000540 opmenu = REGREAD32(ICH7_REG_OPMENU);
541 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
542
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000543 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
544 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000545 break;
546 }
547 opmenu >>= 8;
548 }
549 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000550 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000551 return 1;
552 }
553 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000554
555 /* Handle Atomic */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000556 switch (op.atomic) {
557 case 2:
558 /* Select second preop. */
559 temp16 |= SPIC_SPOP;
560 /* And fall through. */
561 case 1:
562 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000563 temp16 |= SPIC_ACS;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000564 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000565 }
566
567 /* Start */
568 temp16 |= SPIC_SCGO;
569
570 /* write it */
571 REGWRITE16(ICH7_REG_SPIC, temp16);
572
573 /* wait for cycle complete */
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000574 timeout = 100 * 1000 * 60; // 60s is a looong timeout.
Stefan Reinauera9424d52008-06-27 16:28:34 +0000575 while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000576 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000577 }
578 if (!timeout) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000579 msg_perr("timeout\n");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000580 }
581
Sean Nelson316a29f2010-05-07 20:09:04 +0000582 /* FIXME: make sure we do not needlessly cause transaction errors. */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000583 if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000584 msg_pdbg("Transaction error!\n");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000585 return 1;
586 }
587
588 if ((!write_cmd) && (datalength != 0)) {
589 for (a = 0; a < datalength; a++) {
590 if ((a % 4) == 0) {
591 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
592 }
593
594 data[a] =
595 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
596 >> ((a % 4) * 8);
597 }
598 }
599
600 return 0;
601}
602
Stefan Reinauer43119562008-11-02 19:51:50 +0000603static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000604 uint8_t datalength, uint8_t * data)
605{
606 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000607 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000608 uint32_t temp32;
609 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000610 uint64_t opmenu;
611 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000612
613 /* Is it a write command? */
614 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
615 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
616 write_cmd = 1;
617 }
618
619 /* Programm Offset in Flash into FADDR */
620 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
621
622 /* Program data into FDATA0 to N */
623 if (write_cmd && (datalength != 0)) {
624 temp32 = 0;
625 for (a = 0; a < datalength; a++) {
626 if ((a % 4) == 0) {
627 temp32 = 0;
628 }
629
630 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
631
632 if ((a % 4) == 3) {
633 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
634 temp32);
635 }
636 }
637 if (((a - 1) % 4) != 3) {
638 REGWRITE32(ICH9_REG_FDATA0 +
639 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000640 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000641 }
642
643 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000644 /* keep reserved bits (23-19,7,0) */
645 temp32 = REGREAD32(ICH9_REG_SSFS);
646 temp32 &= 0xF8008100;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000647
648 /* clear error status registers */
649 temp32 |= (SSFS_CDS + SSFS_FCERR);
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000650 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000651 temp32 |= SSFC_SCF_20MHZ;
652
653 if (datalength != 0) {
654 uint32_t datatemp;
655 temp32 |= SSFC_DS;
656 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
657 temp32 |= datatemp;
658 }
659
660 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000661 opmenu = REGREAD32(ICH9_REG_OPMENU);
662 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
663
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000664 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
665 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000666 break;
667 }
668 opmenu >>= 8;
669 }
670 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000671 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000672 return 1;
673 }
674 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000675
676 /* Handle Atomic */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000677 switch (op.atomic) {
678 case 2:
679 /* Select second preop. */
680 temp32 |= SSFC_SPOP;
681 /* And fall through. */
682 case 1:
683 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000684 temp32 |= SSFC_ACS;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000685 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000686 }
687
688 /* Start */
689 temp32 |= SSFC_SCGO;
690
691 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000692 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000693
694 /*wait for cycle complete */
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000695 timeout = 100 * 1000 * 60; // 60s is a looong timeout.
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000696 while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000697 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000698 }
699 if (!timeout) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000700 msg_perr("timeout\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000701 }
702
Sean Nelson316a29f2010-05-07 20:09:04 +0000703 /* FIXME make sure we do not needlessly cause transaction errors. */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000704 if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000705 msg_pdbg("Transaction error!\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000706 return 1;
707 }
708
709 if ((!write_cmd) && (datalength != 0)) {
710 for (a = 0; a < datalength; a++) {
711 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000712 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000713 }
714
715 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000716 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
717 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000718 }
719 }
720
721 return 0;
722}
723
Stefan Reinauer43119562008-11-02 19:51:50 +0000724static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000725 uint8_t datalength, uint8_t * data)
726{
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000727 switch (spi_controller) {
728 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000729 if (datalength > 16) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000730 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000731 "opcode 0x%02x, got datalength=%i, want <=16\n",
732 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000733 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000734 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000735 return ich7_run_opcode(op, offset, datalength, data, 16);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000736 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000737 if (datalength > 64) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000738 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000739 "opcode 0x%02x, got datalength=%i, want <=16\n",
740 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000741 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000742 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000743 return ich7_run_opcode(op, offset, datalength, data, 64);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000744 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000745 if (datalength > 64) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000746 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000747 "opcode 0x%02x, got datalength=%i, want <=16\n",
748 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000749 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000750 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000751 return ich9_run_opcode(op, offset, datalength, data);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000752 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000753 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000754 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000755
756 /* If we ever get here, something really weird happened */
757 return -1;
758}
759
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000760int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000761{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000762 int maxdata = 64;
763
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000764 if (spi_controller == SPI_CONTROLLER_VIA)
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000765 maxdata = 16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000766
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000767 return spi_read_chunked(flash, buf, start, len, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000768}
769
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000770int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000771{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000772 int maxdata = 64;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000773
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000774 if (spi_controller == SPI_CONTROLLER_VIA)
775 maxdata = 16;
776
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000777 return spi_write_chunked(flash, buf, start, len, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000778}
779
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000780int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000781 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000782{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000783 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000784 int opcode_index = -1;
785 const unsigned char cmd = *writearr;
786 OPCODE *opcode;
787 uint32_t addr = 0;
788 uint8_t *data;
789 int count;
790
Dominik Geyerb46acba2008-05-16 12:55:55 +0000791 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000792 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000793 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +0000794 if (!ichspi_lock)
795 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
796 if (opcode_index == -1) {
797 msg_pdbg("Invalid OPCODE 0x%02x\n", cmd);
798 return SPI_INVALID_OPCODE;
799 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000800 }
801
802 opcode = &(curopcodes->opcode[opcode_index]);
803
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000804 /* The following valid writecnt/readcnt combinations exist:
805 * writecnt = 4, readcnt >= 0
806 * writecnt = 1, readcnt >= 0
807 * writecnt >= 4, readcnt = 0
808 * writecnt >= 1, readcnt = 0
809 * writecnt >= 1 is guaranteed for all commands.
810 */
811 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
812 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000813 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000814 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
815 writecnt);
816 return SPI_INVALID_LENGTH;
817 }
818 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
819 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000820 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000821 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
822 writecnt);
823 return SPI_INVALID_LENGTH;
824 }
825 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
826 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000827 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000828 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
829 writecnt);
830 return SPI_INVALID_LENGTH;
831 }
832 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
833 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
834 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000835 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000836 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
837 readcnt);
838 return SPI_INVALID_LENGTH;
839 }
840
Dominik Geyerb46acba2008-05-16 12:55:55 +0000841 /* if opcode-type requires an address */
842 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
843 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000844 addr = (writearr[1] << 16) |
845 (writearr[2] << 8) | (writearr[3] << 0);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000846 switch (spi_controller) {
847 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000848 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000849 case SPI_CONTROLLER_ICH9:
850 if (addr < ichspi_bbar) {
851 msg_perr("%s: Address 0x%06x below allowed "
852 "range 0x%06x-0xffffff\n", __func__,
853 addr, ichspi_bbar);
854 return SPI_INVALID_ADDRESS;
855 }
856 break;
857 default:
858 break;
859 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000860 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000861
Dominik Geyerb46acba2008-05-16 12:55:55 +0000862 /* translate read/write array/count */
863 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000864 data = (uint8_t *) (writearr + 1);
865 count = writecnt - 1;
866 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
867 data = (uint8_t *) (writearr + 4);
868 count = writecnt - 4;
869 } else {
870 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000871 count = readcnt;
872 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000873
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000874 result = run_opcode(*opcode, addr, count, data);
875 if (result) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000876 msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000877 }
878
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000879 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000880}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000881
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000882int ich_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000883{
884 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000885 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000886 int oppos, preoppos;
887 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000888 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000889 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000890 preoppos = find_preop(curopcodes, cmds->writearr[0]);
891 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000892 if ((oppos == -1) && (preoppos != -1)) {
893 /* Current command is listed as preopcode in
894 * ICH struct OPCODES, but next command is not
895 * listed as opcode in that struct.
896 * Check for command sanity, then
897 * try to reprogram the ICH opcode list.
898 */
899 if (find_preop(curopcodes,
900 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000901 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000902 "preopcodes 0x%02x and 0x%02x, "
903 "ignoring the first.\n",
904 __func__, cmds->writearr[0],
905 (cmds + 1)->writearr[0]);
906 continue;
907 }
908 /* If the chipset is locked down, we'll fail
909 * during execution of the next command anyway.
910 * No need to bother with fixups.
911 */
912 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +0000913 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
914 if (oppos == -1)
915 continue;
916 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000917 continue;
918 }
919 }
920 if ((oppos != -1) && (preoppos != -1)) {
921 /* Current command is listed as preopcode in
922 * ICH struct OPCODES and next command is listed
923 * as opcode in that struct. Match them up.
924 */
925 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000926 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000927 }
928 /* If none of the above if-statements about oppos or
929 * preoppos matched, this is a normal opcode.
930 */
931 }
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000932 ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
933 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000934 /* Reset the type of all opcodes to non-atomic. */
935 for (i = 0; i < 8; i++)
936 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000937 }
938 return ret;
939}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000940
Michael Karchera4448d92010-07-22 18:04:15 +0000941#define ICH_BMWAG(x) ((x >> 24) & 0xff)
942#define ICH_BMRAG(x) ((x >> 16) & 0xff)
943#define ICH_BRWA(x) ((x >> 8) & 0xff)
944#define ICH_BRRA(x) ((x >> 0) & 0xff)
945
946#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff)
947#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff)
948
949static void do_ich9_spi_frap(uint32_t frap, int i)
950{
Mathias Krausea60faab2011-01-17 07:50:42 +0000951 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +0000952 "locked", "read-only", "write-only", "read-write"
953 };
Mathias Krausea60faab2011-01-17 07:50:42 +0000954 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +0000955 "Flash Descriptor", "BIOS", "Management Engine",
956 "Gigabit Ethernet", "Platform Data"
957 };
958 uint32_t base, limit;
959 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
960 (((ICH_BRRA(frap) >> i) & 1) << 0);
961 int offset = 0x54 + i * 4;
962 uint32_t freg = mmio_readl(ich_spibar + offset);
963
964 msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n",
965 offset, freg, i, region_names[i]);
966
967 base = ICH_FREG_BASE(freg);
968 limit = ICH_FREG_LIMIT(freg);
969 if (base == 0x1fff && limit == 0) {
970 /* this FREG is disabled */
971 msg_pdbg("%s region is unused.\n", region_names[i]);
972 return;
973 }
974
975 msg_pdbg("0x%08x-0x%08x is %s\n",
976 (base << 12), (limit << 12) | 0x0fff,
977 access_names[rwperms]);
978}
979
980int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
981 int ich_generation)
982{
983 int i;
984 uint8_t old, new;
985 uint16_t spibar_offset, tmp2;
986 uint32_t tmp;
987
988 buses_supported |= CHIP_BUSTYPE_SPI;
989 switch (ich_generation) {
990 case 7:
991 spi_controller = SPI_CONTROLLER_ICH7;
992 spibar_offset = 0x3020;
993 break;
994 case 8:
995 spi_controller = SPI_CONTROLLER_ICH9;
996 spibar_offset = 0x3020;
997 break;
998 case 9:
999 case 10:
1000 default: /* Future version might behave the same */
1001 spi_controller = SPI_CONTROLLER_ICH9;
1002 spibar_offset = 0x3800;
1003 break;
1004 }
1005
1006 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
1007 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset);
1008
1009 /* Assign Virtual Address */
1010 ich_spibar = rcrb + spibar_offset;
1011
1012 switch (spi_controller) {
1013 case SPI_CONTROLLER_ICH7:
1014 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1015 mmio_readw(ich_spibar + 0));
1016 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1017 mmio_readw(ich_spibar + 2));
1018 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1019 mmio_readl(ich_spibar + 4));
1020 for (i = 0; i < 8; i++) {
1021 int offs;
1022 offs = 8 + (i * 8);
1023 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1024 mmio_readl(ich_spibar + offs), i);
1025 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1026 mmio_readl(ich_spibar + offs + 4), i);
1027 }
1028 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1029 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1030 ichspi_bbar);
1031 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1032 mmio_readw(ich_spibar + 0x54));
1033 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1034 mmio_readw(ich_spibar + 0x56));
1035 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1036 mmio_readl(ich_spibar + 0x58));
1037 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1038 mmio_readl(ich_spibar + 0x5c));
1039 for (i = 0; i < 4; i++) {
1040 int offs;
1041 offs = 0x60 + (i * 4);
1042 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1043 mmio_readl(ich_spibar + offs), i);
1044 }
1045 msg_pdbg("\n");
1046 if (mmio_readw(ich_spibar) & (1 << 15)) {
1047 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1048 ichspi_lock = 1;
1049 }
1050 ich_init_opcodes();
1051 break;
1052 case SPI_CONTROLLER_ICH9:
1053 tmp2 = mmio_readw(ich_spibar + 4);
1054 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
1055 msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1));
1056 msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1);
1057 msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1);
1058 msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1);
1059 msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3);
1060 msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1);
1061 msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1);
1062 msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1);
1063
1064 tmp = mmio_readl(ich_spibar + 0x50);
1065 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1066 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1067 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1068 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1069 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1070
1071 /* print out the FREGx registers along with FRAP access bits */
1072 for(i = 0; i < 5; i++)
1073 do_ich9_spi_frap(tmp, i);
1074
1075 msg_pdbg("0x74: 0x%08x (PR0)\n",
1076 mmio_readl(ich_spibar + 0x74));
1077 msg_pdbg("0x78: 0x%08x (PR1)\n",
1078 mmio_readl(ich_spibar + 0x78));
1079 msg_pdbg("0x7C: 0x%08x (PR2)\n",
1080 mmio_readl(ich_spibar + 0x7C));
1081 msg_pdbg("0x80: 0x%08x (PR3)\n",
1082 mmio_readl(ich_spibar + 0x80));
1083 msg_pdbg("0x84: 0x%08x (PR4)\n",
1084 mmio_readl(ich_spibar + 0x84));
1085 msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n",
1086 mmio_readl(ich_spibar + 0x90));
1087 msg_pdbg("0x94: 0x%04x (PREOP)\n",
1088 mmio_readw(ich_spibar + 0x94));
1089 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
1090 mmio_readw(ich_spibar + 0x96));
1091 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
1092 mmio_readl(ich_spibar + 0x98));
1093 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
1094 mmio_readl(ich_spibar + 0x9C));
1095 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
1096 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1097 ichspi_bbar);
1098 msg_pdbg("0xB0: 0x%08x (FDOC)\n",
1099 mmio_readl(ich_spibar + 0xB0));
1100 if (tmp2 & (1 << 15)) {
1101 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1102 ichspi_lock = 1;
1103 }
1104 ich_init_opcodes();
1105 break;
1106 default:
1107 /* Nothing */
1108 break;
1109 }
1110
1111 old = pci_read_byte(dev, 0xdc);
1112 msg_pdbg("SPI Read Configuration: ");
1113 new = (old >> 2) & 0x3;
1114 switch (new) {
1115 case 0:
1116 case 1:
1117 case 2:
1118 msg_pdbg("prefetching %sabled, caching %sabled, ",
1119 (new & 0x2) ? "en" : "dis",
1120 (new & 0x1) ? "dis" : "en");
1121 break;
1122 default:
1123 msg_pdbg("invalid prefetching/caching settings, ");
1124 break;
1125 }
1126 return 0;
1127}
1128
1129int via_init_spi(struct pci_dev *dev)
1130{
1131 uint32_t mmio_base;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001132 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00001133
1134 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
1135 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
1136 ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
1137
Michael Karchera4448d92010-07-22 18:04:15 +00001138 /* Not sure if it speaks all these bus protocols. */
1139 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
1140 spi_controller = SPI_CONTROLLER_VIA;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001141
1142 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
1143 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
1144 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
1145 for (i = 0; i < 2; i++) {
1146 int offs;
1147 offs = 8 + (i * 8);
1148 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1149 mmio_readl(ich_spibar + offs), i);
1150 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1151 mmio_readl(ich_spibar + offs + 4), i);
1152 }
1153 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1154 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
1155 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
1156 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
1157 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
1158 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
1159 for (i = 0; i < 3; i++) {
1160 int offs;
1161 offs = 0x60 + (i * 4);
1162 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1163 mmio_readl(ich_spibar + offs), i);
1164 }
1165 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1166 mmio_readw(ich_spibar + 0x6c));
1167 if (mmio_readw(ich_spibar) & (1 << 15)) {
1168 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1169 ichspi_lock = 1;
1170 }
1171
Michael Karchera4448d92010-07-22 18:04:15 +00001172 ich_init_opcodes();
1173
1174 return 0;
1175}
1176
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001177#endif