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Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000014 */
15
16#ifndef __SPI_H__
17#define __SPI_H__ 1
18
19/*
20 * Contains the generic SPI headers
21 */
22
Nico Huber0ecbacb2017-10-14 16:50:43 +020023#define JEDEC_MAX_ADDR_LEN 0x04
24
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000025/* Read Electronic ID */
26#define JEDEC_RDID 0x9f
27#define JEDEC_RDID_OUTSIZE 0x01
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000028/* INSIZE may be 0x04 for some chips*/
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000029#define JEDEC_RDID_INSIZE 0x03
30
Stefan Tauner57794ac2012-12-29 15:04:20 +000031/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */
32#define AT25F_RDID 0x15 /* 0x15 or 0x1d */
33#define AT25F_RDID_OUTSIZE 0x01
34#define AT25F_RDID_INSIZE 0x02
Carl-Daniel Hailfinger0faf03e2008-11-28 23:47:55 +000035
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +000036/* Read Electronic Manufacturer Signature */
37#define JEDEC_REMS 0x90
38#define JEDEC_REMS_OUTSIZE 0x04
39#define JEDEC_REMS_INSIZE 0x02
40
Stefan Taunerac1b4c82012-02-17 14:51:04 +000041/* Read Serial Flash Discoverable Parameters (SFDP) */
42#define JEDEC_SFDP 0x5a
43#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */
44/* JEDEC_SFDP_INSIZE : any length */
45
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000046/* Read Electronic Signature */
47#define JEDEC_RES 0xab
48#define JEDEC_RES_OUTSIZE 0x04
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000049/* INSIZE may be 0x02 for some chips*/
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000050#define JEDEC_RES_INSIZE 0x01
51
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000052/* Write Enable */
53#define JEDEC_WREN 0x06
54#define JEDEC_WREN_OUTSIZE 0x01
55#define JEDEC_WREN_INSIZE 0x00
56
57/* Write Disable */
58#define JEDEC_WRDI 0x04
59#define JEDEC_WRDI_OUTSIZE 0x01
60#define JEDEC_WRDI_INSIZE 0x00
61
62/* Chip Erase 0x60 is supported by Macronix/SST chips. */
63#define JEDEC_CE_60 0x60
64#define JEDEC_CE_60_OUTSIZE 0x01
65#define JEDEC_CE_60_INSIZE 0x00
66
Stefan Tauner3c0fcd02012-09-21 12:46:56 +000067/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
68#define JEDEC_CE_62 0x62
69#define JEDEC_CE_62_OUTSIZE 0x01
70#define JEDEC_CE_62_INSIZE 0x00
71
Peter Stugef83221b2008-07-07 06:38:51 +000072/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000073#define JEDEC_CE_C7 0xc7
74#define JEDEC_CE_C7_OUTSIZE 0x01
75#define JEDEC_CE_C7_INSIZE 0x00
76
Stefan Tauner94b39b42012-10-27 00:06:02 +000077/* Block Erase 0x50 is supported by Atmel AT26DF chips. */
78#define JEDEC_BE_50 0x50
79#define JEDEC_BE_50_OUTSIZE 0x04
80#define JEDEC_BE_50_INSIZE 0x00
81
Carl-Daniel Hailfingerd54ef6e2008-11-15 13:55:43 +000082/* Block Erase 0x52 is supported by SST and old Atmel chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000083#define JEDEC_BE_52 0x52
84#define JEDEC_BE_52_OUTSIZE 0x04
85#define JEDEC_BE_52_INSIZE 0x00
86
Stefan Tauner94b39b42012-10-27 00:06:02 +000087/* Block Erase 0x81 is supported by Atmel AT26DF chips. */
88#define JEDEC_BE_81 0x81
89#define JEDEC_BE_81_OUTSIZE 0x04
90#define JEDEC_BE_81_INSIZE 0x00
91
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +000092/* Block Erase 0xc4 is supported by Micron chips. */
93#define JEDEC_BE_C4 0xc4
94#define JEDEC_BE_C4_OUTSIZE 0x04
95#define JEDEC_BE_C4_INSIZE 0x00
96
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000097/* Block Erase 0xd8 is supported by EON/Macronix chips. */
98#define JEDEC_BE_D8 0xd8
99#define JEDEC_BE_D8_OUTSIZE 0x04
100#define JEDEC_BE_D8_INSIZE 0x00
101
Sean Nelson5643c072010-01-19 03:23:07 +0000102/* Block Erase 0xd7 is supported by PMC chips. */
103#define JEDEC_BE_D7 0xd7
104#define JEDEC_BE_D7_OUTSIZE 0x04
105#define JEDEC_BE_D7_INSIZE 0x00
106
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000107/* Sector Erase 0x20 is supported by Macronix/SST chips. */
108#define JEDEC_SE 0x20
109#define JEDEC_SE_OUTSIZE 0x04
110#define JEDEC_SE_INSIZE 0x00
111
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000112/* Page Erase 0xDB */
113#define JEDEC_PE 0xDB
114#define JEDEC_PE_OUTSIZE 0x04
115#define JEDEC_PE_INSIZE 0x00
116
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000117/* Read Status Register */
118#define JEDEC_RDSR 0x05
119#define JEDEC_RDSR_OUTSIZE 0x01
120#define JEDEC_RDSR_INSIZE 0x01
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000121
122/* Status Register Bits */
123#define SPI_SR_WIP (0x01 << 0)
124#define SPI_SR_WEL (0x01 << 1)
125#define SPI_SR_AAI (0x01 << 6)
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000126
Jason Wanga3f04be2008-11-28 21:36:51 +0000127/* Write Status Enable */
128#define JEDEC_EWSR 0x50
129#define JEDEC_EWSR_OUTSIZE 0x01
130#define JEDEC_EWSR_INSIZE 0x00
131
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000132/* Write Status Register */
133#define JEDEC_WRSR 0x01
134#define JEDEC_WRSR_OUTSIZE 0x02
135#define JEDEC_WRSR_INSIZE 0x00
136
Nico Huber7e3c81a2017-10-14 18:56:50 +0200137/* Enter 4-byte Address Mode */
138#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
139
140/* Exit 4-byte Address Mode */
141#define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9
142
143/* Write Extended Address Register */
144#define JEDEC_WRITE_EXT_ADDR_REG 0xC5
145
146/* Read Extended Address Register */
147#define JEDEC_READ_EXT_ADDR_REG 0xC8
148
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000149/* Read the memory */
150#define JEDEC_READ 0x03
151#define JEDEC_READ_OUTSIZE 0x04
152/* JEDEC_READ_INSIZE : any length */
153
154/* Write memory byte */
Carl-Daniel Hailfingerd99b8d32010-07-29 16:32:24 +0000155#define JEDEC_BYTE_PROGRAM 0x02
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000156#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
157#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
158
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000159/* Write AAI word (SST25VF080B) */
Carl-Daniel Hailfingerd99b8d32010-07-29 16:32:24 +0000160#define JEDEC_AAI_WORD_PROGRAM 0xad
161#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06
162#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03
163#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000164
Nico Huber7e3c81a2017-10-14 18:56:50 +0200165/* Read the memory with 4-byte address
166 From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
167#define JEDEC_READ_4BA 0x13
168
169/* Write memory byte with 4-byte address
170 From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
171#define JEDEC_BYTE_PROGRAM_4BA 0x12
172
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000173/* Error codes */
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000174#define SPI_GENERIC_ERROR -1
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000175#define SPI_INVALID_OPCODE -2
176#define SPI_INVALID_ADDRESS -3
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000177#define SPI_INVALID_LENGTH -4
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000178#define SPI_FLASHROM_BUG -5
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000179#define SPI_PROGRAMMER_ERROR -6
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000180
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000181#endif /* !__SPI_H__ */