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Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __SPI_H__
21#define __SPI_H__ 1
22
23/*
24 * Contains the generic SPI headers
25 */
26
Nico Huber0ecbacb2017-10-14 16:50:43 +020027#define JEDEC_MAX_ADDR_LEN 0x04
28
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000029/* Read Electronic ID */
30#define JEDEC_RDID 0x9f
31#define JEDEC_RDID_OUTSIZE 0x01
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000032/* INSIZE may be 0x04 for some chips*/
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000033#define JEDEC_RDID_INSIZE 0x03
34
Stefan Tauner57794ac2012-12-29 15:04:20 +000035/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */
36#define AT25F_RDID 0x15 /* 0x15 or 0x1d */
37#define AT25F_RDID_OUTSIZE 0x01
38#define AT25F_RDID_INSIZE 0x02
Carl-Daniel Hailfinger0faf03e2008-11-28 23:47:55 +000039
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +000040/* Read Electronic Manufacturer Signature */
41#define JEDEC_REMS 0x90
42#define JEDEC_REMS_OUTSIZE 0x04
43#define JEDEC_REMS_INSIZE 0x02
44
Stefan Taunerac1b4c82012-02-17 14:51:04 +000045/* Read Serial Flash Discoverable Parameters (SFDP) */
46#define JEDEC_SFDP 0x5a
47#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */
48/* JEDEC_SFDP_INSIZE : any length */
49
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000050/* Read Electronic Signature */
51#define JEDEC_RES 0xab
52#define JEDEC_RES_OUTSIZE 0x04
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000053/* INSIZE may be 0x02 for some chips*/
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000054#define JEDEC_RES_INSIZE 0x01
55
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000056/* Write Enable */
57#define JEDEC_WREN 0x06
58#define JEDEC_WREN_OUTSIZE 0x01
59#define JEDEC_WREN_INSIZE 0x00
60
61/* Write Disable */
62#define JEDEC_WRDI 0x04
63#define JEDEC_WRDI_OUTSIZE 0x01
64#define JEDEC_WRDI_INSIZE 0x00
65
66/* Chip Erase 0x60 is supported by Macronix/SST chips. */
67#define JEDEC_CE_60 0x60
68#define JEDEC_CE_60_OUTSIZE 0x01
69#define JEDEC_CE_60_INSIZE 0x00
70
Stefan Tauner3c0fcd02012-09-21 12:46:56 +000071/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
72#define JEDEC_CE_62 0x62
73#define JEDEC_CE_62_OUTSIZE 0x01
74#define JEDEC_CE_62_INSIZE 0x00
75
Peter Stugef83221b2008-07-07 06:38:51 +000076/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000077#define JEDEC_CE_C7 0xc7
78#define JEDEC_CE_C7_OUTSIZE 0x01
79#define JEDEC_CE_C7_INSIZE 0x00
80
Stefan Tauner94b39b42012-10-27 00:06:02 +000081/* Block Erase 0x50 is supported by Atmel AT26DF chips. */
82#define JEDEC_BE_50 0x50
83#define JEDEC_BE_50_OUTSIZE 0x04
84#define JEDEC_BE_50_INSIZE 0x00
85
Carl-Daniel Hailfingerd54ef6e2008-11-15 13:55:43 +000086/* Block Erase 0x52 is supported by SST and old Atmel chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000087#define JEDEC_BE_52 0x52
88#define JEDEC_BE_52_OUTSIZE 0x04
89#define JEDEC_BE_52_INSIZE 0x00
90
Stefan Tauner94b39b42012-10-27 00:06:02 +000091/* Block Erase 0x81 is supported by Atmel AT26DF chips. */
92#define JEDEC_BE_81 0x81
93#define JEDEC_BE_81_OUTSIZE 0x04
94#define JEDEC_BE_81_INSIZE 0x00
95
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +000096/* Block Erase 0xc4 is supported by Micron chips. */
97#define JEDEC_BE_C4 0xc4
98#define JEDEC_BE_C4_OUTSIZE 0x04
99#define JEDEC_BE_C4_INSIZE 0x00
100
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000101/* Block Erase 0xd8 is supported by EON/Macronix chips. */
102#define JEDEC_BE_D8 0xd8
103#define JEDEC_BE_D8_OUTSIZE 0x04
104#define JEDEC_BE_D8_INSIZE 0x00
105
Sean Nelson5643c072010-01-19 03:23:07 +0000106/* Block Erase 0xd7 is supported by PMC chips. */
107#define JEDEC_BE_D7 0xd7
108#define JEDEC_BE_D7_OUTSIZE 0x04
109#define JEDEC_BE_D7_INSIZE 0x00
110
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000111/* Sector Erase 0x20 is supported by Macronix/SST chips. */
112#define JEDEC_SE 0x20
113#define JEDEC_SE_OUTSIZE 0x04
114#define JEDEC_SE_INSIZE 0x00
115
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000116/* Page Erase 0xDB */
117#define JEDEC_PE 0xDB
118#define JEDEC_PE_OUTSIZE 0x04
119#define JEDEC_PE_INSIZE 0x00
120
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000121/* Read Status Register */
122#define JEDEC_RDSR 0x05
123#define JEDEC_RDSR_OUTSIZE 0x01
124#define JEDEC_RDSR_INSIZE 0x01
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000125
126/* Status Register Bits */
127#define SPI_SR_WIP (0x01 << 0)
128#define SPI_SR_WEL (0x01 << 1)
129#define SPI_SR_AAI (0x01 << 6)
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000130
Jason Wanga3f04be2008-11-28 21:36:51 +0000131/* Write Status Enable */
132#define JEDEC_EWSR 0x50
133#define JEDEC_EWSR_OUTSIZE 0x01
134#define JEDEC_EWSR_INSIZE 0x00
135
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000136/* Write Status Register */
137#define JEDEC_WRSR 0x01
138#define JEDEC_WRSR_OUTSIZE 0x02
139#define JEDEC_WRSR_INSIZE 0x00
140
141/* Read the memory */
142#define JEDEC_READ 0x03
143#define JEDEC_READ_OUTSIZE 0x04
144/* JEDEC_READ_INSIZE : any length */
145
146/* Write memory byte */
Carl-Daniel Hailfingerd99b8d32010-07-29 16:32:24 +0000147#define JEDEC_BYTE_PROGRAM 0x02
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000148#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
149#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
150
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000151/* Write AAI word (SST25VF080B) */
Carl-Daniel Hailfingerd99b8d32010-07-29 16:32:24 +0000152#define JEDEC_AAI_WORD_PROGRAM 0xad
153#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06
154#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03
155#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000156
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000157/* Error codes */
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000158#define SPI_GENERIC_ERROR -1
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000159#define SPI_INVALID_OPCODE -2
160#define SPI_INVALID_ADDRESS -3
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000161#define SPI_INVALID_LENGTH -4
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000162#define SPI_FLASHROM_BUG -5
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000163#define SPI_PROGRAMMER_ERROR -6
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000164
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000165#endif /* !__SPI_H__ */