| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdlib.h> |
| 18 | #include <string.h> |
| Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 19 | #include "programmer.h" |
| Thomas Heijligen | a065520 | 2021-12-14 16:36:05 +0100 | [diff] [blame] | 20 | #include "hwaccess_x86_io.h" |
| Thomas Heijligen | d96c97c | 2021-11-02 21:03:00 +0100 | [diff] [blame] | 21 | #include "platform/pci.h" |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 22 | |
| 23 | #define BIOS_ROM_ADDR 0x90 |
| 24 | #define BIOS_ROM_DATA 0x94 |
| 25 | |
| 26 | #define REG_FLASH_ACCESS 0x58 |
| 27 | |
| 28 | #define PCI_VENDOR_ID_HPT 0x1103 |
| 29 | |
| Stefan Tauner | 0ccec8f | 2014-06-01 23:49:03 +0000 | [diff] [blame] | 30 | static uint32_t io_base_addr = 0; |
| 31 | |
| Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 32 | static const struct dev_entry ata_hpt[] = { |
| Michael Karcher | 8448639 | 2010-02-24 00:04:40 +0000 | [diff] [blame] | 33 | {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, |
| 34 | {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"}, |
| 35 | {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"}, |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 36 | |
| Carl-Daniel Hailfinger | 1c6d2ff | 2012-08-27 00:44:42 +0000 | [diff] [blame] | 37 | {0}, |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 38 | }; |
| 39 | |
| Nico Huber | dd6e07a | 2026-02-21 17:55:26 +0100 | [diff] [blame] | 40 | static void atahpt_chip_writeb(const struct par_master *, uint8_t val, chipaddr); |
| 41 | static uint8_t atahpt_chip_readb(const struct par_master *, chipaddr); |
| Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 42 | static const struct par_master par_master_atahpt = { |
| Thomas Heijligen | 43040f2 | 2022-06-23 14:38:35 +0200 | [diff] [blame] | 43 | .chip_readb = atahpt_chip_readb, |
| 44 | .chip_readw = fallback_chip_readw, |
| 45 | .chip_readl = fallback_chip_readl, |
| 46 | .chip_readn = fallback_chip_readn, |
| 47 | .chip_writeb = atahpt_chip_writeb, |
| 48 | .chip_writew = fallback_chip_writew, |
| 49 | .chip_writel = fallback_chip_writel, |
| 50 | .chip_writen = fallback_chip_writen, |
| Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 51 | }; |
| 52 | |
| Nico Huber | e3a2688 | 2023-01-11 21:45:51 +0100 | [diff] [blame] | 53 | static int atahpt_init(struct flashprog_programmer *const prog) |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 54 | { |
| Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 55 | struct pci_dev *dev = NULL; |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 56 | uint32_t reg32; |
| 57 | |
| Carl-Daniel Hailfinger | d6bb828 | 2012-07-21 17:27:08 +0000 | [diff] [blame] | 58 | if (rget_io_perms()) |
| 59 | return 1; |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 60 | |
| Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 61 | dev = pcidev_init(ata_hpt, PCI_BASE_ADDRESS_4); |
| 62 | if (!dev) |
| 63 | return 1; |
| 64 | |
| 65 | io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4); |
| Niklas Söderlund | 89edf36 | 2013-08-23 23:29:23 +0000 | [diff] [blame] | 66 | if (!io_base_addr) |
| 67 | return 1; |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 68 | |
| 69 | /* Enable flash access. */ |
| Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 70 | reg32 = pci_read_long(dev, REG_FLASH_ACCESS); |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 71 | reg32 |= (1 << 24); |
| Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 72 | rpci_write_long(dev, REG_FLASH_ACCESS, reg32); |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 73 | |
| Nico Huber | 47aa85c | 2026-02-21 14:57:20 +0100 | [diff] [blame] | 74 | return register_par_master(&par_master_atahpt, BUS_PARALLEL, 0, 0, NULL); |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 75 | } |
| 76 | |
| Nico Huber | dd6e07a | 2026-02-21 17:55:26 +0100 | [diff] [blame] | 77 | static void atahpt_chip_writeb(const struct par_master *par, uint8_t val, chipaddr addr) |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 78 | { |
| 79 | OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); |
| 80 | OUTB(val, io_base_addr + BIOS_ROM_DATA); |
| 81 | } |
| 82 | |
| Nico Huber | dd6e07a | 2026-02-21 17:55:26 +0100 | [diff] [blame] | 83 | static uint8_t atahpt_chip_readb(const struct par_master *par, const chipaddr addr) |
| Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 84 | { |
| 85 | OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); |
| 86 | return INB(io_base_addr + BIOS_ROM_DATA); |
| 87 | } |
| Andrew Morgan | a074383 | 2011-07-25 22:07:05 +0000 | [diff] [blame] | 88 | |
| Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 89 | const struct programmer_entry programmer_atahpt = { |
| 90 | .name = "atahpt", |
| 91 | .type = PCI, |
| 92 | .devs.dev = ata_hpt, |
| 93 | .init = atahpt_init, |
| Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 94 | }; |