programmer_table: move each entry to the associated programmer source
Change-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71373
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/atahpt.c b/atahpt.c
index dae0222..a064deb 100644
--- a/atahpt.c
+++ b/atahpt.c
@@ -31,7 +31,7 @@
static uint32_t io_base_addr = 0;
-const struct dev_entry ata_hpt[] = {
+static const struct dev_entry ata_hpt[] = {
{0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},
{0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"},
{0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"},
@@ -54,7 +54,7 @@
.chip_writen = fallback_chip_writen,
};
-int atahpt_init(void)
+static int atahpt_init(void)
{
struct pci_dev *dev = NULL;
uint32_t reg32;
@@ -94,6 +94,16 @@
return INB(io_base_addr + BIOS_ROM_DATA);
}
+const struct programmer_entry programmer_atahpt = {
+ .name = "atahpt",
+ .type = PCI,
+ .devs.dev = ata_hpt,
+ .init = atahpt_init,
+ .map_flash_region = fallback_map,
+ .unmap_flash_region = fallback_unmap,
+ .delay = internal_delay,
+};
+
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif