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Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef __PROGRAMMER_H__
25#define __PROGRAMMER_H__ 1
26
27enum programmer {
28#if CONFIG_INTERNAL == 1
29 PROGRAMMER_INTERNAL,
30#endif
31#if CONFIG_DUMMY == 1
32 PROGRAMMER_DUMMY,
33#endif
34#if CONFIG_NIC3COM == 1
35 PROGRAMMER_NIC3COM,
36#endif
37#if CONFIG_NICREALTEK == 1
38 PROGRAMMER_NICREALTEK,
Idwer Vollering004f4b72010-09-03 18:21:21 +000039#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000040#if CONFIG_NICNATSEMI == 1
41 PROGRAMMER_NICNATSEMI,
Idwer Vollering004f4b72010-09-03 18:21:21 +000042#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000043#if CONFIG_GFXNVIDIA == 1
44 PROGRAMMER_GFXNVIDIA,
45#endif
46#if CONFIG_DRKAISER == 1
47 PROGRAMMER_DRKAISER,
48#endif
49#if CONFIG_SATASII == 1
50 PROGRAMMER_SATASII,
51#endif
52#if CONFIG_ATAHPT == 1
53 PROGRAMMER_ATAHPT,
54#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000055#if CONFIG_FT2232_SPI == 1
56 PROGRAMMER_FT2232_SPI,
57#endif
58#if CONFIG_SERPROG == 1
59 PROGRAMMER_SERPROG,
60#endif
61#if CONFIG_BUSPIRATE_SPI == 1
62 PROGRAMMER_BUSPIRATE_SPI,
63#endif
64#if CONFIG_DEDIPROG == 1
65 PROGRAMMER_DEDIPROG,
66#endif
67#if CONFIG_RAYER_SPI == 1
68 PROGRAMMER_RAYER_SPI,
69#endif
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000070#if CONFIG_NICINTEL == 1
71 PROGRAMMER_NICINTEL,
72#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +000073#if CONFIG_NICINTEL_SPI == 1
74 PROGRAMMER_NICINTEL_SPI,
75#endif
Mark Marshall90021f22010-12-03 14:48:11 +000076#if CONFIG_OGP_SPI == 1
77 PROGRAMMER_OGP_SPI,
78#endif
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000079#if CONFIG_SATAMV == 1
80 PROGRAMMER_SATAMV,
81#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000082 PROGRAMMER_INVALID /* This must always be the last entry. */
83};
84
85extern enum programmer programmer;
86
87struct programmer_entry {
88 const char *vendor;
89 const char *name;
90
91 int (*init) (void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000092
93 void * (*map_flash_region) (const char *descr, unsigned long phys_addr,
94 size_t len);
95 void (*unmap_flash_region) (void *virt_addr, size_t len);
96
97 void (*chip_writeb) (uint8_t val, chipaddr addr);
98 void (*chip_writew) (uint16_t val, chipaddr addr);
99 void (*chip_writel) (uint32_t val, chipaddr addr);
100 void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
101 uint8_t (*chip_readb) (const chipaddr addr);
102 uint16_t (*chip_readw) (const chipaddr addr);
103 uint32_t (*chip_readl) (const chipaddr addr);
104 void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
105 void (*delay) (int usecs);
106};
107
108extern const struct programmer_entry programmer_table[];
109
110int programmer_init(char *param);
111int programmer_shutdown(void);
112
113enum bitbang_spi_master_type {
114 BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */
115#if CONFIG_RAYER_SPI == 1
116 BITBANG_SPI_MASTER_RAYER,
117#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +0000118#if CONFIG_NICINTEL_SPI == 1
119 BITBANG_SPI_MASTER_NICINTEL,
120#endif
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000121#if CONFIG_INTERNAL == 1
122#if defined(__i386__) || defined(__x86_64__)
123 BITBANG_SPI_MASTER_MCP,
124#endif
125#endif
Mark Marshall90021f22010-12-03 14:48:11 +0000126#if CONFIG_OGP_SPI == 1
127 BITBANG_SPI_MASTER_OGP,
128#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000129};
130
131struct bitbang_spi_master {
132 enum bitbang_spi_master_type type;
133
134 /* Note that CS# is active low, so val=0 means the chip is active. */
135 void (*set_cs) (int val);
136 void (*set_sck) (int val);
137 void (*set_mosi) (int val);
138 int (*get_miso) (void);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000139 void (*request_bus) (void);
140 void (*release_bus) (void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000141};
142
143#if CONFIG_INTERNAL == 1
144struct penable {
145 uint16_t vendor_id;
146 uint16_t device_id;
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000147 int status; /* OK=0 and NT=1 are defines only. Beware! */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000148 const char *vendor_name;
149 const char *device_name;
150 int (*doit) (struct pci_dev *dev, const char *name);
151};
152
153extern const struct penable chipset_enables[];
154
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000155enum board_match_phase {
156 P1,
157 P2,
158 P3
159};
160
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +0000161struct board_match {
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000162 /* Any device, but make it sensible, like the ISA bridge. */
163 uint16_t first_vendor;
164 uint16_t first_device;
165 uint16_t first_card_vendor;
166 uint16_t first_card_device;
167
168 /* Any device, but make it sensible, like
169 * the host bridge. May be NULL.
170 */
171 uint16_t second_vendor;
172 uint16_t second_device;
173 uint16_t second_card_vendor;
174 uint16_t second_card_device;
175
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000176 /* Pattern to match DMI entries. May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000177 const char *dmi_pattern;
178
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000179 /* The vendor / part name from the coreboot table. May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000180 const char *lb_vendor;
181 const char *lb_part;
182
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000183 enum board_match_phase phase;
184
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000185 const char *vendor_name;
186 const char *board_name;
187
188 int max_rom_decode_parallel;
189 int status;
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000190 int (*enable) (void); /* May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000191};
192
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +0000193extern const struct board_match board_matches[];
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000194
195struct board_info {
196 const char *vendor;
197 const char *name;
198 const int working;
199#ifdef CONFIG_PRINT_WIKI
200 const char *url;
201 const char *note;
202#endif
203};
204
205extern const struct board_info boards_known[];
206extern const struct board_info laptops_known[];
207#endif
208
209/* udelay.c */
210void myusec_delay(int usecs);
211void myusec_calibrate_delay(void);
212void internal_delay(int usecs);
213
214#if NEED_PCI == 1
215/* pcidev.c */
216extern uint32_t io_base_addr;
217extern struct pci_access *pacc;
218extern struct pci_dev *pcidev_dev;
219struct pcidev_status {
220 uint16_t vendor_id;
221 uint16_t device_id;
222 int status;
223 const char *vendor_name;
224 const char *device_name;
225};
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +0000226uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs);
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +0000227uintptr_t pcidev_init(int bar, const struct pcidev_status *devs);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000228/* rpci_write_* are reversible writes. The original PCI config space register
229 * contents will be restored on shutdown.
230 */
Idwer Vollering1a6162e2010-12-26 23:55:19 +0000231int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
232int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
233int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000234#endif
235
236/* print.c */
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000237#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000238void print_supported_pcidevs(const struct pcidev_status *devs);
239#endif
240
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000241#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000242/* board_enable.c */
243void w836xx_ext_enter(uint16_t port);
244void w836xx_ext_leave(uint16_t port);
245int it8705f_write_enable(uint8_t port);
246uint8_t sio_read(uint16_t port, uint8_t reg);
247void sio_write(uint16_t port, uint8_t reg, uint8_t data);
248void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000249void board_handle_before_superio(void);
250void board_handle_before_laptop(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000251int board_flash_enable(const char *vendor, const char *part);
252
253/* chipset_enable.c */
254int chipset_flash_enable(void);
255
256/* processor_enable.c */
257int processor_flash_enable(void);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000258#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000259
260/* physmap.c */
261void *physmap(const char *descr, unsigned long phys_addr, size_t len);
262void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len);
263void physunmap(void *virt_addr, size_t len);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000264#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000265int setup_cpu_msr(int cpu);
266void cleanup_cpu_msr(void);
267
268/* cbtable.c */
269void lb_vendor_dev_from_string(char *boardstring);
270int coreboot_init(void);
271extern char *lb_part, *lb_vendor;
272extern int partvendor_from_cbtable;
273
274/* dmi.c */
275extern int has_dmi_support;
276void dmi_init(void);
277int dmi_match(const char *pattern);
278
279/* internal.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000280struct superio {
281 uint16_t vendor;
282 uint16_t port;
283 uint16_t model;
284};
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000285extern struct superio superios[];
286extern int superio_count;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000287#define SUPERIO_VENDOR_NONE 0x0
288#define SUPERIO_VENDOR_ITE 0x1
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000289#endif
290#if NEED_PCI == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000291struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
Uwe Hermann24c35e42011-07-13 11:22:03 +0000292struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000293struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
294struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
295 uint16_t card_vendor, uint16_t card_device);
296#endif
297void get_io_perms(void);
298void release_io_perms(void);
299#if CONFIG_INTERNAL == 1
300extern int is_laptop;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000301extern int laptop_ok;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000302extern int force_boardenable;
303extern int force_boardmismatch;
304void probe_superio(void);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000305int register_superio(struct superio s);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000306int internal_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000307void internal_chip_writeb(uint8_t val, chipaddr addr);
308void internal_chip_writew(uint16_t val, chipaddr addr);
309void internal_chip_writel(uint32_t val, chipaddr addr);
310uint8_t internal_chip_readb(const chipaddr addr);
311uint16_t internal_chip_readw(const chipaddr addr);
312uint32_t internal_chip_readl(const chipaddr addr);
313void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
314#endif
315
316/* hwaccess.c */
317void mmio_writeb(uint8_t val, void *addr);
318void mmio_writew(uint16_t val, void *addr);
319void mmio_writel(uint32_t val, void *addr);
320uint8_t mmio_readb(void *addr);
321uint16_t mmio_readw(void *addr);
322uint32_t mmio_readl(void *addr);
323void mmio_le_writeb(uint8_t val, void *addr);
324void mmio_le_writew(uint16_t val, void *addr);
325void mmio_le_writel(uint32_t val, void *addr);
326uint8_t mmio_le_readb(void *addr);
327uint16_t mmio_le_readw(void *addr);
328uint32_t mmio_le_readl(void *addr);
329#define pci_mmio_writeb mmio_le_writeb
330#define pci_mmio_writew mmio_le_writew
331#define pci_mmio_writel mmio_le_writel
332#define pci_mmio_readb mmio_le_readb
333#define pci_mmio_readw mmio_le_readw
334#define pci_mmio_readl mmio_le_readl
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000335void rmmio_writeb(uint8_t val, void *addr);
336void rmmio_writew(uint16_t val, void *addr);
337void rmmio_writel(uint32_t val, void *addr);
338void rmmio_le_writeb(uint8_t val, void *addr);
339void rmmio_le_writew(uint16_t val, void *addr);
340void rmmio_le_writel(uint32_t val, void *addr);
341#define pci_rmmio_writeb rmmio_le_writeb
342#define pci_rmmio_writew rmmio_le_writew
343#define pci_rmmio_writel rmmio_le_writel
344void rmmio_valb(void *addr);
345void rmmio_valw(void *addr);
346void rmmio_vall(void *addr);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000347
348/* programmer.c */
349int noop_shutdown(void);
350void *fallback_map(const char *descr, unsigned long phys_addr, size_t len);
351void fallback_unmap(void *virt_addr, size_t len);
352uint8_t noop_chip_readb(const chipaddr addr);
353void noop_chip_writeb(uint8_t val, chipaddr addr);
354void fallback_chip_writew(uint16_t val, chipaddr addr);
355void fallback_chip_writel(uint32_t val, chipaddr addr);
356void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
357uint16_t fallback_chip_readw(const chipaddr addr);
358uint32_t fallback_chip_readl(const chipaddr addr);
359void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
360
361/* dummyflasher.c */
362#if CONFIG_DUMMY == 1
363int dummy_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000364void *dummy_map(const char *descr, unsigned long phys_addr, size_t len);
365void dummy_unmap(void *virt_addr, size_t len);
366void dummy_chip_writeb(uint8_t val, chipaddr addr);
367void dummy_chip_writew(uint16_t val, chipaddr addr);
368void dummy_chip_writel(uint32_t val, chipaddr addr);
369void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
370uint8_t dummy_chip_readb(const chipaddr addr);
371uint16_t dummy_chip_readw(const chipaddr addr);
372uint32_t dummy_chip_readl(const chipaddr addr);
373void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000374#endif
375
376/* nic3com.c */
377#if CONFIG_NIC3COM == 1
378int nic3com_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000379void nic3com_chip_writeb(uint8_t val, chipaddr addr);
380uint8_t nic3com_chip_readb(const chipaddr addr);
381extern const struct pcidev_status nics_3com[];
382#endif
383
384/* gfxnvidia.c */
385#if CONFIG_GFXNVIDIA == 1
386int gfxnvidia_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000387void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr);
388uint8_t gfxnvidia_chip_readb(const chipaddr addr);
389extern const struct pcidev_status gfx_nvidia[];
390#endif
391
392/* drkaiser.c */
393#if CONFIG_DRKAISER == 1
394int drkaiser_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000395void drkaiser_chip_writeb(uint8_t val, chipaddr addr);
396uint8_t drkaiser_chip_readb(const chipaddr addr);
397extern const struct pcidev_status drkaiser_pcidev[];
398#endif
399
400/* nicrealtek.c */
401#if CONFIG_NICREALTEK == 1
402int nicrealtek_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000403void nicrealtek_chip_writeb(uint8_t val, chipaddr addr);
404uint8_t nicrealtek_chip_readb(const chipaddr addr);
405extern const struct pcidev_status nics_realtek[];
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000406#endif
407
408/* nicnatsemi.c */
409#if CONFIG_NICNATSEMI == 1
410int nicnatsemi_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000411void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr);
412uint8_t nicnatsemi_chip_readb(const chipaddr addr);
413extern const struct pcidev_status nics_natsemi[];
414#endif
415
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000416/* nicintel.c */
417#if CONFIG_NICINTEL == 1
418int nicintel_init(void);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000419void nicintel_chip_writeb(uint8_t val, chipaddr addr);
420uint8_t nicintel_chip_readb(const chipaddr addr);
421extern const struct pcidev_status nics_intel[];
422#endif
423
Idwer Vollering004f4b72010-09-03 18:21:21 +0000424/* nicintel_spi.c */
425#if CONFIG_NICINTEL_SPI == 1
426int nicintel_spi_init(void);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000427extern const struct pcidev_status nics_intel_spi[];
428#endif
429
Mark Marshall90021f22010-12-03 14:48:11 +0000430/* ogp_spi.c */
431#if CONFIG_OGP_SPI == 1
432int ogp_spi_init(void);
Mark Marshall90021f22010-12-03 14:48:11 +0000433extern const struct pcidev_status ogp_spi[];
434#endif
435
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000436/* satamv.c */
437#if CONFIG_SATAMV == 1
438int satamv_init(void);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000439void satamv_chip_writeb(uint8_t val, chipaddr addr);
440uint8_t satamv_chip_readb(const chipaddr addr);
441extern const struct pcidev_status satas_mv[];
442#endif
443
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000444/* satasii.c */
445#if CONFIG_SATASII == 1
446int satasii_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000447void satasii_chip_writeb(uint8_t val, chipaddr addr);
448uint8_t satasii_chip_readb(const chipaddr addr);
449extern const struct pcidev_status satas_sii[];
450#endif
451
452/* atahpt.c */
453#if CONFIG_ATAHPT == 1
454int atahpt_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000455void atahpt_chip_writeb(uint8_t val, chipaddr addr);
456uint8_t atahpt_chip_readb(const chipaddr addr);
457extern const struct pcidev_status ata_hpt[];
458#endif
459
460/* ft2232_spi.c */
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000461#if CONFIG_FT2232_SPI == 1
462struct usbdev_status {
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000463 uint16_t vendor_id;
464 uint16_t device_id;
465 int status;
466 const char *vendor_name;
467 const char *device_name;
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000468};
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000469int ft2232_spi_init(void);
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000470extern const struct usbdev_status devs_ft2232spi[];
471void print_supported_usbdevs(const struct usbdev_status *devs);
472#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000473
474/* rayer_spi.c */
475#if CONFIG_RAYER_SPI == 1
476int rayer_spi_init(void);
477#endif
478
479/* bitbang_spi.c */
480int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000481int bitbang_spi_shutdown(const struct bitbang_spi_master *master);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000482
483/* buspirate_spi.c */
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000484#if CONFIG_BUSPIRATE_SPI == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000485int buspirate_spi_init(void);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000486#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000487
488/* dediprog.c */
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000489#if CONFIG_DEDIPROG == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000490int dediprog_init(void);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000491#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000492
493/* flashrom.c */
494struct decode_sizes {
495 uint32_t parallel;
496 uint32_t lpc;
497 uint32_t fwh;
498 uint32_t spi;
499};
500extern struct decode_sizes max_rom_decode;
501extern int programmer_may_write;
502extern unsigned long flashbase;
Carl-Daniel Hailfinger4c823182011-05-04 00:39:50 +0000503void check_chip_supported(const struct flashchip *flash);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000504int check_max_decode(enum chipbustype buses, uint32_t size);
Stefan Tauner66652442011-06-26 17:38:17 +0000505char *extract_programmer_param(const char *param_name);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000506
507/* layout.c */
508int show_id(uint8_t *bios, int size, int force);
509
510/* spi.c */
511enum spi_controller {
512 SPI_CONTROLLER_NONE,
513#if CONFIG_INTERNAL == 1
514#if defined(__i386__) || defined(__x86_64__)
515 SPI_CONTROLLER_ICH7,
516 SPI_CONTROLLER_ICH9,
David Hendricks4e748392011-02-28 23:58:15 +0000517 SPI_CONTROLLER_IT85XX,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000518 SPI_CONTROLLER_IT87XX,
519 SPI_CONTROLLER_SB600,
520 SPI_CONTROLLER_VIA,
521 SPI_CONTROLLER_WBSIO,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000522#endif
523#endif
524#if CONFIG_FT2232_SPI == 1
525 SPI_CONTROLLER_FT2232,
526#endif
527#if CONFIG_DUMMY == 1
528 SPI_CONTROLLER_DUMMY,
529#endif
530#if CONFIG_BUSPIRATE_SPI == 1
531 SPI_CONTROLLER_BUSPIRATE,
532#endif
533#if CONFIG_DEDIPROG == 1
534 SPI_CONTROLLER_DEDIPROG,
535#endif
Michael Karcherb9dbe482011-05-11 17:07:07 +0000536#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__)))
537 SPI_CONTROLLER_BITBANG,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000538#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000539};
540extern const int spi_programmer_count;
Michael Karcher62797512011-05-11 17:07:02 +0000541
542#define MAX_DATA_UNSPECIFIED 0
543#define MAX_DATA_READ_UNLIMITED 64 * 1024
544#define MAX_DATA_WRITE_UNLIMITED 256
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000545struct spi_programmer {
Michael Karcherb9dbe482011-05-11 17:07:07 +0000546 enum spi_controller type;
Michael Karcher62797512011-05-11 17:07:02 +0000547 int max_data_read;
548 int max_data_write;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000549 int (*command)(unsigned int writecnt, unsigned int readcnt,
550 const unsigned char *writearr, unsigned char *readarr);
551 int (*multicommand)(struct spi_command *cmds);
552
553 /* Optimized functions for this programmer */
554 int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len);
555 int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len);
556};
557
Michael Karcherb9dbe482011-05-11 17:07:07 +0000558extern const struct spi_programmer *spi_programmer;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000559int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
560 const unsigned char *writearr, unsigned char *readarr);
561int default_spi_send_multicommand(struct spi_command *cmds);
Michael Karcher62797512011-05-11 17:07:02 +0000562int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
563int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000564void register_spi_programmer(const struct spi_programmer *programmer);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000565
566/* ichspi.c */
567#if CONFIG_INTERNAL == 1
568extern uint32_t ichspi_bbar;
569int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
570 int ich_generation);
571int via_init_spi(struct pci_dev *dev);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000572
David Hendricks4e748392011-02-28 23:58:15 +0000573/* it85spi.c */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000574int it85xx_spi_init(struct superio s);
David Hendricks4e748392011-02-28 23:58:15 +0000575
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000576/* it87spi.c */
577void enter_conf_mode_ite(uint16_t port);
578void exit_conf_mode_ite(uint16_t port);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000579void probe_superio_ite(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000580int init_superio_ite(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000581
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000582/* mcp6x_spi.c */
583int mcp6x_spi_init(int want_spi);
584
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000585/* sb600spi.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000586int sb600_probe_spi(struct pci_dev *dev);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000587
588/* wbsio_spi.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000589int wbsio_check_for_spi(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000590#endif
591
592/* serprog.c */
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000593#if CONFIG_SERPROG == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000594int serprog_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000595void serprog_chip_writeb(uint8_t val, chipaddr addr);
596uint8_t serprog_chip_readb(const chipaddr addr);
597void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
598void serprog_delay(int delay);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000599#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000600
601/* serial.c */
602#if _WIN32
603typedef HANDLE fdtype;
604#else
605typedef int fdtype;
606#endif
607
608void sp_flush_incoming(void);
609fdtype sp_openserport(char *dev, unsigned int baud);
610void __attribute__((noreturn)) sp_die(char *msg);
611extern fdtype sp_fd;
David Hendricks8bb20212011-06-14 01:35:36 +0000612/* expose serialport_shutdown as it's currently used by buspirate */
613int serialport_shutdown(void *data);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000614int serialport_write(unsigned char *buf, unsigned int writecnt);
615int serialport_read(unsigned char *buf, unsigned int readcnt);
616
617#endif /* !__PROGRAMMER_H__ */