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Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00004 * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +00005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00008 * the Free Software Foundation; version 2 of the License.
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +00009 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000014 */
15
Sergii Dmytruk59151a42021-11-08 00:05:12 +020016#include <assert.h>
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000017#include <string.h>
Felix Singer2fb53b12022-08-19 03:29:32 +020018#include <stdbool.h>
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000019#include <stdlib.h>
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +000020#include <stdio.h>
21#include <ctype.h>
Stefan Tauner5e695ab2012-05-06 17:03:40 +000022#include <errno.h>
Nico Huberab696292021-06-09 18:10:07 +020023#include <sys/types.h>
24#include <sys/stat.h>
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000025#include "flash.h"
Carl-Daniel Hailfinger1b0ba892010-06-20 10:58:32 +000026#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000028
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +000029#include "spi.h"
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +020030#include "writeprotect.h"
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +000031
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +000032enum emu_chip {
33 EMULATE_NONE,
34 EMULATE_ST_M25P10_RES,
35 EMULATE_SST_SST25VF040_REMS,
36 EMULATE_SST_SST25VF032B,
Stefan Tauner0b9df972012-05-07 22:12:16 +000037 EMULATE_MACRONIX_MX25L6436,
Nico Huberf9632d82019-01-20 11:23:49 +010038 EMULATE_WINBOND_W25Q128FV,
Nico Huber4203a472022-05-28 17:28:05 +020039 EMULATE_SPANSION_S25FL128L,
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +000040};
Stefan Tauner0b9df972012-05-07 22:12:16 +000041
Lachlan Bishopc753c402020-09-10 14:57:05 +100042struct emu_data {
43 enum emu_chip emu_chip;
44 char *emu_persistent_image;
45 unsigned int emu_chip_size;
Sergii Dmytruk59151a42021-11-08 00:05:12 +020046 /* Note: W25Q128FV doesn't change value of SR2 if it's not provided, but
47 * even its previous generations do, so don't forget to update
Nico Huberbbccdb22022-05-28 16:48:26 +020048 * WRSR code on enabling WRSR_EXT2 for more chips. */
49 bool emu_wrsr_ext2;
50 bool emu_wrsr_ext3;
Felix Singer2fb53b12022-08-19 03:29:32 +020051 bool emu_modified; /* is the image modified since reading it? */
Sergii Dmytruk59151a42021-11-08 00:05:12 +020052 uint8_t emu_status[3];
53 uint8_t emu_status_len; /* number of emulated status registers */
Lachlan Bishopc753c402020-09-10 14:57:05 +100054 unsigned int emu_max_byteprogram_size;
55 unsigned int emu_max_aai_size;
56 unsigned int emu_jedec_se_size;
57 unsigned int emu_jedec_be_52_size;
58 unsigned int emu_jedec_be_d8_size;
59 unsigned int emu_jedec_ce_60_size;
60 unsigned int emu_jedec_ce_c7_size;
61 unsigned char spi_blacklist[256];
62 unsigned char spi_ignorelist[256];
63 unsigned int spi_blacklist_size;
64 unsigned int spi_ignorelist_size;
Edward O'Callaghan94250222021-05-20 20:34:02 +100065
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +020066 bool hwwp; /* state of hardware write protection */
67 /* wp_start == wp_end when write-protection is disabled */
68 uint32_t wp_start;
69 uint32_t wp_end;
70
Edward O'Callaghanb1313422021-05-20 20:27:59 +100071 unsigned int spi_write_256_chunksize;
Edward O'Callaghan94250222021-05-20 20:34:02 +100072 uint8_t *flashchip_contents;
Lachlan Bishopc753c402020-09-10 14:57:05 +100073};
74
Stefan Tauner0b9df972012-05-07 22:12:16 +000075/* A legit complete SFDP table based on the MX25L6436E (rev. 1.8) datasheet. */
Stefan Tauner67d163d2013-01-15 17:37:48 +000076static const uint8_t sfdp_table[] = {
Stefan Tauner0b9df972012-05-07 22:12:16 +000077 0x53, 0x46, 0x44, 0x50, // @0x00: SFDP signature
78 0x00, 0x01, 0x01, 0xFF, // @0x04: revision 1.0, 2 headers
79 0x00, 0x00, 0x01, 0x09, // @0x08: JEDEC SFDP header rev. 1.0, 9 DW long
80 0x1C, 0x00, 0x00, 0xFF, // @0x0C: PTP0 = 0x1C (instead of 0x30)
81 0xC2, 0x00, 0x01, 0x04, // @0x10: Macronix header rev. 1.0, 4 DW long
82 0x48, 0x00, 0x00, 0xFF, // @0x14: PTP1 = 0x48 (instead of 0x60)
83 0xFF, 0xFF, 0xFF, 0xFF, // @0x18: hole.
84 0xE5, 0x20, 0xC9, 0xFF, // @0x1C: SFDP parameter table start
85 0xFF, 0xFF, 0xFF, 0x03, // @0x20
86 0x00, 0xFF, 0x08, 0x6B, // @0x24
87 0x08, 0x3B, 0x00, 0xFF, // @0x28
88 0xEE, 0xFF, 0xFF, 0xFF, // @0x2C
89 0xFF, 0xFF, 0x00, 0x00, // @0x30
90 0xFF, 0xFF, 0x00, 0xFF, // @0x34
91 0x0C, 0x20, 0x0F, 0x52, // @0x38
92 0x10, 0xD8, 0x00, 0xFF, // @0x3C: SFDP parameter table end
93 0xFF, 0xFF, 0xFF, 0xFF, // @0x40: hole.
94 0xFF, 0xFF, 0xFF, 0xFF, // @0x44: hole.
95 0x00, 0x36, 0x00, 0x27, // @0x48: Macronix parameter table start
96 0xF4, 0x4F, 0xFF, 0xFF, // @0x4C
97 0xD9, 0xC8, 0xFF, 0xFF, // @0x50
98 0xFF, 0xFF, 0xFF, 0xFF, // @0x54: Macronix parameter table end
99};
100
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000101
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000102
Edward O'Callaghan5eca4272020-04-12 17:27:53 +1000103static int dummy_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
Mark Marshallf20b7be2014-05-09 21:16:21 +0000104 const unsigned char *writearr, unsigned char *readarr);
105static int dummy_spi_write_256(struct flashctx *flash, const uint8_t *buf,
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000106 unsigned int start, unsigned int len);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000107static void dummy_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
108static void dummy_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr);
109static void dummy_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr);
110static void dummy_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
111static uint8_t dummy_chip_readb(const struct flashctx *flash, const chipaddr addr);
112static uint16_t dummy_chip_readw(const struct flashctx *flash, const chipaddr addr);
113static uint32_t dummy_chip_readl(const struct flashctx *flash, const chipaddr addr);
114static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000115
Nico Huber03f3a6d2021-05-11 17:53:34 +0200116static const struct spi_master spi_master_dummyflasher = {
Nico Huber1cf407b2017-11-10 20:18:23 +0100117 .features = SPI_MASTER_4BA,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000118 .max_data_read = MAX_DATA_READ_UNLIMITED,
119 .max_data_write = MAX_DATA_UNSPECIFIED,
120 .command = dummy_spi_send_command,
121 .multicommand = default_spi_send_multicommand,
122 .read = default_spi_read,
123 .write_256 = dummy_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +0000124 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +0000125};
David Hendricks8bb20212011-06-14 01:35:36 +0000126
Edward O'Callaghanf7504a92021-05-20 20:21:13 +1000127static const struct par_master par_master_dummyflasher = {
Thomas Heijligen43040f22022-06-23 14:38:35 +0200128 .chip_readb = dummy_chip_readb,
129 .chip_readw = dummy_chip_readw,
130 .chip_readl = dummy_chip_readl,
131 .chip_readn = dummy_chip_readn,
132 .chip_writeb = dummy_chip_writeb,
133 .chip_writew = dummy_chip_writew,
134 .chip_writel = dummy_chip_writel,
135 .chip_writen = dummy_chip_writen,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000136};
137
David Hendricks8bb20212011-06-14 01:35:36 +0000138static int dummy_shutdown(void *data)
139{
140 msg_pspew("%s\n", __func__);
Lachlan Bishopc753c402020-09-10 14:57:05 +1000141 struct emu_data *emu_data = (struct emu_data *)data;
142 if (emu_data->emu_chip != EMULATE_NONE) {
143 if (emu_data->emu_persistent_image && emu_data->emu_modified) {
144 msg_pdbg("Writing %s\n", emu_data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000145 write_buf_to_file(emu_data->flashchip_contents,
Lachlan Bishopc753c402020-09-10 14:57:05 +1000146 emu_data->emu_chip_size,
147 emu_data->emu_persistent_image);
David Hendricks8bb20212011-06-14 01:35:36 +0000148 }
Angel Pons02b9ae22021-05-25 12:46:43 +0200149 free(emu_data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000150 free(emu_data->flashchip_contents);
David Hendricks8bb20212011-06-14 01:35:36 +0000151 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000152 free(data);
David Hendricks8bb20212011-06-14 01:35:36 +0000153 return 0;
154}
155
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000156static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_supported)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000157{
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000158 char *bustext = NULL;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000159 char *tmp = NULL;
Nico Huber519be662018-12-23 20:03:35 +0100160 unsigned int i;
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000161 char *endptr;
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000162 char *status = NULL;
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000163
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000164 bustext = extract_programmer_param("bus");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000165 msg_pdbg("Requested buses are: %s\n", bustext ? bustext : "default");
166 if (!bustext)
167 bustext = strdup("parallel+lpc+fwh+spi");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000168 /* Convert the parameters to lowercase. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000169 tolower_string(bustext);
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000170
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000171 *dummy_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000172 if (strstr(bustext, "parallel")) {
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000173 *dummy_buses_supported |= BUS_PARALLEL;
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000174 msg_pdbg("Enabling support for %s flash.\n", "parallel");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000175 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000176 if (strstr(bustext, "lpc")) {
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000177 *dummy_buses_supported |= BUS_LPC;
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000178 msg_pdbg("Enabling support for %s flash.\n", "LPC");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000179 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000180 if (strstr(bustext, "fwh")) {
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000181 *dummy_buses_supported |= BUS_FWH;
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000182 msg_pdbg("Enabling support for %s flash.\n", "FWH");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000183 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000184 if (strstr(bustext, "spi")) {
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000185 *dummy_buses_supported |= BUS_SPI;
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000186 msg_pdbg("Enabling support for %s flash.\n", "SPI");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000187 }
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000188 if (*dummy_buses_supported == BUS_NONE)
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000189 msg_pdbg("Support for all flash bus types disabled.\n");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000190 free(bustext);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000191
192 tmp = extract_programmer_param("spi_write_256_chunksize");
193 if (tmp) {
Edward O'Callaghanb1313422021-05-20 20:27:59 +1000194 data->spi_write_256_chunksize = strtoul(tmp, &endptr, 0);
195 if (*endptr != '\0' || data->spi_write_256_chunksize < 1) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000196 msg_perr("invalid spi_write_256_chunksize\n");
Edward O'Callaghanc785f882021-05-23 22:14:36 +1000197 free(tmp);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000198 return 1;
199 }
Edward O'Callaghanc785f882021-05-23 22:14:36 +1000200 free(tmp);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000201 }
202
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000203 tmp = extract_programmer_param("spi_blacklist");
204 if (tmp) {
205 i = strlen(tmp);
206 if (!strncmp(tmp, "0x", 2)) {
207 i -= 2;
208 memmove(tmp, tmp + 2, i + 1);
209 }
210 if ((i > 512) || (i % 2)) {
211 msg_perr("Invalid SPI command blacklist length\n");
212 free(tmp);
213 return 1;
214 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000215 data->spi_blacklist_size = i / 2;
216 for (i = 0; i < data->spi_blacklist_size * 2; i++) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000217 if (!isxdigit((unsigned char)tmp[i])) {
218 msg_perr("Invalid char \"%c\" in SPI command "
219 "blacklist\n", tmp[i]);
220 free(tmp);
221 return 1;
222 }
223 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000224 for (i = 0; i < data->spi_blacklist_size; i++) {
Carl-Daniel Hailfinger5b554712012-02-16 01:43:06 +0000225 unsigned int tmp2;
226 /* SCNx8 is apparently not supported by MSVC (and thus
227 * MinGW), so work around it with an extra variable
228 */
229 sscanf(tmp + i * 2, "%2x", &tmp2);
Lachlan Bishopc753c402020-09-10 14:57:05 +1000230 data->spi_blacklist[i] = (uint8_t)tmp2;
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000231 }
232 msg_pdbg("SPI blacklist is ");
Lachlan Bishopc753c402020-09-10 14:57:05 +1000233 for (i = 0; i < data->spi_blacklist_size; i++)
234 msg_pdbg("%02x ", data->spi_blacklist[i]);
235 msg_pdbg(", size %u\n", data->spi_blacklist_size);
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000236 }
237 free(tmp);
238
239 tmp = extract_programmer_param("spi_ignorelist");
240 if (tmp) {
241 i = strlen(tmp);
242 if (!strncmp(tmp, "0x", 2)) {
243 i -= 2;
244 memmove(tmp, tmp + 2, i + 1);
245 }
246 if ((i > 512) || (i % 2)) {
247 msg_perr("Invalid SPI command ignorelist length\n");
248 free(tmp);
249 return 1;
250 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000251 data->spi_ignorelist_size = i / 2;
252 for (i = 0; i < data->spi_ignorelist_size * 2; i++) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000253 if (!isxdigit((unsigned char)tmp[i])) {
254 msg_perr("Invalid char \"%c\" in SPI command "
255 "ignorelist\n", tmp[i]);
256 free(tmp);
257 return 1;
258 }
259 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000260 for (i = 0; i < data->spi_ignorelist_size; i++) {
Carl-Daniel Hailfinger5b554712012-02-16 01:43:06 +0000261 unsigned int tmp2;
262 /* SCNx8 is apparently not supported by MSVC (and thus
263 * MinGW), so work around it with an extra variable
264 */
265 sscanf(tmp + i * 2, "%2x", &tmp2);
Lachlan Bishopc753c402020-09-10 14:57:05 +1000266 data->spi_ignorelist[i] = (uint8_t)tmp2;
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000267 }
268 msg_pdbg("SPI ignorelist is ");
Lachlan Bishopc753c402020-09-10 14:57:05 +1000269 for (i = 0; i < data->spi_ignorelist_size; i++)
270 msg_pdbg("%02x ", data->spi_ignorelist[i]);
271 msg_pdbg(", size %u\n", data->spi_ignorelist_size);
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000272 }
273 free(tmp);
274
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200275 tmp = extract_programmer_param("hwwp");
276 if (tmp) {
277 if (!strcmp(tmp, "yes")) {
278 msg_pdbg("Emulated chip will have hardware WP enabled\n");
279 data->hwwp = true;
280 } else if (!strcmp(tmp, "no")) {
281 msg_pdbg("Emulated chip will have hardware WP disabled\n");
282 } else {
283 msg_perr("hwwp can be \"yes\" or \"no\"\n");
284 free(tmp);
285 return 1;
286 }
287 free(tmp);
288 }
289
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000290 tmp = extract_programmer_param("emulate");
291 if (!tmp) {
292 msg_pdbg("Not emulating any flash chip.\n");
293 /* Nothing else to do. */
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000294 return 0;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000295 }
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000296
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000297 if (!strcmp(tmp, "M25P10.RES")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000298 data->emu_chip = EMULATE_ST_M25P10_RES;
299 data->emu_chip_size = 128 * 1024;
300 data->emu_max_byteprogram_size = 128;
301 data->emu_max_aai_size = 0;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200302 data->emu_status_len = 1;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000303 data->emu_jedec_se_size = 0;
304 data->emu_jedec_be_52_size = 0;
305 data->emu_jedec_be_d8_size = 32 * 1024;
306 data->emu_jedec_ce_60_size = 0;
307 data->emu_jedec_ce_c7_size = data->emu_chip_size;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000308 msg_pdbg("Emulating ST M25P10.RES SPI flash chip (RES, page "
309 "write)\n");
310 }
311 if (!strcmp(tmp, "SST25VF040.REMS")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000312 data->emu_chip = EMULATE_SST_SST25VF040_REMS;
313 data->emu_chip_size = 512 * 1024;
314 data->emu_max_byteprogram_size = 1;
315 data->emu_max_aai_size = 0;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200316 data->emu_status_len = 1;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000317 data->emu_jedec_se_size = 4 * 1024;
318 data->emu_jedec_be_52_size = 32 * 1024;
319 data->emu_jedec_be_d8_size = 0;
320 data->emu_jedec_ce_60_size = data->emu_chip_size;
321 data->emu_jedec_ce_c7_size = 0;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000322 msg_pdbg("Emulating SST SST25VF040.REMS SPI flash chip (REMS, "
323 "byte write)\n");
324 }
325 if (!strcmp(tmp, "SST25VF032B")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000326 data->emu_chip = EMULATE_SST_SST25VF032B;
327 data->emu_chip_size = 4 * 1024 * 1024;
328 data->emu_max_byteprogram_size = 1;
329 data->emu_max_aai_size = 2;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200330 data->emu_status_len = 1;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000331 data->emu_jedec_se_size = 4 * 1024;
332 data->emu_jedec_be_52_size = 32 * 1024;
333 data->emu_jedec_be_d8_size = 64 * 1024;
334 data->emu_jedec_ce_60_size = data->emu_chip_size;
335 data->emu_jedec_ce_c7_size = data->emu_chip_size;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000336 msg_pdbg("Emulating SST SST25VF032B SPI flash chip (RDID, AAI "
337 "write)\n");
338 }
Stefan Tauner0b9df972012-05-07 22:12:16 +0000339 if (!strcmp(tmp, "MX25L6436")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000340 data->emu_chip = EMULATE_MACRONIX_MX25L6436;
341 data->emu_chip_size = 8 * 1024 * 1024;
342 data->emu_max_byteprogram_size = 256;
343 data->emu_max_aai_size = 0;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200344 data->emu_status_len = 1;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000345 data->emu_jedec_se_size = 4 * 1024;
346 data->emu_jedec_be_52_size = 32 * 1024;
347 data->emu_jedec_be_d8_size = 64 * 1024;
348 data->emu_jedec_ce_60_size = data->emu_chip_size;
349 data->emu_jedec_ce_c7_size = data->emu_chip_size;
Stefan Tauner0b9df972012-05-07 22:12:16 +0000350 msg_pdbg("Emulating Macronix MX25L6436 SPI flash chip (RDID, "
351 "SFDP)\n");
352 }
Nico Huberf9632d82019-01-20 11:23:49 +0100353 if (!strcmp(tmp, "W25Q128FV")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000354 data->emu_chip = EMULATE_WINBOND_W25Q128FV;
Nico Huberbbccdb22022-05-28 16:48:26 +0200355 data->emu_wrsr_ext2 = true;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000356 data->emu_chip_size = 16 * 1024 * 1024;
357 data->emu_max_byteprogram_size = 256;
358 data->emu_max_aai_size = 0;
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200359 data->emu_status_len = 3;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000360 data->emu_jedec_se_size = 4 * 1024;
361 data->emu_jedec_be_52_size = 32 * 1024;
362 data->emu_jedec_be_d8_size = 64 * 1024;
363 data->emu_jedec_ce_60_size = data->emu_chip_size;
364 data->emu_jedec_ce_c7_size = data->emu_chip_size;
Nico Huberf9632d82019-01-20 11:23:49 +0100365 msg_pdbg("Emulating Winbond W25Q128FV SPI flash chip (RDID)\n");
366 }
Nico Huber4203a472022-05-28 17:28:05 +0200367 if (!strcmp(tmp, "S25FL128L")) {
368 data->emu_chip = EMULATE_SPANSION_S25FL128L;
369 data->emu_wrsr_ext2 = true;
370 data->emu_wrsr_ext3 = true;
371 data->emu_chip_size = 16 * 1024 * 1024;
372 data->emu_max_byteprogram_size = 256;
373 data->emu_max_aai_size = 0;
374 data->emu_status_len = 3;
375 data->emu_jedec_se_size = 4 * 1024;
376 data->emu_jedec_be_52_size = 32 * 1024;
377 data->emu_jedec_be_d8_size = 64 * 1024;
378 data->emu_jedec_ce_60_size = data->emu_chip_size;
379 data->emu_jedec_ce_c7_size = data->emu_chip_size;
380 msg_pdbg("Emulating Spansion S25FL128L SPI flash chip (RES, RDID, WP)\n");
381 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000382 if (data->emu_chip == EMULATE_NONE) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000383 msg_perr("Invalid chip specified for emulation: %s\n", tmp);
384 free(tmp);
385 return 1;
386 }
387 free(tmp);
David Hendricks8bb20212011-06-14 01:35:36 +0000388
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000389 status = extract_programmer_param("spi_status");
390 if (status) {
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200391 unsigned int emu_status;
392
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000393 errno = 0;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200394 emu_status = strtoul(status, &endptr, 0);
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000395 if (errno != 0 || status == endptr) {
Angel Ponsc2484642021-05-25 13:03:24 +0200396 free(status);
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000397 msg_perr("Error: initial status register specified, "
398 "but the value could not be converted.\n");
399 return 1;
400 }
Angel Ponsc2484642021-05-25 13:03:24 +0200401 free(status);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200402
403 data->emu_status[0] = emu_status;
404 data->emu_status[1] = emu_status >> 8;
405 data->emu_status[2] = emu_status >> 16;
406
407 if (data->emu_status_len == 3) {
408 msg_pdbg("Initial status registers:\n"
409 "\tSR1 is set to 0x%02x\n"
410 "\tSR2 is set to 0x%02x\n"
411 "\tSR3 is set to 0x%02x\n",
412 data->emu_status[0], data->emu_status[1], data->emu_status[2]);
413 } else if (data->emu_status_len == 2) {
414 msg_pdbg("Initial status registers:\n"
415 "\tSR1 is set to 0x%02x\n"
416 "\tSR2 is set to 0x%02x\n",
417 data->emu_status[0], data->emu_status[1]);
418 } else {
419 msg_pdbg("Initial status register is set to 0x%02x.\n",
420 data->emu_status[0]);
421 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000422 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000423
Angel Pons328898a2021-05-25 12:56:18 +0200424 data->flashchip_contents = malloc(data->emu_chip_size);
425 if (!data->flashchip_contents) {
426 msg_perr("Out of memory!\n");
427 return 1;
428 }
429
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000430
431 return 0;
432}
433
Thomas Heijligencc853d82021-05-04 15:32:17 +0200434static int dummy_init(void)
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000435{
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000436 struct stat image_stat;
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000437
Nico Huber4e9e99c2021-06-09 18:08:48 +0200438 struct emu_data *data = calloc(1, sizeof(*data));
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000439 if (!data) {
440 msg_perr("Out of memory!\n");
441 return 1;
442 }
443 data->emu_chip = EMULATE_NONE;
Edward O'Callaghanb1313422021-05-20 20:27:59 +1000444 data->spi_write_256_chunksize = 256;
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000445
446 msg_pspew("%s\n", __func__);
447
448 enum chipbustype dummy_buses_supported;
449 if (init_data(data, &dummy_buses_supported)) {
450 free(data);
451 return 1;
452 }
453
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000454 if (data->emu_chip == EMULATE_NONE) {
455 msg_pdbg("Not emulating any flash chip.\n");
456 /* Nothing else to do. */
457 goto dummy_init_out;
458 }
459
Lachlan Bishopc753c402020-09-10 14:57:05 +1000460 msg_pdbg("Filling fake flash chip with 0xff, size %i\n", data->emu_chip_size);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000461 memset(data->flashchip_contents, 0xff, data->emu_chip_size);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000462
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000463 /* Will be freed by shutdown function if necessary. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000464 data->emu_persistent_image = extract_programmer_param("image");
465 if (!data->emu_persistent_image) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000466 /* Nothing else to do. */
David Hendricks8bb20212011-06-14 01:35:36 +0000467 goto dummy_init_out;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000468 }
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000469 /* We will silently (in default verbosity) ignore the file if it does not exist (yet) or the size does
470 * not match the emulated chip. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000471 if (!stat(data->emu_persistent_image, &image_stat)) {
Stefan Tauner23e10b82016-01-23 16:16:49 +0000472 msg_pdbg("Found persistent image %s, %jd B ",
Lachlan Bishopc753c402020-09-10 14:57:05 +1000473 data->emu_persistent_image, (intmax_t)image_stat.st_size);
474 if ((uintmax_t)image_stat.st_size == data->emu_chip_size) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000475 msg_pdbg("matches.\n");
Lachlan Bishopc753c402020-09-10 14:57:05 +1000476 msg_pdbg("Reading %s\n", data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000477 if (read_buf_from_file(data->flashchip_contents, data->emu_chip_size,
Lachlan Bishopc753c402020-09-10 14:57:05 +1000478 data->emu_persistent_image)) {
479 msg_perr("Unable to read %s\n", data->emu_persistent_image);
Angel Pons02b9ae22021-05-25 12:46:43 +0200480 free(data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000481 free(data->flashchip_contents);
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000482 free(data);
Jacob Garberca598da2019-08-12 10:44:17 -0600483 return 1;
484 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000485 } else {
486 msg_pdbg("doesn't match.\n");
487 }
488 }
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000489
David Hendricks8bb20212011-06-14 01:35:36 +0000490dummy_init_out:
Lachlan Bishopc753c402020-09-10 14:57:05 +1000491 if (register_shutdown(dummy_shutdown, data)) {
Angel Pons02b9ae22021-05-25 12:46:43 +0200492 free(data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000493 free(data->flashchip_contents);
Lachlan Bishopc753c402020-09-10 14:57:05 +1000494 free(data);
David Hendricks8bb20212011-06-14 01:35:36 +0000495 return 1;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000496 }
Edward O'Callaghan3fa321d2021-05-17 20:01:27 +1000497 if (dummy_buses_supported & BUS_NONSPI)
Edward O'Callaghanf7504a92021-05-20 20:21:13 +1000498 register_par_master(&par_master_dummyflasher,
Anastasia Klimchukb91a2032021-05-21 09:40:58 +1000499 dummy_buses_supported & BUS_NONSPI,
Anastasia Klimchuka7389152021-05-21 09:45:53 +1000500 data);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000501 if (dummy_buses_supported & BUS_SPI)
Nico Huber03f3a6d2021-05-11 17:53:34 +0200502 register_spi_master(&spi_master_dummyflasher, data);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000503
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000504 return 0;
505}
506
Thomas Heijligencc853d82021-05-04 15:32:17 +0200507static void *dummy_map(const char *descr, uintptr_t phys_addr, size_t len)
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000508{
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000509 msg_pspew("%s: Mapping %s, 0x%zx bytes at 0x%0*" PRIxPTR "\n",
Stefan Tauner0554ca52013-07-25 22:54:25 +0000510 __func__, descr, len, PRIxPTR_WIDTH, phys_addr);
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000511 return (void *)phys_addr;
512}
513
Thomas Heijligencc853d82021-05-04 15:32:17 +0200514static void dummy_unmap(void *virt_addr, size_t len)
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000515{
Stefan Tauner0554ca52013-07-25 22:54:25 +0000516 msg_pspew("%s: Unmapping 0x%zx bytes at %p\n", __func__, len, virt_addr);
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000517}
518
Mark Marshallf20b7be2014-05-09 21:16:21 +0000519static void dummy_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000520{
Stefan Taunerc2333752013-07-13 23:31:37 +0000521 msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%02x\n", __func__, addr, val);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000522}
523
Mark Marshallf20b7be2014-05-09 21:16:21 +0000524static void dummy_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000525{
Stefan Taunerc2333752013-07-13 23:31:37 +0000526 msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%04x\n", __func__, addr, val);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000527}
528
Mark Marshallf20b7be2014-05-09 21:16:21 +0000529static void dummy_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000530{
Stefan Taunerc2333752013-07-13 23:31:37 +0000531 msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%08x\n", __func__, addr, val);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000532}
533
Mark Marshallf20b7be2014-05-09 21:16:21 +0000534static void dummy_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len)
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000535{
536 size_t i;
Stefan Tauner0554ca52013-07-25 22:54:25 +0000537 msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, writing data (hex):", __func__, addr, len);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000538 for (i = 0; i < len; i++) {
539 if ((i % 16) == 0)
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000540 msg_pspew("\n");
541 msg_pspew("%02x ", buf[i]);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000542 }
543}
544
Mark Marshallf20b7be2014-05-09 21:16:21 +0000545static uint8_t dummy_chip_readb(const struct flashctx *flash, const chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000546{
Stefan Taunerc2333752013-07-13 23:31:37 +0000547 msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xff\n", __func__, addr);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000548 return 0xff;
549}
550
Mark Marshallf20b7be2014-05-09 21:16:21 +0000551static uint16_t dummy_chip_readw(const struct flashctx *flash, const chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000552{
Stefan Taunerc2333752013-07-13 23:31:37 +0000553 msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xffff\n", __func__, addr);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000554 return 0xffff;
555}
556
Mark Marshallf20b7be2014-05-09 21:16:21 +0000557static uint32_t dummy_chip_readl(const struct flashctx *flash, const chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000558{
Stefan Taunerc2333752013-07-13 23:31:37 +0000559 msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xffffffff\n", __func__, addr);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000560 return 0xffffffff;
561}
562
Mark Marshallf20b7be2014-05-09 21:16:21 +0000563static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len)
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000564{
Stefan Tauner0554ca52013-07-25 22:54:25 +0000565 msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, returning array of 0xff\n", __func__, addr, len);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000566 memset(buf, 0xff, len);
567 return;
568}
569
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200570static uint8_t get_reg_ro_bit_mask(const struct emu_data *data, enum flash_reg reg)
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200571{
572 /* Whoever adds a new register must not forget to update this function
573 or at least shouldn't use it incorrectly. */
574 assert(reg == STATUS1 || reg == STATUS2 || reg == STATUS3);
575
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200576 uint8_t ro_bits = reg == STATUS1 ? SPI_SR_WIP : 0;
577
578 if (data->emu_chip == EMULATE_WINBOND_W25Q128FV) {
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200579 const bool srp0 = (data->emu_status[0] >> 7);
580 const bool srp1 = (data->emu_status[1] & 1);
581
582 const bool wp_active = (srp1 || (srp0 && data->hwwp));
583
584 if (wp_active) {
585 ro_bits = 0xff;
586 } else if (reg == STATUS2) {
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200587 /* SUS (bit_7) and (R) (bit_2). */
588 ro_bits = 0x84;
589 /* Once any of the lock bits (LB[1..3]) are set, they
590 can't be unset. */
591 ro_bits |= data->emu_status[1] & (1 << 3);
592 ro_bits |= data->emu_status[1] & (1 << 4);
593 ro_bits |= data->emu_status[1] & (1 << 5);
594 } else if (reg == STATUS3) {
595 /* Four reserved bits. */
596 ro_bits = 0x1b;
597 }
598 }
599
Nico Huber4203a472022-05-28 17:28:05 +0200600 if (data->emu_chip == EMULATE_SPANSION_S25FL128L) {
601 const bool srp0 = (data->emu_status[0] >> 7);
602 const bool srp1 = (data->emu_status[1] & 1);
603
604 const bool wp_active = (srp1 || (srp0 && data->hwwp));
605
606 if (wp_active) {
607 ro_bits = 0xff;
608 } else if (reg == STATUS2) {
609 /* SUS (bit_7) */
610 ro_bits = 0x80;
611 /* Once any of the lock bits (LB[0..3]) are set, they
612 can't be unset. */
613 ro_bits |= data->emu_status[1] & (1 << 2);
614 ro_bits |= data->emu_status[1] & (1 << 3);
615 ro_bits |= data->emu_status[1] & (1 << 4);
616 ro_bits |= data->emu_status[1] & (1 << 5);
617 } else if (reg == STATUS3) {
618 /* Two reserved bits. */
619 ro_bits = 0x11;
620 }
621 }
622
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200623 return ro_bits;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200624}
625
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200626static void update_write_protection(struct emu_data *data)
627{
Nico Huber4203a472022-05-28 17:28:05 +0200628 if (data->emu_chip != EMULATE_WINBOND_W25Q128FV &&
629 data->emu_chip != EMULATE_SPANSION_S25FL128L)
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200630 return;
631
632 const struct wp_bits bits = {
633 .srp = data->emu_status[0] >> 7,
634 .srl = data->emu_status[1] & 1,
635
636 .bp_bit_count = 3,
637 .bp =
638 {
639 (data->emu_status[0] >> 2) & 1,
640 (data->emu_status[0] >> 3) & 1,
641 (data->emu_status[0] >> 4) & 1
642 },
643
644 .tb_bit_present = true,
645 .tb = (data->emu_status[0] >> 5) & 1,
646
647 .sec_bit_present = true,
648 .sec = (data->emu_status[0] >> 6) & 1,
649
650 .cmp_bit_present = true,
651 .cmp = (data->emu_status[1] >> 6) & 1,
652 };
653
654 size_t start;
655 size_t len;
656 decode_range_spi25(&start, &len, &bits, data->emu_chip_size);
657
658 data->wp_start = start;
659 data->wp_end = start + len;
660}
661
662/* Checks whether range intersects a write-protected area of the flash if one is
663 * defined. */
664static bool is_write_protected(const struct emu_data *data, uint32_t start, uint32_t len)
665{
666 if (len == 0)
667 return false;
668
669 const uint32_t last = start + len - 1;
670 return (start < data->wp_end && last >= data->wp_start);
671}
672
673/* Returns non-zero on error. */
674static int write_flash_data(struct emu_data *data, uint32_t start, uint32_t len, const uint8_t *buf)
675{
676 if (is_write_protected(data, start, len)) {
677 msg_perr("At least part of the write range is write protected!\n");
678 return 1;
679 }
680
681 memcpy(data->flashchip_contents + start, buf, len);
Felix Singer2fb53b12022-08-19 03:29:32 +0200682 data->emu_modified = true;
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200683 return 0;
684}
685
686/* Returns non-zero on error. */
687static int erase_flash_data(struct emu_data *data, uint32_t start, uint32_t len)
688{
689 if (is_write_protected(data, start, len)) {
690 msg_perr("At least part of the erase range is write protected!\n");
691 return 1;
692 }
693
694 memset(data->flashchip_contents + start, 0xff, len);
Felix Singer2fb53b12022-08-19 03:29:32 +0200695 data->emu_modified = true;
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200696 return 0;
697}
698
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000699static int emulate_spi_chip_response(unsigned int writecnt,
700 unsigned int readcnt,
701 const unsigned char *writearr,
Lachlan Bishopc753c402020-09-10 14:57:05 +1000702 unsigned char *readarr,
703 struct emu_data *data)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000704{
Stefan Tauner0b9df972012-05-07 22:12:16 +0000705 unsigned int offs, i, toread;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200706 uint8_t ro_bits;
Nico Huberbbccdb22022-05-28 16:48:26 +0200707 bool wrsr_ext2, wrsr_ext3;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000708 static int unsigned aai_offs;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000709 const unsigned char sst25vf040_rems_response[2] = {0xbf, 0x44};
710 const unsigned char sst25vf032b_rems_response[2] = {0xbf, 0x4a};
711 const unsigned char mx25l6436_rems_response[2] = {0xc2, 0x16};
Nico Huberf9632d82019-01-20 11:23:49 +0100712 const unsigned char w25q128fv_rems_response[2] = {0xef, 0x17};
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000713
714 if (writecnt == 0) {
715 msg_perr("No command sent to the chip!\n");
716 return 1;
717 }
Paul Menzelac427b22012-02-16 21:07:07 +0000718 /* spi_blacklist has precedence over spi_ignorelist. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000719 for (i = 0; i < data->spi_blacklist_size; i++) {
720 if (writearr[0] == data->spi_blacklist[i]) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000721 msg_pdbg("Refusing blacklisted SPI command 0x%02x\n",
Lachlan Bishopc753c402020-09-10 14:57:05 +1000722 data->spi_blacklist[i]);
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000723 return SPI_INVALID_OPCODE;
724 }
725 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000726 for (i = 0; i < data->spi_ignorelist_size; i++) {
727 if (writearr[0] == data->spi_ignorelist[i]) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000728 msg_cdbg("Ignoring ignorelisted SPI command 0x%02x\n",
Lachlan Bishopc753c402020-09-10 14:57:05 +1000729 data->spi_ignorelist[i]);
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000730 /* Return success because the command does not fail,
731 * it is simply ignored.
732 */
733 return 0;
734 }
735 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000736
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200737 if (data->emu_max_aai_size && (data->emu_status[0] & SPI_SR_AAI)) {
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000738 if (writearr[0] != JEDEC_AAI_WORD_PROGRAM &&
739 writearr[0] != JEDEC_WRDI &&
740 writearr[0] != JEDEC_RDSR) {
741 msg_perr("Forbidden opcode (0x%02x) attempted during "
742 "AAI sequence!\n", writearr[0]);
743 return 0;
744 }
745 }
746
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000747 switch (writearr[0]) {
748 case JEDEC_RES:
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000749 if (writecnt < JEDEC_RES_OUTSIZE)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000750 break;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000751 /* offs calculation is only needed for SST chips which treat RES like REMS. */
752 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
753 offs += writecnt - JEDEC_REMS_OUTSIZE;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000754 switch (data->emu_chip) {
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000755 case EMULATE_ST_M25P10_RES:
756 if (readcnt > 0)
757 memset(readarr, 0x10, readcnt);
758 break;
759 case EMULATE_SST_SST25VF040_REMS:
760 for (i = 0; i < readcnt; i++)
761 readarr[i] = sst25vf040_rems_response[(offs + i) % 2];
762 break;
763 case EMULATE_SST_SST25VF032B:
764 for (i = 0; i < readcnt; i++)
765 readarr[i] = sst25vf032b_rems_response[(offs + i) % 2];
766 break;
767 case EMULATE_MACRONIX_MX25L6436:
768 if (readcnt > 0)
769 memset(readarr, 0x16, readcnt);
770 break;
Nico Huberf9632d82019-01-20 11:23:49 +0100771 case EMULATE_WINBOND_W25Q128FV:
772 if (readcnt > 0)
773 memset(readarr, 0x17, readcnt);
774 break;
Nico Huber4203a472022-05-28 17:28:05 +0200775 case EMULATE_SPANSION_S25FL128L:
776 if (readcnt > 0)
777 readarr[0] = 0x60;
778 if (readcnt > 1)
779 readarr[1] = 0x18;
780 break;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000781 default: /* ignore */
782 break;
783 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000784 break;
785 case JEDEC_REMS:
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000786 /* REMS response has wraparound and uses an address parameter. */
787 if (writecnt < JEDEC_REMS_OUTSIZE)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000788 break;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000789 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
790 offs += writecnt - JEDEC_REMS_OUTSIZE;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000791 switch (data->emu_chip) {
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000792 case EMULATE_SST_SST25VF040_REMS:
793 for (i = 0; i < readcnt; i++)
794 readarr[i] = sst25vf040_rems_response[(offs + i) % 2];
795 break;
796 case EMULATE_SST_SST25VF032B:
797 for (i = 0; i < readcnt; i++)
798 readarr[i] = sst25vf032b_rems_response[(offs + i) % 2];
799 break;
800 case EMULATE_MACRONIX_MX25L6436:
801 for (i = 0; i < readcnt; i++)
802 readarr[i] = mx25l6436_rems_response[(offs + i) % 2];
803 break;
Nico Huberf9632d82019-01-20 11:23:49 +0100804 case EMULATE_WINBOND_W25Q128FV:
805 for (i = 0; i < readcnt; i++)
806 readarr[i] = w25q128fv_rems_response[(offs + i) % 2];
807 break;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000808 default: /* ignore */
809 break;
810 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000811 break;
812 case JEDEC_RDID:
Lachlan Bishopc753c402020-09-10 14:57:05 +1000813 switch (data->emu_chip) {
Stefan Tauner0b9df972012-05-07 22:12:16 +0000814 case EMULATE_SST_SST25VF032B:
815 if (readcnt > 0)
816 readarr[0] = 0xbf;
817 if (readcnt > 1)
818 readarr[1] = 0x25;
819 if (readcnt > 2)
820 readarr[2] = 0x4a;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000821 break;
Stefan Tauner0b9df972012-05-07 22:12:16 +0000822 case EMULATE_MACRONIX_MX25L6436:
823 if (readcnt > 0)
824 readarr[0] = 0xc2;
825 if (readcnt > 1)
826 readarr[1] = 0x20;
827 if (readcnt > 2)
828 readarr[2] = 0x17;
829 break;
Nico Huberf9632d82019-01-20 11:23:49 +0100830 case EMULATE_WINBOND_W25Q128FV:
831 if (readcnt > 0)
832 readarr[0] = 0xef;
833 if (readcnt > 1)
834 readarr[1] = 0x40;
835 if (readcnt > 2)
836 readarr[2] = 0x18;
837 break;
Nico Huber4203a472022-05-28 17:28:05 +0200838 case EMULATE_SPANSION_S25FL128L:
839 if (readcnt > 0)
840 readarr[0] = 0x01;
841 if (readcnt > 1)
842 readarr[1] = 0x60;
843 if (readcnt > 2)
844 readarr[2] = 0x18;
845 break;
Stefan Tauner0b9df972012-05-07 22:12:16 +0000846 default: /* ignore */
847 break;
848 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000849 break;
Stefan Tauner0b9df972012-05-07 22:12:16 +0000850 case JEDEC_RDSR:
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200851 memset(readarr, data->emu_status[0], readcnt);
852 break;
853 case JEDEC_RDSR2:
854 if (data->emu_status_len >= 2)
855 memset(readarr, data->emu_status[1], readcnt);
856 break;
857 case JEDEC_RDSR3:
858 if (data->emu_status_len >= 3)
859 memset(readarr, data->emu_status[2], readcnt);
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000860 break;
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000861 /* FIXME: this should be chip-specific. */
862 case JEDEC_EWSR:
863 case JEDEC_WREN:
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200864 data->emu_status[0] |= SPI_SR_WEL;
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000865 break;
866 case JEDEC_WRSR:
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200867 if (!(data->emu_status[0] & SPI_SR_WEL)) {
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000868 msg_perr("WRSR attempted, but WEL is 0!\n");
869 break;
870 }
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200871
Nico Huberbbccdb22022-05-28 16:48:26 +0200872 wrsr_ext2 = (writecnt == 3 && data->emu_wrsr_ext2);
873 wrsr_ext3 = (writecnt == 4 && data->emu_wrsr_ext3);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200874
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000875 /* FIXME: add some reasonable simulation of the busy flag */
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200876
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200877 ro_bits = get_reg_ro_bit_mask(data, STATUS1);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200878 data->emu_status[0] &= ro_bits;
879 data->emu_status[0] |= writearr[1] & ~ro_bits;
Nico Huberbbccdb22022-05-28 16:48:26 +0200880 if (wrsr_ext2 || wrsr_ext3) {
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200881 ro_bits = get_reg_ro_bit_mask(data, STATUS2);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200882 data->emu_status[1] &= ro_bits;
883 data->emu_status[1] |= writearr[2] & ~ro_bits;
884 }
Nico Huberbbccdb22022-05-28 16:48:26 +0200885 if (wrsr_ext3) {
886 ro_bits = get_reg_ro_bit_mask(data, STATUS3);
887 data->emu_status[2] &= ro_bits;
888 data->emu_status[2] |= writearr[3] & ~ro_bits;
889 }
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200890
Nico Huberbbccdb22022-05-28 16:48:26 +0200891 if (wrsr_ext3)
892 msg_pdbg2("WRSR wrote 0x%02x%02x%02x.\n", data->emu_status[2], data->emu_status[1], data->emu_status[0]);
893 else if (wrsr_ext2)
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200894 msg_pdbg2("WRSR wrote 0x%02x%02x.\n", data->emu_status[1], data->emu_status[0]);
895 else
896 msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status[0]);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200897
898 update_write_protection(data);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200899 break;
900 case JEDEC_WRSR2:
901 if (data->emu_status_len < 2)
902 break;
903 if (!(data->emu_status[0] & SPI_SR_WEL)) {
904 msg_perr("WRSR2 attempted, but WEL is 0!\n");
905 break;
906 }
907
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200908 ro_bits = get_reg_ro_bit_mask(data, STATUS2);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200909 data->emu_status[1] &= ro_bits;
910 data->emu_status[1] |= (writearr[1] & ~ro_bits);
911
912 msg_pdbg2("WRSR2 wrote 0x%02x.\n", data->emu_status[1]);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200913
914 update_write_protection(data);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200915 break;
916 case JEDEC_WRSR3:
917 if (data->emu_status_len < 3)
918 break;
919 if (!(data->emu_status[0] & SPI_SR_WEL)) {
920 msg_perr("WRSR3 attempted, but WEL is 0!\n");
921 break;
922 }
923
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200924 ro_bits = get_reg_ro_bit_mask(data, STATUS3);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200925 data->emu_status[2] &= ro_bits;
926 data->emu_status[2] |= (writearr[1] & ~ro_bits);
927
928 msg_pdbg2("WRSR3 wrote 0x%02x.\n", data->emu_status[2]);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000929 break;
930 case JEDEC_READ:
931 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
932 /* Truncate to emu_chip_size. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000933 offs %= data->emu_chip_size;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000934 if (readcnt > 0)
Edward O'Callaghan94250222021-05-20 20:34:02 +1000935 memcpy(readarr, data->flashchip_contents + offs, readcnt);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000936 break;
937 case JEDEC_BYTE_PROGRAM:
938 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
939 /* Truncate to emu_chip_size. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000940 offs %= data->emu_chip_size;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000941 if (writecnt < 5) {
942 msg_perr("BYTE PROGRAM size too short!\n");
943 return 1;
944 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000945 if (writecnt - 4 > data->emu_max_byteprogram_size) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000946 msg_perr("Max BYTE PROGRAM size exceeded!\n");
947 return 1;
948 }
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200949 if (write_flash_data(data, offs, writecnt - 4, writearr + 4)) {
950 msg_perr("Failed to program flash!\n");
951 return 1;
952 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000953 break;
954 case JEDEC_AAI_WORD_PROGRAM:
Lachlan Bishopc753c402020-09-10 14:57:05 +1000955 if (!data->emu_max_aai_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000956 break;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200957 if (!(data->emu_status[0] & SPI_SR_AAI)) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000958 if (writecnt < JEDEC_AAI_WORD_PROGRAM_OUTSIZE) {
959 msg_perr("Initial AAI WORD PROGRAM size too "
960 "short!\n");
961 return 1;
962 }
963 if (writecnt > JEDEC_AAI_WORD_PROGRAM_OUTSIZE) {
964 msg_perr("Initial AAI WORD PROGRAM size too "
965 "long!\n");
966 return 1;
967 }
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200968 data->emu_status[0] |= SPI_SR_AAI;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000969 aai_offs = writearr[1] << 16 | writearr[2] << 8 |
970 writearr[3];
971 /* Truncate to emu_chip_size. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000972 aai_offs %= data->emu_chip_size;
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200973 if (write_flash_data(data, aai_offs, 2, writearr + 4)) {
974 msg_perr("Failed to program flash!\n");
975 return 1;
976 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000977 aai_offs += 2;
978 } else {
979 if (writecnt < JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE) {
980 msg_perr("Continuation AAI WORD PROGRAM size "
981 "too short!\n");
982 return 1;
983 }
984 if (writecnt > JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE) {
985 msg_perr("Continuation AAI WORD PROGRAM size "
986 "too long!\n");
987 return 1;
988 }
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200989 if (write_flash_data(data, aai_offs, 2, writearr + 1)) {
990 msg_perr("Failed to program flash!\n");
991 return 1;
992 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000993 aai_offs += 2;
994 }
995 break;
996 case JEDEC_WRDI:
Lachlan Bishopc753c402020-09-10 14:57:05 +1000997 if (data->emu_max_aai_size)
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200998 data->emu_status[0] &= ~SPI_SR_AAI;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000999 break;
1000 case JEDEC_SE:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001001 if (!data->emu_jedec_se_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001002 break;
1003 if (writecnt != JEDEC_SE_OUTSIZE) {
1004 msg_perr("SECTOR ERASE 0x20 outsize invalid!\n");
1005 return 1;
1006 }
1007 if (readcnt != JEDEC_SE_INSIZE) {
1008 msg_perr("SECTOR ERASE 0x20 insize invalid!\n");
1009 return 1;
1010 }
1011 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
Lachlan Bishopc753c402020-09-10 14:57:05 +10001012 if (offs & (data->emu_jedec_se_size - 1))
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001013 msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs);
Lachlan Bishopc753c402020-09-10 14:57:05 +10001014 offs &= ~(data->emu_jedec_se_size - 1);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001015 if (erase_flash_data(data, offs, data->emu_jedec_se_size)) {
1016 msg_perr("Failed to erase flash!\n");
1017 return 1;
1018 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001019 break;
1020 case JEDEC_BE_52:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001021 if (!data->emu_jedec_be_52_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001022 break;
1023 if (writecnt != JEDEC_BE_52_OUTSIZE) {
1024 msg_perr("BLOCK ERASE 0x52 outsize invalid!\n");
1025 return 1;
1026 }
1027 if (readcnt != JEDEC_BE_52_INSIZE) {
1028 msg_perr("BLOCK ERASE 0x52 insize invalid!\n");
1029 return 1;
1030 }
1031 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
Lachlan Bishopc753c402020-09-10 14:57:05 +10001032 if (offs & (data->emu_jedec_be_52_size - 1))
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001033 msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs);
Lachlan Bishopc753c402020-09-10 14:57:05 +10001034 offs &= ~(data->emu_jedec_be_52_size - 1);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001035 if (erase_flash_data(data, offs, data->emu_jedec_be_52_size)) {
1036 msg_perr("Failed to erase flash!\n");
1037 return 1;
1038 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001039 break;
1040 case JEDEC_BE_D8:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001041 if (!data->emu_jedec_be_d8_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001042 break;
1043 if (writecnt != JEDEC_BE_D8_OUTSIZE) {
1044 msg_perr("BLOCK ERASE 0xd8 outsize invalid!\n");
1045 return 1;
1046 }
1047 if (readcnt != JEDEC_BE_D8_INSIZE) {
1048 msg_perr("BLOCK ERASE 0xd8 insize invalid!\n");
1049 return 1;
1050 }
1051 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
Lachlan Bishopc753c402020-09-10 14:57:05 +10001052 if (offs & (data->emu_jedec_be_d8_size - 1))
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001053 msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs);
Lachlan Bishopc753c402020-09-10 14:57:05 +10001054 offs &= ~(data->emu_jedec_be_d8_size - 1);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001055 if (erase_flash_data(data, offs, data->emu_jedec_be_d8_size)) {
1056 msg_perr("Failed to erase flash!\n");
1057 return 1;
1058 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001059 break;
1060 case JEDEC_CE_60:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001061 if (!data->emu_jedec_ce_60_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001062 break;
1063 if (writecnt != JEDEC_CE_60_OUTSIZE) {
1064 msg_perr("CHIP ERASE 0x60 outsize invalid!\n");
1065 return 1;
1066 }
1067 if (readcnt != JEDEC_CE_60_INSIZE) {
1068 msg_perr("CHIP ERASE 0x60 insize invalid!\n");
1069 return 1;
1070 }
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001071 /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001072 /* emu_jedec_ce_60_size is emu_chip_size. */
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001073 if (erase_flash_data(data, 0, data->emu_jedec_ce_60_size)) {
1074 msg_perr("Failed to erase flash!\n");
1075 return 1;
1076 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001077 break;
1078 case JEDEC_CE_C7:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001079 if (!data->emu_jedec_ce_c7_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001080 break;
1081 if (writecnt != JEDEC_CE_C7_OUTSIZE) {
1082 msg_perr("CHIP ERASE 0xc7 outsize invalid!\n");
1083 return 1;
1084 }
1085 if (readcnt != JEDEC_CE_C7_INSIZE) {
1086 msg_perr("CHIP ERASE 0xc7 insize invalid!\n");
1087 return 1;
1088 }
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001089 /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001090 /* emu_jedec_ce_c7_size is emu_chip_size. */
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001091 if (erase_flash_data(data, 0, data->emu_jedec_ce_c7_size)) {
1092 msg_perr("Failed to erase flash!\n");
1093 return 1;
1094 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001095 break;
Stefan Tauner0b9df972012-05-07 22:12:16 +00001096 case JEDEC_SFDP:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001097 if (data->emu_chip != EMULATE_MACRONIX_MX25L6436)
Stefan Tauner0b9df972012-05-07 22:12:16 +00001098 break;
1099 if (writecnt < 4)
1100 break;
1101 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
1102
1103 /* SFDP expects one dummy byte after the address. */
1104 if (writecnt == 4) {
1105 /* The dummy byte was not written, make sure it is read instead.
1106 * Shifting and shortening the read array does achieve this goal.
1107 */
1108 readarr++;
1109 readcnt--;
1110 } else {
1111 /* The response is shifted if more than 5 bytes are written, because SFDP data is
1112 * already shifted out by the chip while those superfluous bytes are written. */
1113 offs += writecnt - 5;
1114 }
1115
1116 /* The SFDP spec implies that the start address of an SFDP read may be truncated to fit in the
1117 * SFDP table address space, i.e. the start address may be wrapped around at SFDP table size.
1118 * This is a reasonable implementation choice in hardware because it saves a few gates. */
1119 if (offs >= sizeof(sfdp_table)) {
1120 msg_pdbg("Wrapping the start address around the SFDP table boundary (using 0x%x "
1121 "instead of 0x%x).\n", (unsigned int)(offs % sizeof(sfdp_table)), offs);
1122 offs %= sizeof(sfdp_table);
1123 }
1124 toread = min(sizeof(sfdp_table) - offs, readcnt);
1125 memcpy(readarr, sfdp_table + offs, toread);
1126 if (toread < readcnt)
1127 msg_pdbg("Crossing the SFDP table boundary in a single "
1128 "continuous chunk produces undefined results "
1129 "after that point.\n");
1130 break;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001131 default:
1132 /* No special response. */
1133 break;
1134 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001135 if (writearr[0] != JEDEC_WREN && writearr[0] != JEDEC_EWSR)
Sergii Dmytruk59151a42021-11-08 00:05:12 +02001136 data->emu_status[0] &= ~SPI_SR_WEL;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001137 return 0;
1138}
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001139
Edward O'Callaghan5eca4272020-04-12 17:27:53 +10001140static int dummy_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001141 unsigned int readcnt,
1142 const unsigned char *writearr,
1143 unsigned char *readarr)
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001144{
Nico Huber519be662018-12-23 20:03:35 +01001145 unsigned int i;
Lachlan Bishopc753c402020-09-10 14:57:05 +10001146 struct emu_data *emu_data = flash->mst->spi.data;
1147 if (!emu_data) {
1148 msg_perr("No data in flash context!\n");
1149 return 1;
1150 }
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001151
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001152 msg_pspew("%s:", __func__);
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001153
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001154 msg_pspew(" writing %u bytes:", writecnt);
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001155 for (i = 0; i < writecnt; i++)
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001156 msg_pspew(" 0x%02x", writearr[i]);
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001157
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001158 /* Response for unknown commands and missing chip is 0xff. */
1159 memset(readarr, 0xff, readcnt);
Lachlan Bishopc753c402020-09-10 14:57:05 +10001160 switch (emu_data->emu_chip) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001161 case EMULATE_ST_M25P10_RES:
1162 case EMULATE_SST_SST25VF040_REMS:
1163 case EMULATE_SST_SST25VF032B:
Stefan Tauner0b9df972012-05-07 22:12:16 +00001164 case EMULATE_MACRONIX_MX25L6436:
Nico Huberf9632d82019-01-20 11:23:49 +01001165 case EMULATE_WINBOND_W25Q128FV:
Nico Huber4203a472022-05-28 17:28:05 +02001166 case EMULATE_SPANSION_S25FL128L:
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001167 if (emulate_spi_chip_response(writecnt, readcnt, writearr,
Lachlan Bishopc753c402020-09-10 14:57:05 +10001168 readarr, emu_data)) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +00001169 msg_pdbg("Invalid command sent to flash chip!\n");
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001170 return 1;
1171 }
1172 break;
1173 default:
1174 break;
1175 }
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001176 msg_pspew(" reading %u bytes:", readcnt);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001177 for (i = 0; i < readcnt; i++)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001178 msg_pspew(" 0x%02x", readarr[i]);
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001179 msg_pspew("\n");
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001180 return 0;
1181}
Carl-Daniel Hailfinger1b0ba892010-06-20 10:58:32 +00001182
Mark Marshallf20b7be2014-05-09 21:16:21 +00001183static int dummy_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001184{
Edward O'Callaghanb1313422021-05-20 20:27:59 +10001185 const struct emu_data *const data = flash->mst->spi.data;
1186 return spi_write_chunked(flash, buf, start, len, data->spi_write_256_chunksize);
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001187}
Thomas Heijligencc853d82021-05-04 15:32:17 +02001188
1189const struct programmer_entry programmer_dummy = {
1190 .name = "dummy",
1191 .type = OTHER,
1192 /* FIXME */
1193 .devs.note = "Dummy device, does nothing and logs all accesses\n",
1194 .init = dummy_init,
1195 .map_flash_region = dummy_map,
1196 .unmap_flash_region = dummy_unmap,
1197 .delay = internal_delay,
1198};