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Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00004 * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +00005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00008 * the Free Software Foundation; version 2 of the License.
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +00009 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000014 */
15
Sergii Dmytruk59151a42021-11-08 00:05:12 +020016#include <assert.h>
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000017#include <string.h>
Felix Singer2fb53b12022-08-19 03:29:32 +020018#include <stdbool.h>
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000019#include <stdlib.h>
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +000020#include <stdio.h>
21#include <ctype.h>
Stefan Tauner5e695ab2012-05-06 17:03:40 +000022#include <errno.h>
Nico Huberab696292021-06-09 18:10:07 +020023#include <sys/types.h>
24#include <sys/stat.h>
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000025#include "flash.h"
Carl-Daniel Hailfinger1b0ba892010-06-20 10:58:32 +000026#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000028
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +000029#include "spi.h"
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +020030#include "writeprotect.h"
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +000031
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +000032enum emu_chip {
33 EMULATE_NONE,
34 EMULATE_ST_M25P10_RES,
35 EMULATE_SST_SST25VF040_REMS,
36 EMULATE_SST_SST25VF032B,
Stefan Tauner0b9df972012-05-07 22:12:16 +000037 EMULATE_MACRONIX_MX25L6436,
Nico Huberf9632d82019-01-20 11:23:49 +010038 EMULATE_WINBOND_W25Q128FV,
Nico Huber4203a472022-05-28 17:28:05 +020039 EMULATE_SPANSION_S25FL128L,
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +000040};
Stefan Tauner0b9df972012-05-07 22:12:16 +000041
Lachlan Bishopc753c402020-09-10 14:57:05 +100042struct emu_data {
43 enum emu_chip emu_chip;
44 char *emu_persistent_image;
45 unsigned int emu_chip_size;
Sergii Dmytruk59151a42021-11-08 00:05:12 +020046 /* Note: W25Q128FV doesn't change value of SR2 if it's not provided, but
47 * even its previous generations do, so don't forget to update
Nico Huberbbccdb22022-05-28 16:48:26 +020048 * WRSR code on enabling WRSR_EXT2 for more chips. */
49 bool emu_wrsr_ext2;
50 bool emu_wrsr_ext3;
Felix Singer2fb53b12022-08-19 03:29:32 +020051 bool emu_modified; /* is the image modified since reading it? */
Sergii Dmytruk59151a42021-11-08 00:05:12 +020052 uint8_t emu_status[3];
53 uint8_t emu_status_len; /* number of emulated status registers */
Lachlan Bishopc753c402020-09-10 14:57:05 +100054 unsigned int emu_max_byteprogram_size;
55 unsigned int emu_max_aai_size;
56 unsigned int emu_jedec_se_size;
57 unsigned int emu_jedec_be_52_size;
58 unsigned int emu_jedec_be_d8_size;
59 unsigned int emu_jedec_ce_60_size;
60 unsigned int emu_jedec_ce_c7_size;
61 unsigned char spi_blacklist[256];
62 unsigned char spi_ignorelist[256];
63 unsigned int spi_blacklist_size;
64 unsigned int spi_ignorelist_size;
Edward O'Callaghan94250222021-05-20 20:34:02 +100065
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +020066 bool hwwp; /* state of hardware write protection */
67 /* wp_start == wp_end when write-protection is disabled */
68 uint32_t wp_start;
69 uint32_t wp_end;
70
Edward O'Callaghanb1313422021-05-20 20:27:59 +100071 unsigned int spi_write_256_chunksize;
Edward O'Callaghan94250222021-05-20 20:34:02 +100072 uint8_t *flashchip_contents;
Lachlan Bishopc753c402020-09-10 14:57:05 +100073};
74
Stefan Tauner0b9df972012-05-07 22:12:16 +000075/* A legit complete SFDP table based on the MX25L6436E (rev. 1.8) datasheet. */
Stefan Tauner67d163d2013-01-15 17:37:48 +000076static const uint8_t sfdp_table[] = {
Stefan Tauner0b9df972012-05-07 22:12:16 +000077 0x53, 0x46, 0x44, 0x50, // @0x00: SFDP signature
78 0x00, 0x01, 0x01, 0xFF, // @0x04: revision 1.0, 2 headers
79 0x00, 0x00, 0x01, 0x09, // @0x08: JEDEC SFDP header rev. 1.0, 9 DW long
80 0x1C, 0x00, 0x00, 0xFF, // @0x0C: PTP0 = 0x1C (instead of 0x30)
81 0xC2, 0x00, 0x01, 0x04, // @0x10: Macronix header rev. 1.0, 4 DW long
82 0x48, 0x00, 0x00, 0xFF, // @0x14: PTP1 = 0x48 (instead of 0x60)
83 0xFF, 0xFF, 0xFF, 0xFF, // @0x18: hole.
84 0xE5, 0x20, 0xC9, 0xFF, // @0x1C: SFDP parameter table start
85 0xFF, 0xFF, 0xFF, 0x03, // @0x20
86 0x00, 0xFF, 0x08, 0x6B, // @0x24
87 0x08, 0x3B, 0x00, 0xFF, // @0x28
88 0xEE, 0xFF, 0xFF, 0xFF, // @0x2C
89 0xFF, 0xFF, 0x00, 0x00, // @0x30
90 0xFF, 0xFF, 0x00, 0xFF, // @0x34
91 0x0C, 0x20, 0x0F, 0x52, // @0x38
92 0x10, 0xD8, 0x00, 0xFF, // @0x3C: SFDP parameter table end
93 0xFF, 0xFF, 0xFF, 0xFF, // @0x40: hole.
94 0xFF, 0xFF, 0xFF, 0xFF, // @0x44: hole.
95 0x00, 0x36, 0x00, 0x27, // @0x48: Macronix parameter table start
96 0xF4, 0x4F, 0xFF, 0xFF, // @0x4C
97 0xD9, 0xC8, 0xFF, 0xFF, // @0x50
98 0xFF, 0xFF, 0xFF, 0xFF, // @0x54: Macronix parameter table end
99};
100
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000101
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000102
Edward O'Callaghan5eca4272020-04-12 17:27:53 +1000103static int dummy_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
Mark Marshallf20b7be2014-05-09 21:16:21 +0000104 const unsigned char *writearr, unsigned char *readarr);
105static int dummy_spi_write_256(struct flashctx *flash, const uint8_t *buf,
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000106 unsigned int start, unsigned int len);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000107static void dummy_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
108static void dummy_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr);
109static void dummy_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr);
110static void dummy_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
111static uint8_t dummy_chip_readb(const struct flashctx *flash, const chipaddr addr);
112static uint16_t dummy_chip_readw(const struct flashctx *flash, const chipaddr addr);
113static uint32_t dummy_chip_readl(const struct flashctx *flash, const chipaddr addr);
114static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
Nikolai Artemieve7a41e32022-11-28 17:40:56 +1100115static bool dummy_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000116
Nico Huber03f3a6d2021-05-11 17:53:34 +0200117static const struct spi_master spi_master_dummyflasher = {
Nico Huber1cf407b2017-11-10 20:18:23 +0100118 .features = SPI_MASTER_4BA,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000119 .max_data_read = MAX_DATA_READ_UNLIMITED,
120 .max_data_write = MAX_DATA_UNSPECIFIED,
121 .command = dummy_spi_send_command,
122 .multicommand = default_spi_send_multicommand,
123 .read = default_spi_read,
124 .write_256 = dummy_spi_write_256,
Aarya Chaumal0cea7532022-07-04 18:21:50 +0530125 .probe_opcode = dummy_spi_probe_opcode,
Michael Karcherb9dbe482011-05-11 17:07:07 +0000126};
David Hendricks8bb20212011-06-14 01:35:36 +0000127
Edward O'Callaghanf7504a92021-05-20 20:21:13 +1000128static const struct par_master par_master_dummyflasher = {
Thomas Heijligen43040f22022-06-23 14:38:35 +0200129 .chip_readb = dummy_chip_readb,
130 .chip_readw = dummy_chip_readw,
131 .chip_readl = dummy_chip_readl,
132 .chip_readn = dummy_chip_readn,
133 .chip_writeb = dummy_chip_writeb,
134 .chip_writew = dummy_chip_writew,
135 .chip_writel = dummy_chip_writel,
136 .chip_writen = dummy_chip_writen,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000137};
138
David Hendricks8bb20212011-06-14 01:35:36 +0000139static int dummy_shutdown(void *data)
140{
141 msg_pspew("%s\n", __func__);
Lachlan Bishopc753c402020-09-10 14:57:05 +1000142 struct emu_data *emu_data = (struct emu_data *)data;
143 if (emu_data->emu_chip != EMULATE_NONE) {
144 if (emu_data->emu_persistent_image && emu_data->emu_modified) {
145 msg_pdbg("Writing %s\n", emu_data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000146 write_buf_to_file(emu_data->flashchip_contents,
Lachlan Bishopc753c402020-09-10 14:57:05 +1000147 emu_data->emu_chip_size,
148 emu_data->emu_persistent_image);
David Hendricks8bb20212011-06-14 01:35:36 +0000149 }
Angel Pons02b9ae22021-05-25 12:46:43 +0200150 free(emu_data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000151 free(emu_data->flashchip_contents);
David Hendricks8bb20212011-06-14 01:35:36 +0000152 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000153 free(data);
David Hendricks8bb20212011-06-14 01:35:36 +0000154 return 0;
155}
156
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000157static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_supported)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000158{
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000159 char *bustext = NULL;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000160 char *tmp = NULL;
Nico Huber519be662018-12-23 20:03:35 +0100161 unsigned int i;
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000162 char *endptr;
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000163 char *status = NULL;
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000164
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000165 bustext = extract_programmer_param("bus");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000166 msg_pdbg("Requested buses are: %s\n", bustext ? bustext : "default");
167 if (!bustext)
168 bustext = strdup("parallel+lpc+fwh+spi");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000169 /* Convert the parameters to lowercase. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000170 tolower_string(bustext);
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000171
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000172 *dummy_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000173 if (strstr(bustext, "parallel")) {
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000174 *dummy_buses_supported |= BUS_PARALLEL;
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000175 msg_pdbg("Enabling support for %s flash.\n", "parallel");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000176 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000177 if (strstr(bustext, "lpc")) {
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000178 *dummy_buses_supported |= BUS_LPC;
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000179 msg_pdbg("Enabling support for %s flash.\n", "LPC");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000180 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000181 if (strstr(bustext, "fwh")) {
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000182 *dummy_buses_supported |= BUS_FWH;
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000183 msg_pdbg("Enabling support for %s flash.\n", "FWH");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000184 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000185 if (strstr(bustext, "spi")) {
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000186 *dummy_buses_supported |= BUS_SPI;
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000187 msg_pdbg("Enabling support for %s flash.\n", "SPI");
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000188 }
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000189 if (*dummy_buses_supported == BUS_NONE)
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000190 msg_pdbg("Support for all flash bus types disabled.\n");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000191 free(bustext);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000192
193 tmp = extract_programmer_param("spi_write_256_chunksize");
194 if (tmp) {
Edward O'Callaghanb1313422021-05-20 20:27:59 +1000195 data->spi_write_256_chunksize = strtoul(tmp, &endptr, 0);
196 if (*endptr != '\0' || data->spi_write_256_chunksize < 1) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000197 msg_perr("invalid spi_write_256_chunksize\n");
Edward O'Callaghanc785f882021-05-23 22:14:36 +1000198 free(tmp);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000199 return 1;
200 }
Edward O'Callaghanc785f882021-05-23 22:14:36 +1000201 free(tmp);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000202 }
203
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000204 tmp = extract_programmer_param("spi_blacklist");
205 if (tmp) {
206 i = strlen(tmp);
207 if (!strncmp(tmp, "0x", 2)) {
208 i -= 2;
209 memmove(tmp, tmp + 2, i + 1);
210 }
211 if ((i > 512) || (i % 2)) {
212 msg_perr("Invalid SPI command blacklist length\n");
213 free(tmp);
214 return 1;
215 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000216 data->spi_blacklist_size = i / 2;
217 for (i = 0; i < data->spi_blacklist_size * 2; i++) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000218 if (!isxdigit((unsigned char)tmp[i])) {
219 msg_perr("Invalid char \"%c\" in SPI command "
220 "blacklist\n", tmp[i]);
221 free(tmp);
222 return 1;
223 }
224 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000225 for (i = 0; i < data->spi_blacklist_size; i++) {
Carl-Daniel Hailfinger5b554712012-02-16 01:43:06 +0000226 unsigned int tmp2;
227 /* SCNx8 is apparently not supported by MSVC (and thus
228 * MinGW), so work around it with an extra variable
229 */
230 sscanf(tmp + i * 2, "%2x", &tmp2);
Lachlan Bishopc753c402020-09-10 14:57:05 +1000231 data->spi_blacklist[i] = (uint8_t)tmp2;
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000232 }
233 msg_pdbg("SPI blacklist is ");
Lachlan Bishopc753c402020-09-10 14:57:05 +1000234 for (i = 0; i < data->spi_blacklist_size; i++)
235 msg_pdbg("%02x ", data->spi_blacklist[i]);
236 msg_pdbg(", size %u\n", data->spi_blacklist_size);
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000237 }
238 free(tmp);
239
240 tmp = extract_programmer_param("spi_ignorelist");
241 if (tmp) {
242 i = strlen(tmp);
243 if (!strncmp(tmp, "0x", 2)) {
244 i -= 2;
245 memmove(tmp, tmp + 2, i + 1);
246 }
247 if ((i > 512) || (i % 2)) {
248 msg_perr("Invalid SPI command ignorelist length\n");
249 free(tmp);
250 return 1;
251 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000252 data->spi_ignorelist_size = i / 2;
253 for (i = 0; i < data->spi_ignorelist_size * 2; i++) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000254 if (!isxdigit((unsigned char)tmp[i])) {
255 msg_perr("Invalid char \"%c\" in SPI command "
256 "ignorelist\n", tmp[i]);
257 free(tmp);
258 return 1;
259 }
260 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000261 for (i = 0; i < data->spi_ignorelist_size; i++) {
Carl-Daniel Hailfinger5b554712012-02-16 01:43:06 +0000262 unsigned int tmp2;
263 /* SCNx8 is apparently not supported by MSVC (and thus
264 * MinGW), so work around it with an extra variable
265 */
266 sscanf(tmp + i * 2, "%2x", &tmp2);
Lachlan Bishopc753c402020-09-10 14:57:05 +1000267 data->spi_ignorelist[i] = (uint8_t)tmp2;
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000268 }
269 msg_pdbg("SPI ignorelist is ");
Lachlan Bishopc753c402020-09-10 14:57:05 +1000270 for (i = 0; i < data->spi_ignorelist_size; i++)
271 msg_pdbg("%02x ", data->spi_ignorelist[i]);
272 msg_pdbg(", size %u\n", data->spi_ignorelist_size);
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000273 }
274 free(tmp);
275
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200276 tmp = extract_programmer_param("hwwp");
277 if (tmp) {
278 if (!strcmp(tmp, "yes")) {
279 msg_pdbg("Emulated chip will have hardware WP enabled\n");
280 data->hwwp = true;
281 } else if (!strcmp(tmp, "no")) {
282 msg_pdbg("Emulated chip will have hardware WP disabled\n");
283 } else {
284 msg_perr("hwwp can be \"yes\" or \"no\"\n");
285 free(tmp);
286 return 1;
287 }
288 free(tmp);
289 }
290
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000291 tmp = extract_programmer_param("emulate");
292 if (!tmp) {
293 msg_pdbg("Not emulating any flash chip.\n");
294 /* Nothing else to do. */
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000295 return 0;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000296 }
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000297
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000298 if (!strcmp(tmp, "M25P10.RES")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000299 data->emu_chip = EMULATE_ST_M25P10_RES;
300 data->emu_chip_size = 128 * 1024;
301 data->emu_max_byteprogram_size = 128;
302 data->emu_max_aai_size = 0;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200303 data->emu_status_len = 1;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000304 data->emu_jedec_se_size = 0;
305 data->emu_jedec_be_52_size = 0;
306 data->emu_jedec_be_d8_size = 32 * 1024;
307 data->emu_jedec_ce_60_size = 0;
308 data->emu_jedec_ce_c7_size = data->emu_chip_size;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000309 msg_pdbg("Emulating ST M25P10.RES SPI flash chip (RES, page "
310 "write)\n");
311 }
312 if (!strcmp(tmp, "SST25VF040.REMS")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000313 data->emu_chip = EMULATE_SST_SST25VF040_REMS;
314 data->emu_chip_size = 512 * 1024;
315 data->emu_max_byteprogram_size = 1;
316 data->emu_max_aai_size = 0;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200317 data->emu_status_len = 1;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000318 data->emu_jedec_se_size = 4 * 1024;
319 data->emu_jedec_be_52_size = 32 * 1024;
320 data->emu_jedec_be_d8_size = 0;
321 data->emu_jedec_ce_60_size = data->emu_chip_size;
322 data->emu_jedec_ce_c7_size = 0;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000323 msg_pdbg("Emulating SST SST25VF040.REMS SPI flash chip (REMS, "
324 "byte write)\n");
325 }
326 if (!strcmp(tmp, "SST25VF032B")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000327 data->emu_chip = EMULATE_SST_SST25VF032B;
328 data->emu_chip_size = 4 * 1024 * 1024;
329 data->emu_max_byteprogram_size = 1;
330 data->emu_max_aai_size = 2;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200331 data->emu_status_len = 1;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000332 data->emu_jedec_se_size = 4 * 1024;
333 data->emu_jedec_be_52_size = 32 * 1024;
334 data->emu_jedec_be_d8_size = 64 * 1024;
335 data->emu_jedec_ce_60_size = data->emu_chip_size;
336 data->emu_jedec_ce_c7_size = data->emu_chip_size;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000337 msg_pdbg("Emulating SST SST25VF032B SPI flash chip (RDID, AAI "
338 "write)\n");
339 }
Stefan Tauner0b9df972012-05-07 22:12:16 +0000340 if (!strcmp(tmp, "MX25L6436")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000341 data->emu_chip = EMULATE_MACRONIX_MX25L6436;
342 data->emu_chip_size = 8 * 1024 * 1024;
343 data->emu_max_byteprogram_size = 256;
344 data->emu_max_aai_size = 0;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200345 data->emu_status_len = 1;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000346 data->emu_jedec_se_size = 4 * 1024;
347 data->emu_jedec_be_52_size = 32 * 1024;
348 data->emu_jedec_be_d8_size = 64 * 1024;
349 data->emu_jedec_ce_60_size = data->emu_chip_size;
350 data->emu_jedec_ce_c7_size = data->emu_chip_size;
Stefan Tauner0b9df972012-05-07 22:12:16 +0000351 msg_pdbg("Emulating Macronix MX25L6436 SPI flash chip (RDID, "
352 "SFDP)\n");
353 }
Nico Huberf9632d82019-01-20 11:23:49 +0100354 if (!strcmp(tmp, "W25Q128FV")) {
Lachlan Bishopc753c402020-09-10 14:57:05 +1000355 data->emu_chip = EMULATE_WINBOND_W25Q128FV;
Nico Huberbbccdb22022-05-28 16:48:26 +0200356 data->emu_wrsr_ext2 = true;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000357 data->emu_chip_size = 16 * 1024 * 1024;
358 data->emu_max_byteprogram_size = 256;
359 data->emu_max_aai_size = 0;
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200360 data->emu_status_len = 3;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000361 data->emu_jedec_se_size = 4 * 1024;
362 data->emu_jedec_be_52_size = 32 * 1024;
363 data->emu_jedec_be_d8_size = 64 * 1024;
364 data->emu_jedec_ce_60_size = data->emu_chip_size;
365 data->emu_jedec_ce_c7_size = data->emu_chip_size;
Nico Huberf9632d82019-01-20 11:23:49 +0100366 msg_pdbg("Emulating Winbond W25Q128FV SPI flash chip (RDID)\n");
367 }
Nico Huber4203a472022-05-28 17:28:05 +0200368 if (!strcmp(tmp, "S25FL128L")) {
369 data->emu_chip = EMULATE_SPANSION_S25FL128L;
370 data->emu_wrsr_ext2 = true;
371 data->emu_wrsr_ext3 = true;
372 data->emu_chip_size = 16 * 1024 * 1024;
373 data->emu_max_byteprogram_size = 256;
374 data->emu_max_aai_size = 0;
375 data->emu_status_len = 3;
376 data->emu_jedec_se_size = 4 * 1024;
377 data->emu_jedec_be_52_size = 32 * 1024;
378 data->emu_jedec_be_d8_size = 64 * 1024;
379 data->emu_jedec_ce_60_size = data->emu_chip_size;
380 data->emu_jedec_ce_c7_size = data->emu_chip_size;
381 msg_pdbg("Emulating Spansion S25FL128L SPI flash chip (RES, RDID, WP)\n");
382 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000383 if (data->emu_chip == EMULATE_NONE) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000384 msg_perr("Invalid chip specified for emulation: %s\n", tmp);
385 free(tmp);
386 return 1;
387 }
388 free(tmp);
David Hendricks8bb20212011-06-14 01:35:36 +0000389
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000390 status = extract_programmer_param("spi_status");
391 if (status) {
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200392 unsigned int emu_status;
393
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000394 errno = 0;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200395 emu_status = strtoul(status, &endptr, 0);
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000396 if (errno != 0 || status == endptr) {
Angel Ponsc2484642021-05-25 13:03:24 +0200397 free(status);
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000398 msg_perr("Error: initial status register specified, "
399 "but the value could not be converted.\n");
400 return 1;
401 }
Angel Ponsc2484642021-05-25 13:03:24 +0200402 free(status);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200403
404 data->emu_status[0] = emu_status;
405 data->emu_status[1] = emu_status >> 8;
406 data->emu_status[2] = emu_status >> 16;
407
408 if (data->emu_status_len == 3) {
409 msg_pdbg("Initial status registers:\n"
410 "\tSR1 is set to 0x%02x\n"
411 "\tSR2 is set to 0x%02x\n"
412 "\tSR3 is set to 0x%02x\n",
413 data->emu_status[0], data->emu_status[1], data->emu_status[2]);
414 } else if (data->emu_status_len == 2) {
415 msg_pdbg("Initial status registers:\n"
416 "\tSR1 is set to 0x%02x\n"
417 "\tSR2 is set to 0x%02x\n",
418 data->emu_status[0], data->emu_status[1]);
419 } else {
420 msg_pdbg("Initial status register is set to 0x%02x.\n",
421 data->emu_status[0]);
422 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000423 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000424
Angel Pons328898a2021-05-25 12:56:18 +0200425 data->flashchip_contents = malloc(data->emu_chip_size);
426 if (!data->flashchip_contents) {
427 msg_perr("Out of memory!\n");
428 return 1;
429 }
430
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000431
432 return 0;
433}
434
Thomas Heijligencc853d82021-05-04 15:32:17 +0200435static int dummy_init(void)
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000436{
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000437 struct stat image_stat;
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000438
Nico Huber4e9e99c2021-06-09 18:08:48 +0200439 struct emu_data *data = calloc(1, sizeof(*data));
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000440 if (!data) {
441 msg_perr("Out of memory!\n");
442 return 1;
443 }
444 data->emu_chip = EMULATE_NONE;
Edward O'Callaghanb1313422021-05-20 20:27:59 +1000445 data->spi_write_256_chunksize = 256;
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000446
447 msg_pspew("%s\n", __func__);
448
449 enum chipbustype dummy_buses_supported;
450 if (init_data(data, &dummy_buses_supported)) {
451 free(data);
452 return 1;
453 }
454
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000455 if (data->emu_chip == EMULATE_NONE) {
456 msg_pdbg("Not emulating any flash chip.\n");
457 /* Nothing else to do. */
458 goto dummy_init_out;
459 }
460
Lachlan Bishopc753c402020-09-10 14:57:05 +1000461 msg_pdbg("Filling fake flash chip with 0xff, size %i\n", data->emu_chip_size);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000462 memset(data->flashchip_contents, 0xff, data->emu_chip_size);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000463
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000464 /* Will be freed by shutdown function if necessary. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000465 data->emu_persistent_image = extract_programmer_param("image");
466 if (!data->emu_persistent_image) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000467 /* Nothing else to do. */
David Hendricks8bb20212011-06-14 01:35:36 +0000468 goto dummy_init_out;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000469 }
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000470 /* We will silently (in default verbosity) ignore the file if it does not exist (yet) or the size does
471 * not match the emulated chip. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000472 if (!stat(data->emu_persistent_image, &image_stat)) {
Stefan Tauner23e10b82016-01-23 16:16:49 +0000473 msg_pdbg("Found persistent image %s, %jd B ",
Lachlan Bishopc753c402020-09-10 14:57:05 +1000474 data->emu_persistent_image, (intmax_t)image_stat.st_size);
475 if ((uintmax_t)image_stat.st_size == data->emu_chip_size) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000476 msg_pdbg("matches.\n");
Lachlan Bishopc753c402020-09-10 14:57:05 +1000477 msg_pdbg("Reading %s\n", data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000478 if (read_buf_from_file(data->flashchip_contents, data->emu_chip_size,
Lachlan Bishopc753c402020-09-10 14:57:05 +1000479 data->emu_persistent_image)) {
480 msg_perr("Unable to read %s\n", data->emu_persistent_image);
Angel Pons02b9ae22021-05-25 12:46:43 +0200481 free(data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000482 free(data->flashchip_contents);
Anastasia Klimchuk3c55c792021-05-31 09:42:36 +1000483 free(data);
Jacob Garberca598da2019-08-12 10:44:17 -0600484 return 1;
485 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000486 } else {
487 msg_pdbg("doesn't match.\n");
488 }
489 }
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000490
David Hendricks8bb20212011-06-14 01:35:36 +0000491dummy_init_out:
Lachlan Bishopc753c402020-09-10 14:57:05 +1000492 if (register_shutdown(dummy_shutdown, data)) {
Angel Pons02b9ae22021-05-25 12:46:43 +0200493 free(data->emu_persistent_image);
Edward O'Callaghan94250222021-05-20 20:34:02 +1000494 free(data->flashchip_contents);
Lachlan Bishopc753c402020-09-10 14:57:05 +1000495 free(data);
David Hendricks8bb20212011-06-14 01:35:36 +0000496 return 1;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000497 }
Edward O'Callaghan3fa321d2021-05-17 20:01:27 +1000498 if (dummy_buses_supported & BUS_NONSPI)
Edward O'Callaghanf7504a92021-05-20 20:21:13 +1000499 register_par_master(&par_master_dummyflasher,
Anastasia Klimchukb91a2032021-05-21 09:40:58 +1000500 dummy_buses_supported & BUS_NONSPI,
Anastasia Klimchuka7389152021-05-21 09:45:53 +1000501 data);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000502 if (dummy_buses_supported & BUS_SPI)
Nico Huber03f3a6d2021-05-11 17:53:34 +0200503 register_spi_master(&spi_master_dummyflasher, data);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000504
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000505 return 0;
506}
507
Thomas Heijligencc853d82021-05-04 15:32:17 +0200508static void *dummy_map(const char *descr, uintptr_t phys_addr, size_t len)
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000509{
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000510 msg_pspew("%s: Mapping %s, 0x%zx bytes at 0x%0*" PRIxPTR "\n",
Stefan Tauner0554ca52013-07-25 22:54:25 +0000511 __func__, descr, len, PRIxPTR_WIDTH, phys_addr);
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000512 return (void *)phys_addr;
513}
514
Thomas Heijligencc853d82021-05-04 15:32:17 +0200515static void dummy_unmap(void *virt_addr, size_t len)
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000516{
Stefan Tauner0554ca52013-07-25 22:54:25 +0000517 msg_pspew("%s: Unmapping 0x%zx bytes at %p\n", __func__, len, virt_addr);
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000518}
519
Mark Marshallf20b7be2014-05-09 21:16:21 +0000520static void dummy_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000521{
Stefan Taunerc2333752013-07-13 23:31:37 +0000522 msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%02x\n", __func__, addr, val);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000523}
524
Mark Marshallf20b7be2014-05-09 21:16:21 +0000525static void dummy_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000526{
Stefan Taunerc2333752013-07-13 23:31:37 +0000527 msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%04x\n", __func__, addr, val);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000528}
529
Mark Marshallf20b7be2014-05-09 21:16:21 +0000530static void dummy_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000531{
Stefan Taunerc2333752013-07-13 23:31:37 +0000532 msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%08x\n", __func__, addr, val);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000533}
534
Mark Marshallf20b7be2014-05-09 21:16:21 +0000535static void dummy_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len)
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000536{
537 size_t i;
Stefan Tauner0554ca52013-07-25 22:54:25 +0000538 msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, writing data (hex):", __func__, addr, len);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000539 for (i = 0; i < len; i++) {
540 if ((i % 16) == 0)
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +0000541 msg_pspew("\n");
542 msg_pspew("%02x ", buf[i]);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000543 }
544}
545
Mark Marshallf20b7be2014-05-09 21:16:21 +0000546static uint8_t dummy_chip_readb(const struct flashctx *flash, const chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000547{
Stefan Taunerc2333752013-07-13 23:31:37 +0000548 msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xff\n", __func__, addr);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000549 return 0xff;
550}
551
Mark Marshallf20b7be2014-05-09 21:16:21 +0000552static uint16_t dummy_chip_readw(const struct flashctx *flash, const chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000553{
Stefan Taunerc2333752013-07-13 23:31:37 +0000554 msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xffff\n", __func__, addr);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000555 return 0xffff;
556}
557
Mark Marshallf20b7be2014-05-09 21:16:21 +0000558static uint32_t dummy_chip_readl(const struct flashctx *flash, const chipaddr addr)
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000559{
Stefan Taunerc2333752013-07-13 23:31:37 +0000560 msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xffffffff\n", __func__, addr);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000561 return 0xffffffff;
562}
563
Mark Marshallf20b7be2014-05-09 21:16:21 +0000564static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len)
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000565{
Stefan Tauner0554ca52013-07-25 22:54:25 +0000566 msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, returning array of 0xff\n", __func__, addr, len);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000567 memset(buf, 0xff, len);
568 return;
569}
570
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200571static uint8_t get_reg_ro_bit_mask(const struct emu_data *data, enum flash_reg reg)
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200572{
573 /* Whoever adds a new register must not forget to update this function
574 or at least shouldn't use it incorrectly. */
575 assert(reg == STATUS1 || reg == STATUS2 || reg == STATUS3);
576
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200577 uint8_t ro_bits = reg == STATUS1 ? SPI_SR_WIP : 0;
578
579 if (data->emu_chip == EMULATE_WINBOND_W25Q128FV) {
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200580 const bool srp0 = (data->emu_status[0] >> 7);
581 const bool srp1 = (data->emu_status[1] & 1);
582
583 const bool wp_active = (srp1 || (srp0 && data->hwwp));
584
585 if (wp_active) {
586 ro_bits = 0xff;
587 } else if (reg == STATUS2) {
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200588 /* SUS (bit_7) and (R) (bit_2). */
589 ro_bits = 0x84;
590 /* Once any of the lock bits (LB[1..3]) are set, they
591 can't be unset. */
592 ro_bits |= data->emu_status[1] & (1 << 3);
593 ro_bits |= data->emu_status[1] & (1 << 4);
594 ro_bits |= data->emu_status[1] & (1 << 5);
595 } else if (reg == STATUS3) {
596 /* Four reserved bits. */
597 ro_bits = 0x1b;
598 }
599 }
600
Nico Huber4203a472022-05-28 17:28:05 +0200601 if (data->emu_chip == EMULATE_SPANSION_S25FL128L) {
602 const bool srp0 = (data->emu_status[0] >> 7);
603 const bool srp1 = (data->emu_status[1] & 1);
604
605 const bool wp_active = (srp1 || (srp0 && data->hwwp));
606
607 if (wp_active) {
608 ro_bits = 0xff;
609 } else if (reg == STATUS2) {
610 /* SUS (bit_7) */
611 ro_bits = 0x80;
612 /* Once any of the lock bits (LB[0..3]) are set, they
613 can't be unset. */
614 ro_bits |= data->emu_status[1] & (1 << 2);
615 ro_bits |= data->emu_status[1] & (1 << 3);
616 ro_bits |= data->emu_status[1] & (1 << 4);
617 ro_bits |= data->emu_status[1] & (1 << 5);
618 } else if (reg == STATUS3) {
619 /* Two reserved bits. */
620 ro_bits = 0x11;
621 }
622 }
623
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200624 return ro_bits;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200625}
626
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200627static void update_write_protection(struct emu_data *data)
628{
Nico Huber4203a472022-05-28 17:28:05 +0200629 if (data->emu_chip != EMULATE_WINBOND_W25Q128FV &&
630 data->emu_chip != EMULATE_SPANSION_S25FL128L)
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200631 return;
632
633 const struct wp_bits bits = {
634 .srp = data->emu_status[0] >> 7,
635 .srl = data->emu_status[1] & 1,
636
637 .bp_bit_count = 3,
638 .bp =
639 {
640 (data->emu_status[0] >> 2) & 1,
641 (data->emu_status[0] >> 3) & 1,
642 (data->emu_status[0] >> 4) & 1
643 },
644
645 .tb_bit_present = true,
646 .tb = (data->emu_status[0] >> 5) & 1,
647
648 .sec_bit_present = true,
649 .sec = (data->emu_status[0] >> 6) & 1,
650
651 .cmp_bit_present = true,
652 .cmp = (data->emu_status[1] >> 6) & 1,
653 };
654
655 size_t start;
656 size_t len;
657 decode_range_spi25(&start, &len, &bits, data->emu_chip_size);
658
659 data->wp_start = start;
660 data->wp_end = start + len;
661}
662
663/* Checks whether range intersects a write-protected area of the flash if one is
664 * defined. */
665static bool is_write_protected(const struct emu_data *data, uint32_t start, uint32_t len)
666{
667 if (len == 0)
668 return false;
669
670 const uint32_t last = start + len - 1;
671 return (start < data->wp_end && last >= data->wp_start);
672}
673
674/* Returns non-zero on error. */
675static int write_flash_data(struct emu_data *data, uint32_t start, uint32_t len, const uint8_t *buf)
676{
677 if (is_write_protected(data, start, len)) {
678 msg_perr("At least part of the write range is write protected!\n");
679 return 1;
680 }
681
682 memcpy(data->flashchip_contents + start, buf, len);
Felix Singer2fb53b12022-08-19 03:29:32 +0200683 data->emu_modified = true;
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200684 return 0;
685}
686
687/* Returns non-zero on error. */
688static int erase_flash_data(struct emu_data *data, uint32_t start, uint32_t len)
689{
690 if (is_write_protected(data, start, len)) {
691 msg_perr("At least part of the erase range is write protected!\n");
692 return 1;
693 }
694
695 memset(data->flashchip_contents + start, 0xff, len);
Felix Singer2fb53b12022-08-19 03:29:32 +0200696 data->emu_modified = true;
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200697 return 0;
698}
699
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000700static int emulate_spi_chip_response(unsigned int writecnt,
701 unsigned int readcnt,
702 const unsigned char *writearr,
Lachlan Bishopc753c402020-09-10 14:57:05 +1000703 unsigned char *readarr,
704 struct emu_data *data)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000705{
Stefan Tauner0b9df972012-05-07 22:12:16 +0000706 unsigned int offs, i, toread;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200707 uint8_t ro_bits;
Nico Huberbbccdb22022-05-28 16:48:26 +0200708 bool wrsr_ext2, wrsr_ext3;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000709 static int unsigned aai_offs;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000710 const unsigned char sst25vf040_rems_response[2] = {0xbf, 0x44};
711 const unsigned char sst25vf032b_rems_response[2] = {0xbf, 0x4a};
712 const unsigned char mx25l6436_rems_response[2] = {0xc2, 0x16};
Nico Huberf9632d82019-01-20 11:23:49 +0100713 const unsigned char w25q128fv_rems_response[2] = {0xef, 0x17};
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000714
715 if (writecnt == 0) {
716 msg_perr("No command sent to the chip!\n");
717 return 1;
718 }
Paul Menzelac427b22012-02-16 21:07:07 +0000719 /* spi_blacklist has precedence over spi_ignorelist. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000720 for (i = 0; i < data->spi_blacklist_size; i++) {
721 if (writearr[0] == data->spi_blacklist[i]) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000722 msg_pdbg("Refusing blacklisted SPI command 0x%02x\n",
Lachlan Bishopc753c402020-09-10 14:57:05 +1000723 data->spi_blacklist[i]);
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000724 return SPI_INVALID_OPCODE;
725 }
726 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000727 for (i = 0; i < data->spi_ignorelist_size; i++) {
728 if (writearr[0] == data->spi_ignorelist[i]) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000729 msg_cdbg("Ignoring ignorelisted SPI command 0x%02x\n",
Lachlan Bishopc753c402020-09-10 14:57:05 +1000730 data->spi_ignorelist[i]);
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +0000731 /* Return success because the command does not fail,
732 * it is simply ignored.
733 */
734 return 0;
735 }
736 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000737
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200738 if (data->emu_max_aai_size && (data->emu_status[0] & SPI_SR_AAI)) {
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000739 if (writearr[0] != JEDEC_AAI_WORD_PROGRAM &&
740 writearr[0] != JEDEC_WRDI &&
741 writearr[0] != JEDEC_RDSR) {
742 msg_perr("Forbidden opcode (0x%02x) attempted during "
743 "AAI sequence!\n", writearr[0]);
744 return 0;
745 }
746 }
747
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000748 switch (writearr[0]) {
749 case JEDEC_RES:
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000750 if (writecnt < JEDEC_RES_OUTSIZE)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000751 break;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000752 /* offs calculation is only needed for SST chips which treat RES like REMS. */
753 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
754 offs += writecnt - JEDEC_REMS_OUTSIZE;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000755 switch (data->emu_chip) {
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000756 case EMULATE_ST_M25P10_RES:
757 if (readcnt > 0)
758 memset(readarr, 0x10, readcnt);
759 break;
760 case EMULATE_SST_SST25VF040_REMS:
761 for (i = 0; i < readcnt; i++)
762 readarr[i] = sst25vf040_rems_response[(offs + i) % 2];
763 break;
764 case EMULATE_SST_SST25VF032B:
765 for (i = 0; i < readcnt; i++)
766 readarr[i] = sst25vf032b_rems_response[(offs + i) % 2];
767 break;
768 case EMULATE_MACRONIX_MX25L6436:
769 if (readcnt > 0)
770 memset(readarr, 0x16, readcnt);
771 break;
Nico Huberf9632d82019-01-20 11:23:49 +0100772 case EMULATE_WINBOND_W25Q128FV:
773 if (readcnt > 0)
774 memset(readarr, 0x17, readcnt);
775 break;
Nico Huber4203a472022-05-28 17:28:05 +0200776 case EMULATE_SPANSION_S25FL128L:
777 if (readcnt > 0)
778 readarr[0] = 0x60;
779 if (readcnt > 1)
780 readarr[1] = 0x18;
781 break;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000782 default: /* ignore */
783 break;
784 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000785 break;
786 case JEDEC_REMS:
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000787 /* REMS response has wraparound and uses an address parameter. */
788 if (writecnt < JEDEC_REMS_OUTSIZE)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000789 break;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000790 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
791 offs += writecnt - JEDEC_REMS_OUTSIZE;
Lachlan Bishopc753c402020-09-10 14:57:05 +1000792 switch (data->emu_chip) {
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000793 case EMULATE_SST_SST25VF040_REMS:
794 for (i = 0; i < readcnt; i++)
795 readarr[i] = sst25vf040_rems_response[(offs + i) % 2];
796 break;
797 case EMULATE_SST_SST25VF032B:
798 for (i = 0; i < readcnt; i++)
799 readarr[i] = sst25vf032b_rems_response[(offs + i) % 2];
800 break;
801 case EMULATE_MACRONIX_MX25L6436:
802 for (i = 0; i < readcnt; i++)
803 readarr[i] = mx25l6436_rems_response[(offs + i) % 2];
804 break;
Nico Huberf9632d82019-01-20 11:23:49 +0100805 case EMULATE_WINBOND_W25Q128FV:
806 for (i = 0; i < readcnt; i++)
807 readarr[i] = w25q128fv_rems_response[(offs + i) % 2];
808 break;
Carl-Daniel Hailfingeraf2cac02012-08-30 21:41:00 +0000809 default: /* ignore */
810 break;
811 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000812 break;
813 case JEDEC_RDID:
Lachlan Bishopc753c402020-09-10 14:57:05 +1000814 switch (data->emu_chip) {
Stefan Tauner0b9df972012-05-07 22:12:16 +0000815 case EMULATE_SST_SST25VF032B:
816 if (readcnt > 0)
817 readarr[0] = 0xbf;
818 if (readcnt > 1)
819 readarr[1] = 0x25;
820 if (readcnt > 2)
821 readarr[2] = 0x4a;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000822 break;
Stefan Tauner0b9df972012-05-07 22:12:16 +0000823 case EMULATE_MACRONIX_MX25L6436:
824 if (readcnt > 0)
825 readarr[0] = 0xc2;
826 if (readcnt > 1)
827 readarr[1] = 0x20;
828 if (readcnt > 2)
829 readarr[2] = 0x17;
830 break;
Nico Huberf9632d82019-01-20 11:23:49 +0100831 case EMULATE_WINBOND_W25Q128FV:
832 if (readcnt > 0)
833 readarr[0] = 0xef;
834 if (readcnt > 1)
835 readarr[1] = 0x40;
836 if (readcnt > 2)
837 readarr[2] = 0x18;
838 break;
Nico Huber4203a472022-05-28 17:28:05 +0200839 case EMULATE_SPANSION_S25FL128L:
840 if (readcnt > 0)
841 readarr[0] = 0x01;
842 if (readcnt > 1)
843 readarr[1] = 0x60;
844 if (readcnt > 2)
845 readarr[2] = 0x18;
846 break;
Stefan Tauner0b9df972012-05-07 22:12:16 +0000847 default: /* ignore */
848 break;
849 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000850 break;
Stefan Tauner0b9df972012-05-07 22:12:16 +0000851 case JEDEC_RDSR:
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200852 memset(readarr, data->emu_status[0], readcnt);
853 break;
854 case JEDEC_RDSR2:
855 if (data->emu_status_len >= 2)
856 memset(readarr, data->emu_status[1], readcnt);
857 break;
858 case JEDEC_RDSR3:
859 if (data->emu_status_len >= 3)
860 memset(readarr, data->emu_status[2], readcnt);
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000861 break;
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000862 /* FIXME: this should be chip-specific. */
863 case JEDEC_EWSR:
864 case JEDEC_WREN:
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200865 data->emu_status[0] |= SPI_SR_WEL;
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000866 break;
867 case JEDEC_WRSR:
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200868 if (!(data->emu_status[0] & SPI_SR_WEL)) {
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000869 msg_perr("WRSR attempted, but WEL is 0!\n");
870 break;
871 }
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200872
Nico Huberbbccdb22022-05-28 16:48:26 +0200873 wrsr_ext2 = (writecnt == 3 && data->emu_wrsr_ext2);
874 wrsr_ext3 = (writecnt == 4 && data->emu_wrsr_ext3);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200875
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000876 /* FIXME: add some reasonable simulation of the busy flag */
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200877
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200878 ro_bits = get_reg_ro_bit_mask(data, STATUS1);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200879 data->emu_status[0] &= ro_bits;
880 data->emu_status[0] |= writearr[1] & ~ro_bits;
Nico Huberbbccdb22022-05-28 16:48:26 +0200881 if (wrsr_ext2 || wrsr_ext3) {
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200882 ro_bits = get_reg_ro_bit_mask(data, STATUS2);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200883 data->emu_status[1] &= ro_bits;
884 data->emu_status[1] |= writearr[2] & ~ro_bits;
885 }
Nico Huberbbccdb22022-05-28 16:48:26 +0200886 if (wrsr_ext3) {
887 ro_bits = get_reg_ro_bit_mask(data, STATUS3);
888 data->emu_status[2] &= ro_bits;
889 data->emu_status[2] |= writearr[3] & ~ro_bits;
890 }
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200891
Nico Huberbbccdb22022-05-28 16:48:26 +0200892 if (wrsr_ext3)
893 msg_pdbg2("WRSR wrote 0x%02x%02x%02x.\n", data->emu_status[2], data->emu_status[1], data->emu_status[0]);
894 else if (wrsr_ext2)
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200895 msg_pdbg2("WRSR wrote 0x%02x%02x.\n", data->emu_status[1], data->emu_status[0]);
896 else
897 msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status[0]);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200898
899 update_write_protection(data);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200900 break;
901 case JEDEC_WRSR2:
902 if (data->emu_status_len < 2)
903 break;
904 if (!(data->emu_status[0] & SPI_SR_WEL)) {
905 msg_perr("WRSR2 attempted, but WEL is 0!\n");
906 break;
907 }
908
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200909 ro_bits = get_reg_ro_bit_mask(data, STATUS2);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200910 data->emu_status[1] &= ro_bits;
911 data->emu_status[1] |= (writearr[1] & ~ro_bits);
912
913 msg_pdbg2("WRSR2 wrote 0x%02x.\n", data->emu_status[1]);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200914
915 update_write_protection(data);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200916 break;
917 case JEDEC_WRSR3:
918 if (data->emu_status_len < 3)
919 break;
920 if (!(data->emu_status[0] & SPI_SR_WEL)) {
921 msg_perr("WRSR3 attempted, but WEL is 0!\n");
922 break;
923 }
924
Sergii Dmytruk27835ea2021-11-08 00:06:33 +0200925 ro_bits = get_reg_ro_bit_mask(data, STATUS3);
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200926 data->emu_status[2] &= ro_bits;
927 data->emu_status[2] |= (writearr[1] & ~ro_bits);
928
929 msg_pdbg2("WRSR3 wrote 0x%02x.\n", data->emu_status[2]);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000930 break;
931 case JEDEC_READ:
932 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
933 /* Truncate to emu_chip_size. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000934 offs %= data->emu_chip_size;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000935 if (readcnt > 0)
Edward O'Callaghan94250222021-05-20 20:34:02 +1000936 memcpy(readarr, data->flashchip_contents + offs, readcnt);
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000937 break;
938 case JEDEC_BYTE_PROGRAM:
939 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
940 /* Truncate to emu_chip_size. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000941 offs %= data->emu_chip_size;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000942 if (writecnt < 5) {
943 msg_perr("BYTE PROGRAM size too short!\n");
944 return 1;
945 }
Lachlan Bishopc753c402020-09-10 14:57:05 +1000946 if (writecnt - 4 > data->emu_max_byteprogram_size) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000947 msg_perr("Max BYTE PROGRAM size exceeded!\n");
948 return 1;
949 }
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200950 if (write_flash_data(data, offs, writecnt - 4, writearr + 4)) {
951 msg_perr("Failed to program flash!\n");
952 return 1;
953 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000954 break;
955 case JEDEC_AAI_WORD_PROGRAM:
Lachlan Bishopc753c402020-09-10 14:57:05 +1000956 if (!data->emu_max_aai_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000957 break;
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200958 if (!(data->emu_status[0] & SPI_SR_AAI)) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000959 if (writecnt < JEDEC_AAI_WORD_PROGRAM_OUTSIZE) {
960 msg_perr("Initial AAI WORD PROGRAM size too "
961 "short!\n");
962 return 1;
963 }
964 if (writecnt > JEDEC_AAI_WORD_PROGRAM_OUTSIZE) {
965 msg_perr("Initial AAI WORD PROGRAM size too "
966 "long!\n");
967 return 1;
968 }
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200969 data->emu_status[0] |= SPI_SR_AAI;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000970 aai_offs = writearr[1] << 16 | writearr[2] << 8 |
971 writearr[3];
972 /* Truncate to emu_chip_size. */
Lachlan Bishopc753c402020-09-10 14:57:05 +1000973 aai_offs %= data->emu_chip_size;
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200974 if (write_flash_data(data, aai_offs, 2, writearr + 4)) {
975 msg_perr("Failed to program flash!\n");
976 return 1;
977 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000978 aai_offs += 2;
979 } else {
980 if (writecnt < JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE) {
981 msg_perr("Continuation AAI WORD PROGRAM size "
982 "too short!\n");
983 return 1;
984 }
985 if (writecnt > JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE) {
986 msg_perr("Continuation AAI WORD PROGRAM size "
987 "too long!\n");
988 return 1;
989 }
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +0200990 if (write_flash_data(data, aai_offs, 2, writearr + 1)) {
991 msg_perr("Failed to program flash!\n");
992 return 1;
993 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +0000994 aai_offs += 2;
995 }
996 break;
997 case JEDEC_WRDI:
Lachlan Bishopc753c402020-09-10 14:57:05 +1000998 if (data->emu_max_aai_size)
Sergii Dmytruk59151a42021-11-08 00:05:12 +0200999 data->emu_status[0] &= ~SPI_SR_AAI;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001000 break;
1001 case JEDEC_SE:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001002 if (!data->emu_jedec_se_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001003 break;
1004 if (writecnt != JEDEC_SE_OUTSIZE) {
1005 msg_perr("SECTOR ERASE 0x20 outsize invalid!\n");
1006 return 1;
1007 }
1008 if (readcnt != JEDEC_SE_INSIZE) {
1009 msg_perr("SECTOR ERASE 0x20 insize invalid!\n");
1010 return 1;
1011 }
1012 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
Lachlan Bishopc753c402020-09-10 14:57:05 +10001013 if (offs & (data->emu_jedec_se_size - 1))
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001014 msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs);
Lachlan Bishopc753c402020-09-10 14:57:05 +10001015 offs &= ~(data->emu_jedec_se_size - 1);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001016 if (erase_flash_data(data, offs, data->emu_jedec_se_size)) {
1017 msg_perr("Failed to erase flash!\n");
1018 return 1;
1019 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001020 break;
1021 case JEDEC_BE_52:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001022 if (!data->emu_jedec_be_52_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001023 break;
1024 if (writecnt != JEDEC_BE_52_OUTSIZE) {
1025 msg_perr("BLOCK ERASE 0x52 outsize invalid!\n");
1026 return 1;
1027 }
1028 if (readcnt != JEDEC_BE_52_INSIZE) {
1029 msg_perr("BLOCK ERASE 0x52 insize invalid!\n");
1030 return 1;
1031 }
1032 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
Lachlan Bishopc753c402020-09-10 14:57:05 +10001033 if (offs & (data->emu_jedec_be_52_size - 1))
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001034 msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs);
Lachlan Bishopc753c402020-09-10 14:57:05 +10001035 offs &= ~(data->emu_jedec_be_52_size - 1);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001036 if (erase_flash_data(data, offs, data->emu_jedec_be_52_size)) {
1037 msg_perr("Failed to erase flash!\n");
1038 return 1;
1039 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001040 break;
1041 case JEDEC_BE_D8:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001042 if (!data->emu_jedec_be_d8_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001043 break;
1044 if (writecnt != JEDEC_BE_D8_OUTSIZE) {
1045 msg_perr("BLOCK ERASE 0xd8 outsize invalid!\n");
1046 return 1;
1047 }
1048 if (readcnt != JEDEC_BE_D8_INSIZE) {
1049 msg_perr("BLOCK ERASE 0xd8 insize invalid!\n");
1050 return 1;
1051 }
1052 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
Lachlan Bishopc753c402020-09-10 14:57:05 +10001053 if (offs & (data->emu_jedec_be_d8_size - 1))
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001054 msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs);
Lachlan Bishopc753c402020-09-10 14:57:05 +10001055 offs &= ~(data->emu_jedec_be_d8_size - 1);
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001056 if (erase_flash_data(data, offs, data->emu_jedec_be_d8_size)) {
1057 msg_perr("Failed to erase flash!\n");
1058 return 1;
1059 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001060 break;
1061 case JEDEC_CE_60:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001062 if (!data->emu_jedec_ce_60_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001063 break;
1064 if (writecnt != JEDEC_CE_60_OUTSIZE) {
1065 msg_perr("CHIP ERASE 0x60 outsize invalid!\n");
1066 return 1;
1067 }
1068 if (readcnt != JEDEC_CE_60_INSIZE) {
1069 msg_perr("CHIP ERASE 0x60 insize invalid!\n");
1070 return 1;
1071 }
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001072 /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001073 /* emu_jedec_ce_60_size is emu_chip_size. */
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001074 if (erase_flash_data(data, 0, data->emu_jedec_ce_60_size)) {
1075 msg_perr("Failed to erase flash!\n");
1076 return 1;
1077 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001078 break;
1079 case JEDEC_CE_C7:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001080 if (!data->emu_jedec_ce_c7_size)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001081 break;
1082 if (writecnt != JEDEC_CE_C7_OUTSIZE) {
1083 msg_perr("CHIP ERASE 0xc7 outsize invalid!\n");
1084 return 1;
1085 }
1086 if (readcnt != JEDEC_CE_C7_INSIZE) {
1087 msg_perr("CHIP ERASE 0xc7 insize invalid!\n");
1088 return 1;
1089 }
Carl-Daniel Hailfinger146b77d2011-02-04 22:52:04 +00001090 /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001091 /* emu_jedec_ce_c7_size is emu_chip_size. */
Sergii Dmytruk2fc70dc2021-11-08 01:38:52 +02001092 if (erase_flash_data(data, 0, data->emu_jedec_ce_c7_size)) {
1093 msg_perr("Failed to erase flash!\n");
1094 return 1;
1095 }
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001096 break;
Stefan Tauner0b9df972012-05-07 22:12:16 +00001097 case JEDEC_SFDP:
Lachlan Bishopc753c402020-09-10 14:57:05 +10001098 if (data->emu_chip != EMULATE_MACRONIX_MX25L6436)
Stefan Tauner0b9df972012-05-07 22:12:16 +00001099 break;
1100 if (writecnt < 4)
1101 break;
1102 offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
1103
1104 /* SFDP expects one dummy byte after the address. */
1105 if (writecnt == 4) {
1106 /* The dummy byte was not written, make sure it is read instead.
1107 * Shifting and shortening the read array does achieve this goal.
1108 */
1109 readarr++;
1110 readcnt--;
1111 } else {
1112 /* The response is shifted if more than 5 bytes are written, because SFDP data is
1113 * already shifted out by the chip while those superfluous bytes are written. */
1114 offs += writecnt - 5;
1115 }
1116
1117 /* The SFDP spec implies that the start address of an SFDP read may be truncated to fit in the
1118 * SFDP table address space, i.e. the start address may be wrapped around at SFDP table size.
1119 * This is a reasonable implementation choice in hardware because it saves a few gates. */
1120 if (offs >= sizeof(sfdp_table)) {
1121 msg_pdbg("Wrapping the start address around the SFDP table boundary (using 0x%x "
1122 "instead of 0x%x).\n", (unsigned int)(offs % sizeof(sfdp_table)), offs);
1123 offs %= sizeof(sfdp_table);
1124 }
1125 toread = min(sizeof(sfdp_table) - offs, readcnt);
1126 memcpy(readarr, sfdp_table + offs, toread);
1127 if (toread < readcnt)
1128 msg_pdbg("Crossing the SFDP table boundary in a single "
1129 "continuous chunk produces undefined results "
1130 "after that point.\n");
1131 break;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001132 default:
1133 /* No special response. */
1134 break;
1135 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001136 if (writearr[0] != JEDEC_WREN && writearr[0] != JEDEC_EWSR)
Sergii Dmytruk59151a42021-11-08 00:05:12 +02001137 data->emu_status[0] &= ~SPI_SR_WEL;
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001138 return 0;
1139}
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001140
Edward O'Callaghan5eca4272020-04-12 17:27:53 +10001141static int dummy_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001142 unsigned int readcnt,
1143 const unsigned char *writearr,
1144 unsigned char *readarr)
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001145{
Nico Huber519be662018-12-23 20:03:35 +01001146 unsigned int i;
Lachlan Bishopc753c402020-09-10 14:57:05 +10001147 struct emu_data *emu_data = flash->mst->spi.data;
1148 if (!emu_data) {
1149 msg_perr("No data in flash context!\n");
1150 return 1;
1151 }
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001152
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001153 msg_pspew("%s:", __func__);
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001154
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001155 msg_pspew(" writing %u bytes:", writecnt);
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001156 for (i = 0; i < writecnt; i++)
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001157 msg_pspew(" 0x%02x", writearr[i]);
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001158
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001159 /* Response for unknown commands and missing chip is 0xff. */
1160 memset(readarr, 0xff, readcnt);
Lachlan Bishopc753c402020-09-10 14:57:05 +10001161 switch (emu_data->emu_chip) {
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001162 case EMULATE_ST_M25P10_RES:
1163 case EMULATE_SST_SST25VF040_REMS:
1164 case EMULATE_SST_SST25VF032B:
Stefan Tauner0b9df972012-05-07 22:12:16 +00001165 case EMULATE_MACRONIX_MX25L6436:
Nico Huberf9632d82019-01-20 11:23:49 +01001166 case EMULATE_WINBOND_W25Q128FV:
Nico Huber4203a472022-05-28 17:28:05 +02001167 case EMULATE_SPANSION_S25FL128L:
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001168 if (emulate_spi_chip_response(writecnt, readcnt, writearr,
Lachlan Bishopc753c402020-09-10 14:57:05 +10001169 readarr, emu_data)) {
Carl-Daniel Hailfinger1b83be52012-02-08 23:28:54 +00001170 msg_pdbg("Invalid command sent to flash chip!\n");
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001171 return 1;
1172 }
1173 break;
1174 default:
1175 break;
1176 }
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001177 msg_pspew(" reading %u bytes:", readcnt);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001178 for (i = 0; i < readcnt; i++)
Carl-Daniel Hailfingerf68aa8a2010-11-01 22:07:04 +00001179 msg_pspew(" 0x%02x", readarr[i]);
Carl-Daniel Hailfinger3ac101c2010-01-09 04:32:23 +00001180 msg_pspew("\n");
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +00001181 return 0;
1182}
Carl-Daniel Hailfinger1b0ba892010-06-20 10:58:32 +00001183
Mark Marshallf20b7be2014-05-09 21:16:21 +00001184static int dummy_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001185{
Edward O'Callaghanb1313422021-05-20 20:27:59 +10001186 const struct emu_data *const data = flash->mst->spi.data;
1187 return spi_write_chunked(flash, buf, start, len, data->spi_write_256_chunksize);
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001188}
Thomas Heijligencc853d82021-05-04 15:32:17 +02001189
Nikolai Artemieve7a41e32022-11-28 17:40:56 +11001190static bool dummy_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
Aarya Chaumal0cea7532022-07-04 18:21:50 +05301191{
1192 size_t i;
Nikolai Artemieve7a41e32022-11-28 17:40:56 +11001193 const struct emu_data *emu_data = flash->mst->spi.data;
Aarya Chaumal0cea7532022-07-04 18:21:50 +05301194 for (i = 0; i < emu_data->spi_blacklist_size; i++) {
1195 if (emu_data->spi_blacklist[i] == opcode)
1196 return false;
1197 }
1198 return true;
1199}
1200
Thomas Heijligencc853d82021-05-04 15:32:17 +02001201const struct programmer_entry programmer_dummy = {
1202 .name = "dummy",
1203 .type = OTHER,
1204 /* FIXME */
1205 .devs.note = "Dummy device, does nothing and logs all accesses\n",
1206 .init = dummy_init,
1207 .map_flash_region = dummy_map,
1208 .unmap_flash_region = dummy_unmap,
Thomas Heijligencc853d82021-05-04 15:32:17 +02001209};