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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000019 */
20
21#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000022
Uwe Hermann09e04f72009-05-16 22:36:00 +000023static int erase_sector_29f040b(chipaddr bios, unsigned long address)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000024{
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000025 chip_writeb(0xAA, bios + 0x555);
26 chip_writeb(0x55, bios + 0x2AA);
27 chip_writeb(0x80, bios + 0x555);
28 chip_writeb(0xAA, bios + 0x555);
29 chip_writeb(0x55, bios + 0x2AA);
30 chip_writeb(0x30, bios + address);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000031
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000032 programmer_delay(2 * 1000 * 1000);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000033
34 /* wait for Toggle bit ready */
35 toggle_ready_jedec(bios + address);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000036
Uwe Hermannffec5f32007-08-23 16:08:21 +000037 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000038}
39
Uwe Hermann09e04f72009-05-16 22:36:00 +000040static int write_sector_29f040b(chipaddr bios, uint8_t *src, chipaddr dst,
41 unsigned int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000042{
43 int i;
44
45 for (i = 0; i < page_size; i++) {
Uwe Hermann0b7afe62007-04-01 19:44:21 +000046 if ((i & 0xfff) == 0xfff)
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000047 printf("0x%08lx", dst - bios);
Ollie Lho761bf1b2004-03-20 16:46:10 +000048
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000049 chip_writeb(0xAA, bios + 0x555);
50 chip_writeb(0x55, bios + 0x2AA);
51 chip_writeb(0xA0, bios + 0x555);
52 chip_writeb(*src++, dst++);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000053
54 /* wait for Toggle bit ready */
55 toggle_ready_jedec(bios);
56
Uwe Hermann0b7afe62007-04-01 19:44:21 +000057 if ((i & 0xfff) == 0xfff)
Stefan Reinauer99349a52006-03-16 16:46:19 +000058 printf("\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000059 }
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000060
Uwe Hermannffec5f32007-08-23 16:08:21 +000061 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000062}
63
Ollie Lho761bf1b2004-03-20 16:46:10 +000064int probe_29f040b(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000065{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000066 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000067 uint8_t id1, id2;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000068
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000069 chip_writeb(0xAA, bios + 0x555);
70 chip_writeb(0x55, bios + 0x2AA);
71 chip_writeb(0x90, bios + 0x555);
Ollie Lho761bf1b2004-03-20 16:46:10 +000072
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000073 id1 = chip_readb(bios);
74 id2 = chip_readb(bios + 0x01);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000075
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000076 chip_writeb(0xF0, bios);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000077
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000078 programmer_delay(10);
Ollie Lho761bf1b2004-03-20 16:46:10 +000079
Peter Stuge5cafc332009-01-25 23:52:45 +000080 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000081 if (id1 == flash->manufacture_id && id2 == flash->model_id)
82 return 1;
83
84 return 0;
85}
86
Ollie Lho761bf1b2004-03-20 16:46:10 +000087int erase_29f040b(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000088{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000089 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000090
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000091 chip_writeb(0xAA, bios + 0x555);
92 chip_writeb(0x55, bios + 0x2AA);
93 chip_writeb(0x80, bios + 0x555);
94 chip_writeb(0xAA, bios + 0x555);
95 chip_writeb(0x55, bios + 0x2AA);
96 chip_writeb(0x10, bios + 0x555);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000097
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000098 programmer_delay(10);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000099 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000100
Uwe Hermannffec5f32007-08-23 16:08:21 +0000101 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000102}
103
Ollie Lho184a4042005-11-26 21:55:36 +0000104int write_29f040b(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000105{
106 int i;
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000107 int total_size = flash->total_size * 1024;
108 int page_size = flash->page_size;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000109 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000110
Stefan Reinauer99349a52006-03-16 16:46:19 +0000111 printf("Programming page ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000112 for (i = 0; i < total_size / page_size; i++) {
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000113 /* erase the page before programming */
114 erase_sector_29f040b(bios, i * page_size);
115
116 /* write to the sector */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000117 printf("%04d at address: ", i);
118 write_sector_29f040b(bios, buf + i * page_size,
119 bios + i * page_size, page_size);
120 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000121 }
122 printf("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000123
Uwe Hermannffec5f32007-08-23 16:08:21 +0000124 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000125}