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review.sourcearcade.org / libgfxinit / 6489f3d262e772742075a6a405d7259075487c62 / . / common / ironlake / hw-gfx-gma-plls.adb
blob: 8b6ca36b26841ec1bce53e1674ac7f780255756d [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with HW.Time;
16with HW.GFX.GMA.Config;
17with HW.GFX.GMA.Registers;
18
19with HW.Debug;
20with GNAT.Source_Info;
21
22package body HW.GFX.GMA.PLLs
23with
24 Refined_State => (State => PLLs)
25is
26
27 Debug_Clocks : constant Boolean := False;
28
29 type Count_Range is new Natural range 0 .. 2;
30
31 type PLL_State is record
32 Use_Count : Count_Range;
33 Used_For_DP : Boolean;
34 Link_Rate : DP_Bandwidth;
35 Mode : Mode_Type;
36 end record;
37
38 type PLL_State_Array is array (DPLLs) of PLL_State;
39
40 PLLs : PLL_State_Array;
41
42 ----------------------------------------------------------------------------
43
44 subtype N_Range is Int64 range 3 .. 8;
45 subtype M_Range is Int64 range 79 .. 128;
46 subtype M1_Range is Int64 range 14 .. 25;
47 subtype M2_Range is Int64 range 7 .. 12;
48 subtype P_Range is Int64 range 5 .. 112;
49 subtype P1_Range is Int64 range 1 .. 8;
50 subtype P2_Range is Int64 range 5 .. 14;
51 subtype VCO_Range is Int64 range 1760000000 .. 3510000000;
52 subtype Clock_Range is HW.GFX.Frequency_Type;
53
54 type Clock_Type is
55 record
56 N : N_Range;
57 M1 : M1_Range;
58 M2 : M2_Range;
59 P1 : P1_Range;
60 P2 : P2_Range;
61 M : M_Range;
62 P : P_Range;
63 VCO : VCO_Range;
64 Reference_Clock : Clock_Range;
65 Dotclock : Clock_Range;
66 end record;
67
68 Invalid_Clock : constant Clock_Type := Clock_Type'
69 (N => N_Range'Last,
70 M1 => M1_Range'Last,
71 M2 => M2_Range'Last,
72 P1 => P1_Range'Last,
73 P2 => P2_Range'Last,
74 Reference_Clock => Clock_Range'Last,
75 M => M_Range'Last,
76 P => P_Range'Last,
77 VCO => VCO_Range'Last,
78 Dotclock => Clock_Range'Last);
79
80 type Limits_Type is
81 record
82 N_Lower : N_Range;
83 N_Upper : N_Range;
84 M_Lower : M_Range;
85 M_Upper : M_Range;
86 M1_Lower : M1_Range;
87 M1_Upper : M1_Range;
88 M2_Lower : M2_Range;
89 M2_Upper : M2_Range;
90 P_Lower : P_Range;
91 P_Upper : P_Range;
92 P1_Lower : P1_Range;
93 P1_Upper : P1_Range;
94 P2_Fast : P2_Range;
95 P2_Slow : P2_Range;
96 P2_Threshold : Clock_Range;
97 VCO_Lower : VCO_Range;
98 VCO_Upper : VCO_Range;
99 end record;
100
101 LVDS_Single_Limits : constant Limits_Type := Limits_Type'
102 (N_Lower => 3, N_Upper => 5,
103 M_Lower => 79, M_Upper => 118,
104 M1_Lower => 14, M1_Upper => 22, -- this is capped by M_Upper >= 5 * M1 + M2_Lower
105 M2_Lower => 7, M2_Upper => 11,
106 P_Lower => 28, P_Upper => 112,
107 P1_Lower => 2, P1_Upper => 8,
108 P2_Fast => 14, P2_Slow => 14,
109 P2_Threshold => Clock_Range'First,
110 VCO_Lower => 1_760_000_000, VCO_Upper => 3_510_000_000);
111 LVDS_Dual_Limits : constant Limits_Type := Limits_Type'
112 (N_Lower => 3, N_Upper => 5,
113 M_Lower => 79, M_Upper => 127,
114 M1_Lower => 14, M1_Upper => 24,
115 M2_Lower => 7, M2_Upper => 11,
116 P_Lower => 14, P_Upper => 56,
117 P1_Lower => 2, P1_Upper => 8,
118 P2_Fast => 7, P2_Slow => 7,
119 P2_Threshold => Clock_Range'First,
120 VCO_Lower => 1_760_000_000, VCO_Upper => 3_510_000_000);
121 All_Other_Limits : constant Limits_Type := Limits_Type'
122 (N_Lower => 3, N_Upper => 7,
123 M_Lower => 79, M_Upper => 127,
124 M1_Lower => 14, M1_Upper => 24,
125 M2_Lower => 7, M2_Upper => 11,
126 P_Lower => 5, P_Upper => 80,
127 P1_Lower => 1, P1_Upper => 8,
128 -- use P2_Slow if Dotclock <= P2_Threshold, P2_Fast otherwise
129 P2_Fast => 5, P2_Slow => 10,
130 P2_Threshold => 225_000_000,
131 VCO_Lower => 1_760_000_000, VCO_Upper => 3_510_000_000);
132
133 ----------------------------------------------------------------------------
134
135 type Regs is array (DPLLs) of Registers.Registers_Index;
136
137 DPLL : constant Regs := Regs'(Registers.PCH_DPLL_A, Registers.PCH_DPLL_B);
138 DPLL_VCO_ENABLE : constant := 1 * 2 ** 31;
139 DPLL_P2_10_OR_14 : constant := 0 * 2 ** 24;
140 DPLL_P2_5_OR_7 : constant := 1 * 2 ** 24;
141 DPLL_P1_DIVIDER_SHIFT : constant := 16;
142 DPLL_SDVOCLK : constant := 2 * 2 ** 13;
143
144 DPLL_HIGH_SPEED : constant := 1 * 2 ** 30;
145 DPLL_MODE_LVDS : constant := 2 * 2 ** 26;
146 DPLL_MODE_DAC : constant := 1 * 2 ** 26;
147 DPLL_DREFCLK : constant := 0 * 2 ** 13;
148 DPLL_SSC : constant := 3 * 2 ** 13;
149
150 MODE_DPLL_DAC_HDMI : constant Word32 := Word32'
151 (DPLL_MODE_DAC or DPLL_DREFCLK or DPLL_HIGH_SPEED);
152
153 MODE_DPLL_LVDS : constant Word32 := Word32'
154 (DPLL_MODE_LVDS or DPLL_SSC);
155
156 MODE_DPLL_DP : constant Word32 := Word32'
157 (DPLL_MODE_DAC or DPLL_SSC or DPLL_HIGH_SPEED);
158
159 type DPLL_Mode_Array is array (Display_Type) of Word32;
160
161 DPLL_Mode : constant DPLL_Mode_Array := DPLL_Mode_Array'
162 (LVDS => MODE_DPLL_LVDS,
163 DP => MODE_DPLL_DP,
164 others => MODE_DPLL_DAC_HDMI);
165
166 FP0 : constant Regs := Regs'(Registers.PCH_FPA0, Registers.PCH_FPB0);
167 FP1 : constant Regs := Regs'(Registers.PCH_FPA1, Registers.PCH_FPB1);
168 FP_DOUBLE_CLOCK : constant := 1 * 2 ** 27;
169 FP_N_SHIFT : constant := 16;
170 FP_M1_SHIFT : constant := 8;
171 FP_M2_SHIFT : constant := 0;
172
173 ----------------------------------------------------------------------------
174
175 procedure Verify_Parameters
176 (N : in N_Range;
177 M1 : in M1_Range;
178 M2 : in M2_Range;
179 P1 : in P1_Range;
180 P2 : in P2_Range;
181 Reference_Clock : in Clock_Range;
182 Current_Limits : in Limits_Type;
183 Result : out Clock_Type;
184 Valid : out Boolean)
185 with
186 Global => null,
187 Pre => True,
188 Post => True
189 is
190 M : Int64;
191 P : Int64;
192 VCO : Int64;
193 Dotclock : Int64;
194 begin
195 pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
196
197 M := 5 * M1 + M2;
198 P := P1 * P2;
199 VCO := (Int64 (Reference_Clock) * M) / N;
200 Dotclock := VCO / P;
201
202 pragma Debug (Debug_Clocks and not (Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper ), Debug.Put_Line ("P1 out of range."));
203 pragma Debug (Debug_Clocks and (Current_Limits.P2_Fast /= P2 and P2 /= Current_Limits.P2_Slow ), Debug.Put_Line ("P2 out of range."));
204 pragma Debug (Debug_Clocks and not (Current_Limits.P_Lower <= P and P <= Current_Limits.P_Upper ), Debug.Put_Line ("P out of range."));
205 pragma Debug (Debug_Clocks and not (Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper ), Debug.Put_Line ("M1 out of range."));
206 pragma Debug (Debug_Clocks and not (Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper ), Debug.Put_Line ("M2 out of range."));
207 -- pragma Debug (Debug_Clocks and not (M2 <= M1 ), Debug.Put_Line ("M1 greater thant M2."));
208 pragma Debug (Debug_Clocks and not (Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper ), Debug.Put_Line ("N out of range."));
209 pragma Debug (Debug_Clocks and not (Current_Limits.M_Lower <= M and M <= Current_Limits.M_Upper ), Debug.Put_Line ("M out of range."));
210 pragma Debug (Debug_Clocks and not (Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper), Debug.Put_Line ("VCO out of range."));
211
212 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Line ("Dotclock too low."));
213 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Int64 (Dotclock));
214 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.New_Line);
215
216 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Line ("Dotclock too high."));
217 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Int64 (Dotclock));
218 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.New_Line);
219
220 Valid :=
221 Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper and
222 (Current_Limits.P2_Fast = P2 or P2 = Current_Limits.P2_Slow) and
223 Current_Limits.P_Lower <= P and P <= Current_Limits.P_Upper and
224 Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper and
225 Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper and
226 -- M2 <= M1 and
227 Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper and
228 Current_Limits.M_Lower <= M and M <= Current_Limits.M_Upper and
229 Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper and
230 Int64 (Clock_Range'First) <= Dotclock and
231 Dotclock <= Int64 (Clock_Range'Last);
232
233 if Valid
234 then
235 Result := Clock_Type'
236 (N => N,
237 M1 => M1,
238 M2 => M2,
239 P1 => P1,
240 P2 => P2,
241 Reference_Clock => Reference_Clock,
242 M => M,
243 P => P,
244 VCO => VCO,
245 Dotclock => Clock_Range (Dotclock));
246 else
247 Result := Invalid_Clock;
248 end if;
249
250 end Verify_Parameters;
251
252 procedure Calculate_Clock_Parameters
253 (Display : in Display_Type;
254 Target_Dotclock : in Clock_Range;
255 Reference_Clock : in Clock_Range;
256 Best_Clock : out Clock_Type;
257 Valid : out Boolean)
258 with
259 Global => null,
260 Pre => True,
261 Post => True
262 is
263 Limits : constant Limits_Type :=
264 (if Display = LVDS then
265 (if Target_Dotclock >= Config.LVDS_Dual_Threshold then
266 LVDS_Dual_Limits
267 else
268 LVDS_Single_Limits)
269 else
270 All_Other_Limits);
271
272 P2 : P2_Range;
273 Best_Delta : Int64 := Int64'Last;
274 Current_Delta : Int64;
275 Current_Clock : Clock_Type;
276 Registers_Valid : Boolean;
277 begin
278 pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
279
280 Valid := False;
281 Best_Clock := Invalid_Clock;
282
283 if Target_Dotclock <= Limits.P2_Threshold then
284 P2 := Limits.P2_Slow;
285 else
286 P2 := Limits.P2_Fast;
287 end if;
288
289 for N in N_Range range Limits.N_Lower .. Limits.N_Upper
290 loop
291 -- reverse loops as hardware prefers higher values
292 for M1 in reverse M1_Range range Limits.M1_Lower .. Limits.M1_Upper
293 loop
Nico Huber3652e9c2022-09-04 14:29:30 +0000[diff] [blame]294 pragma Loop_Invariant (True);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]295 for M2 in reverse M2_Range range Limits.M2_Lower .. Limits.M2_Upper
296 loop
Nico Huber3652e9c2022-09-04 14:29:30 +0000[diff] [blame]297 pragma Loop_Invariant (True);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]298 for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper
299 loop
300 Verify_Parameters
301 (N => N,
302 M1 => M1,
303 M2 => M2,
304 P1 => P1,
305 P2 => P2,
306 Reference_Clock => Reference_Clock,
307 Current_Limits => Limits,
308 Result => Current_Clock,
309 Valid => Registers_Valid);
310
311 if Registers_Valid
312 then
313 if Current_Clock.Dotclock > Target_Dotclock
314 then
315 Current_Delta := Current_Clock.Dotclock - Target_Dotclock;
316 else
317 Current_Delta := Target_Dotclock - Current_Clock.Dotclock;
318 end if;
319
320 if Current_Delta < Best_Delta
321 then
322 Best_Delta := Current_Delta;
323 Best_Clock := Current_Clock;
324 Valid := True;
325 end if;
326
327 pragma Debug (Debug_Clocks, Debug.Put ("Current/Target/Best_Delta: "));
328 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Current_Clock.Dotclock));
329 pragma Debug (Debug_Clocks, Debug.Put ("/"));
330 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Target_Dotclock));
331 pragma Debug (Debug_Clocks, Debug.Put ("/"));
332 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Best_Delta));
333 pragma Debug (Debug_Clocks, Debug.Put_Line ("."));
334
335 end if;
336 end loop;
337 end loop;
338 end loop;
339 end loop;
340
341 pragma Debug (Valid, Debug.Put_Line ("Valid clock found."));
342 pragma Debug (Valid, Debug.Put ("Best/Target/Delta: "));
343 pragma Debug (Valid, Debug.Put_Int64 (Best_Clock.Dotclock));
344 pragma Debug (Valid, Debug.Put ("/"));
345 pragma Debug (Valid, Debug.Put_Int64 (Target_Dotclock));
346 pragma Debug (Valid, Debug.Put ("/"));
347 pragma Debug (Valid, Debug.Put_Int64 (Best_Delta));
348 pragma Debug (Valid, Debug.Put_Line ("."));
349 pragma Debug (not Valid, Debug.Put_Line ("No valid clock found."));
350
351 end Calculate_Clock_Parameters;
352
353 procedure Program_DPLL
354 (PLL : DPLLs;
355 Display : Display_Type;
356 Clk : Clock_Type)
357 with
358 Global => (In_Out => Registers.Register_State),
359 Pre => True,
360 Post => True
361 is
362 FP, Encoded_P1, Encoded_P2 : Word32;
363 begin
364 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
365
366 FP :=
367 Shift_Left (Word32 (Clk.N - 2), FP_N_SHIFT) or
368 Shift_Left (Word32 (Clk.M1 - 2), FP_M1_SHIFT) or
369 Shift_Left (Word32 (Clk.M2 - 2), FP_M2_SHIFT);
370
371 Registers.Write (FP0 (PLL), FP);
372 Registers.Write (FP1 (PLL), FP);
373
374 Encoded_P1 := Shift_Left (1, Natural (Clk.P1) - 1);
375
376 if Clk.P2 = 5 or Clk.P2 = 7
377 then
378 Encoded_P2 := DPLL_P2_5_OR_7;
379 else
380 Encoded_P2 := DPLL_P2_10_OR_14;
381 end if;
382
383 Registers.Write
384 (Register => DPLL (PLL),
385 Value => DPLL_Mode (Display) or
386 Encoded_P2 or
387 Shift_Left (Encoded_P1, DPLL_P1_DIVIDER_SHIFT) or
388 Encoded_P1);
389 end Program_DPLL;
390
391 procedure On
392 (PLL : in T;
393 Port_Cfg : in Port_Config;
394 Success : out Boolean)
395 is
396 Target_Clock : constant Frequency_Type :=
397 (if Port_Cfg.Display = DP then
398 DP_Symbol_Rate (Port_Cfg.DP.Bandwidth)
399 else
400 Port_Cfg.Mode.Dotclock);
401 Clk : Clock_Type;
402 begin
403 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
404
405 Success := PLL in DPLLs;
406 Clk := Invalid_Clock;
407
408 if Success then
409 if Port_Cfg.Display = DP then
410 Success := True;
411 -- we use static values for DP
412 case Port_Cfg.DP.Bandwidth is
413 when DP_Bandwidth_1_62 =>
414 Clk.N := 3;
415 Clk.M1 := 14;
416 Clk.M2 := 11;
417 Clk.P1 := 2;
418 Clk.P2 := 10;
419 when DP_Bandwidth_2_7 =>
420 Clk.N := 4;
421 Clk.M1 := 16;
422 Clk.M2 := 10;
423 Clk.P1 := 1;
424 Clk.P2 := 10;
425 when others =>
426 Success := False;
427 end case;
428 elsif Target_Clock <= 340_000_000 then
429 Calculate_Clock_Parameters
430 (Display => Port_Cfg.Display,
431 Target_Dotclock => Target_Clock,
432 -- should be, but doesn't has to be always the same:
433 Reference_Clock => 120_000_000,
434 Best_Clock => Clk,
435 Valid => Success);
436 else
437 Success := False;
438 pragma Debug (Debug.Put ("WARNING: Targeted clock too high: "));
439 pragma Debug (Debug.Put_Int64 (Target_Clock));
440 pragma Debug (Debug.Put (" > "));
441 pragma Debug (Debug.Put_Int32 (340_000_000));
442 pragma Debug (Debug.New_Line);
443 pragma Debug (Debug.New_Line);
444 end if;
445 end if;
446
447 if Success then
448 Program_DPLL (PLL, Port_Cfg.Display, Clk);
449
450 Registers.Set_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
451 Registers.Posting_Read (DPLL (PLL));
452 Time.U_Delay (150);
453 end if;
454 end On;
455
456 procedure Off (PLL : T)
457 is
458 begin
459 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
460
461 if PLL in DPLLs then
462 Registers.Unset_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
463 end if;
464 end Off;
465
466 ----------------------------------------------------------------------------
467
468 procedure Initialize
469 is
470 begin
471 PLLs :=
472 (DPLLs =>
473 (Use_Count => 0,
474 Used_For_DP => False,
475 Link_Rate => DP_Bandwidth'First,
476 Mode => Invalid_Mode));
477 end Initialize;
478
479 procedure Alloc_Configurable
480 (Port_Cfg : in Port_Config;
481 PLL : out T;
482 Success : out Boolean)
483 with
484 Pre => True
485 is
486 function Config_Matches (PE : PLL_State) return Boolean
487 is
488 begin
489 return
490 PE.Used_For_DP = (Port_Cfg.Display = DP) and
491 ((PE.Used_For_DP and PE.Link_Rate = Port_Cfg.DP.Bandwidth) or
492 (not PE.Used_For_DP and PE.Mode = Port_Cfg.Mode));
493 end Config_Matches;
494 begin
495 -- try to find shareable PLL
496 for P in DPLLs loop
497 Success := PLLs (P).Use_Count /= 0 and
498 PLLs (P).Use_Count /= Count_Range'Last and
499 Config_Matches (PLLs (P));
500 if Success then
501 PLL := P;
502 PLLs (PLL).Use_Count := PLLs (PLL).Use_Count + 1;
503 return;
504 end if;
505 end loop;
506
507 -- try to find free PLL
508 for P in DPLLs loop
509 if PLLs (P).Use_Count = 0 then
510 PLL := P;
511 On (PLL, Port_Cfg, Success);
512 if Success then
513 PLLs (PLL) :=
514 (Use_Count => 1,
515 Used_For_DP => Port_Cfg.Display = DP,
516 Link_Rate => Port_Cfg.DP.Bandwidth,
517 Mode => Port_Cfg.Mode);
518 end if;
519 return;
520 end if;
521 end loop;
522
523 PLL := Invalid;
524 end Alloc_Configurable;
525
526 procedure Alloc
527 (Port_Cfg : in Port_Config;
528 PLL : out T;
529 Success : out Boolean)
530 is
531 begin
532 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
533
534 if Port_Cfg.Port = DIGI_A then
535 PLL := Invalid;
536 Success := True;
537 else
538 Alloc_Configurable (Port_Cfg, PLL, Success);
539 end if;
540 end Alloc;
541
542 procedure Free (PLL : T)
543 is
544 begin
545 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
546
547 if PLL in DPLLs then
548 if PLLs (PLL).Use_Count /= 0 then
549 PLLs (PLL).Use_Count := PLLs (PLL).Use_Count - 1;
550 if PLLs (PLL).Use_Count = 0 then
551 Off (PLL);
552 end if;
553 end if;
554 end if;
555 end Free;
556
557 procedure All_Off
558 is
559 begin
560 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
561
562 for PLL in DPLLs loop
563 Off (PLL);
564 end loop;
565 end All_Off;
566
567 function Register_Value (PLL : T) return Word32
568 is
569 begin
570 return (if PLL = DPLL_B then 1 else 0);
571 end Register_Value;
572
573end HW.GFX.GMA.PLLs;