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review.sourcearcade.org / libgfxinit / 83693c8d7d87f5cebe120abdf25951c9e212b319 / . / common / ironlake / hw-gfx-gma-plls.adb
blob: 7ecfb66aa768b16e6bc175f485cc53586b642334 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame^]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
6-- the Free Software Foundation; version 2 of the License.
7--
8-- This program is distributed in the hope that it will be useful,
9-- but WITHOUT ANY WARRANTY; without even the implied warranty of
10-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11-- GNU General Public License for more details.
12--
13
14with HW.Time;
15with HW.GFX.GMA.Config;
16with HW.GFX.GMA.Registers;
17
18with HW.Debug;
19with GNAT.Source_Info;
20
21package body HW.GFX.GMA.PLLs
22with
23 Refined_State => (State => PLLs)
24is
25
26 Debug_Clocks : constant Boolean := False;
27
28 type Count_Range is new Natural range 0 .. 2;
29
30 type PLL_State is record
31 Use_Count : Count_Range;
32 Used_For_DP : Boolean;
33 Link_Rate : DP_Bandwidth;
34 Mode : Mode_Type;
35 end record;
36
37 type PLL_State_Array is array (DPLLs) of PLL_State;
38
39 PLLs : PLL_State_Array;
40
41 ----------------------------------------------------------------------------
42
43 subtype N_Range is Int64 range 3 .. 8;
44 subtype M_Range is Int64 range 79 .. 128;
45 subtype M1_Range is Int64 range 14 .. 25;
46 subtype M2_Range is Int64 range 7 .. 12;
47 subtype P_Range is Int64 range 5 .. 112;
48 subtype P1_Range is Int64 range 1 .. 8;
49 subtype P2_Range is Int64 range 5 .. 14;
50 subtype VCO_Range is Int64 range 1760000000 .. 3510000000;
51 subtype Clock_Range is HW.GFX.Frequency_Type;
52
53 type Clock_Type is
54 record
55 N : N_Range;
56 M1 : M1_Range;
57 M2 : M2_Range;
58 P1 : P1_Range;
59 P2 : P2_Range;
60 M : M_Range;
61 P : P_Range;
62 VCO : VCO_Range;
63 Reference_Clock : Clock_Range;
64 Dotclock : Clock_Range;
65 end record;
66
67 Invalid_Clock : constant Clock_Type := Clock_Type'
68 (N => N_Range'Last,
69 M1 => M1_Range'Last,
70 M2 => M2_Range'Last,
71 P1 => P1_Range'Last,
72 P2 => P2_Range'Last,
73 Reference_Clock => Clock_Range'Last,
74 M => M_Range'Last,
75 P => P_Range'Last,
76 VCO => VCO_Range'Last,
77 Dotclock => Clock_Range'Last);
78
79 type Limits_Type is
80 record
81 N_Lower : N_Range;
82 N_Upper : N_Range;
83 M_Lower : M_Range;
84 M_Upper : M_Range;
85 M1_Lower : M1_Range;
86 M1_Upper : M1_Range;
87 M2_Lower : M2_Range;
88 M2_Upper : M2_Range;
89 P_Lower : P_Range;
90 P_Upper : P_Range;
91 P1_Lower : P1_Range;
92 P1_Upper : P1_Range;
93 P2_Fast : P2_Range;
94 P2_Slow : P2_Range;
95 P2_Threshold : Clock_Range;
96 VCO_Lower : VCO_Range;
97 VCO_Upper : VCO_Range;
98 end record;
99
100 LVDS_Single_Limits : constant Limits_Type := Limits_Type'
101 (N_Lower => 3, N_Upper => 5,
102 M_Lower => 79, M_Upper => 118,
103 M1_Lower => 14, M1_Upper => 22, -- this is capped by M_Upper >= 5 * M1 + M2_Lower
104 M2_Lower => 7, M2_Upper => 11,
105 P_Lower => 28, P_Upper => 112,
106 P1_Lower => 2, P1_Upper => 8,
107 P2_Fast => 14, P2_Slow => 14,
108 P2_Threshold => Clock_Range'First,
109 VCO_Lower => 1_760_000_000, VCO_Upper => 3_510_000_000);
110 LVDS_Dual_Limits : constant Limits_Type := Limits_Type'
111 (N_Lower => 3, N_Upper => 5,
112 M_Lower => 79, M_Upper => 127,
113 M1_Lower => 14, M1_Upper => 24,
114 M2_Lower => 7, M2_Upper => 11,
115 P_Lower => 14, P_Upper => 56,
116 P1_Lower => 2, P1_Upper => 8,
117 P2_Fast => 7, P2_Slow => 7,
118 P2_Threshold => Clock_Range'First,
119 VCO_Lower => 1_760_000_000, VCO_Upper => 3_510_000_000);
120 All_Other_Limits : constant Limits_Type := Limits_Type'
121 (N_Lower => 3, N_Upper => 7,
122 M_Lower => 79, M_Upper => 127,
123 M1_Lower => 14, M1_Upper => 24,
124 M2_Lower => 7, M2_Upper => 11,
125 P_Lower => 5, P_Upper => 80,
126 P1_Lower => 1, P1_Upper => 8,
127 -- use P2_Slow if Dotclock <= P2_Threshold, P2_Fast otherwise
128 P2_Fast => 5, P2_Slow => 10,
129 P2_Threshold => 225_000_000,
130 VCO_Lower => 1_760_000_000, VCO_Upper => 3_510_000_000);
131
132 ----------------------------------------------------------------------------
133
134 type Regs is array (DPLLs) of Registers.Registers_Index;
135
136 DPLL : constant Regs := Regs'(Registers.PCH_DPLL_A, Registers.PCH_DPLL_B);
137 DPLL_VCO_ENABLE : constant := 1 * 2 ** 31;
138 DPLL_P2_10_OR_14 : constant := 0 * 2 ** 24;
139 DPLL_P2_5_OR_7 : constant := 1 * 2 ** 24;
140 DPLL_P1_DIVIDER_SHIFT : constant := 16;
141 DPLL_SDVOCLK : constant := 2 * 2 ** 13;
142
143 DPLL_HIGH_SPEED : constant := 1 * 2 ** 30;
144 DPLL_MODE_LVDS : constant := 2 * 2 ** 26;
145 DPLL_MODE_DAC : constant := 1 * 2 ** 26;
146 DPLL_DREFCLK : constant := 0 * 2 ** 13;
147 DPLL_SSC : constant := 3 * 2 ** 13;
148
149 MODE_DPLL_DAC_HDMI : constant Word32 := Word32'
150 (DPLL_MODE_DAC or DPLL_DREFCLK or DPLL_HIGH_SPEED);
151
152 MODE_DPLL_LVDS : constant Word32 := Word32'
153 (DPLL_MODE_LVDS or DPLL_SSC);
154
155 MODE_DPLL_DP : constant Word32 := Word32'
156 (DPLL_MODE_DAC or DPLL_SSC or DPLL_HIGH_SPEED);
157
158 type DPLL_Mode_Array is array (Display_Type) of Word32;
159
160 DPLL_Mode : constant DPLL_Mode_Array := DPLL_Mode_Array'
161 (LVDS => MODE_DPLL_LVDS,
162 DP => MODE_DPLL_DP,
163 others => MODE_DPLL_DAC_HDMI);
164
165 FP0 : constant Regs := Regs'(Registers.PCH_FPA0, Registers.PCH_FPB0);
166 FP1 : constant Regs := Regs'(Registers.PCH_FPA1, Registers.PCH_FPB1);
167 FP_DOUBLE_CLOCK : constant := 1 * 2 ** 27;
168 FP_N_SHIFT : constant := 16;
169 FP_M1_SHIFT : constant := 8;
170 FP_M2_SHIFT : constant := 0;
171
172 ----------------------------------------------------------------------------
173
174 procedure Verify_Parameters
175 (N : in N_Range;
176 M1 : in M1_Range;
177 M2 : in M2_Range;
178 P1 : in P1_Range;
179 P2 : in P2_Range;
180 Reference_Clock : in Clock_Range;
181 Current_Limits : in Limits_Type;
182 Result : out Clock_Type;
183 Valid : out Boolean)
184 with
185 Global => null,
186 Pre => True,
187 Post => True
188 is
189 M : Int64;
190 P : Int64;
191 VCO : Int64;
192 Dotclock : Int64;
193 begin
194 pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
195
196 M := 5 * M1 + M2;
197 P := P1 * P2;
198 VCO := (Int64 (Reference_Clock) * M) / N;
199 Dotclock := VCO / P;
200
201 pragma Debug (Debug_Clocks and not (Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper ), Debug.Put_Line ("P1 out of range."));
202 pragma Debug (Debug_Clocks and (Current_Limits.P2_Fast /= P2 and P2 /= Current_Limits.P2_Slow ), Debug.Put_Line ("P2 out of range."));
203 pragma Debug (Debug_Clocks and not (Current_Limits.P_Lower <= P and P <= Current_Limits.P_Upper ), Debug.Put_Line ("P out of range."));
204 pragma Debug (Debug_Clocks and not (Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper ), Debug.Put_Line ("M1 out of range."));
205 pragma Debug (Debug_Clocks and not (Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper ), Debug.Put_Line ("M2 out of range."));
206 -- pragma Debug (Debug_Clocks and not (M2 <= M1 ), Debug.Put_Line ("M1 greater thant M2."));
207 pragma Debug (Debug_Clocks and not (Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper ), Debug.Put_Line ("N out of range."));
208 pragma Debug (Debug_Clocks and not (Current_Limits.M_Lower <= M and M <= Current_Limits.M_Upper ), Debug.Put_Line ("M out of range."));
209 pragma Debug (Debug_Clocks and not (Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper), Debug.Put_Line ("VCO out of range."));
210
211 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Line ("Dotclock too low."));
212 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Int64 (Dotclock));
213 pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.New_Line);
214
215 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Line ("Dotclock too high."));
216 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Int64 (Dotclock));
217 pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.New_Line);
218
219 Valid :=
220 Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper and
221 (Current_Limits.P2_Fast = P2 or P2 = Current_Limits.P2_Slow) and
222 Current_Limits.P_Lower <= P and P <= Current_Limits.P_Upper and
223 Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper and
224 Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper and
225 -- M2 <= M1 and
226 Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper and
227 Current_Limits.M_Lower <= M and M <= Current_Limits.M_Upper and
228 Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper and
229 Int64 (Clock_Range'First) <= Dotclock and
230 Dotclock <= Int64 (Clock_Range'Last);
231
232 if Valid
233 then
234 Result := Clock_Type'
235 (N => N,
236 M1 => M1,
237 M2 => M2,
238 P1 => P1,
239 P2 => P2,
240 Reference_Clock => Reference_Clock,
241 M => M,
242 P => P,
243 VCO => VCO,
244 Dotclock => Clock_Range (Dotclock));
245 else
246 Result := Invalid_Clock;
247 end if;
248
249 end Verify_Parameters;
250
251 procedure Calculate_Clock_Parameters
252 (Display : in Display_Type;
253 Target_Dotclock : in Clock_Range;
254 Reference_Clock : in Clock_Range;
255 Best_Clock : out Clock_Type;
256 Valid : out Boolean)
257 with
258 Global => null,
259 Pre => True,
260 Post => True
261 is
262 Limits : constant Limits_Type :=
263 (if Display = LVDS then
264 (if Target_Dotclock >= Config.LVDS_Dual_Threshold then
265 LVDS_Dual_Limits
266 else
267 LVDS_Single_Limits)
268 else
269 All_Other_Limits);
270
271 P2 : P2_Range;
272 Best_Delta : Int64 := Int64'Last;
273 Current_Delta : Int64;
274 Current_Clock : Clock_Type;
275 Registers_Valid : Boolean;
276 begin
277 pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
278
279 Valid := False;
280 Best_Clock := Invalid_Clock;
281
282 if Target_Dotclock <= Limits.P2_Threshold then
283 P2 := Limits.P2_Slow;
284 else
285 P2 := Limits.P2_Fast;
286 end if;
287
288 for N in N_Range range Limits.N_Lower .. Limits.N_Upper
289 loop
290 -- reverse loops as hardware prefers higher values
291 for M1 in reverse M1_Range range Limits.M1_Lower .. Limits.M1_Upper
292 loop
293 for M2 in reverse M2_Range range Limits.M2_Lower .. Limits.M2_Upper
294 loop
295 for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper
296 loop
297 Verify_Parameters
298 (N => N,
299 M1 => M1,
300 M2 => M2,
301 P1 => P1,
302 P2 => P2,
303 Reference_Clock => Reference_Clock,
304 Current_Limits => Limits,
305 Result => Current_Clock,
306 Valid => Registers_Valid);
307
308 if Registers_Valid
309 then
310 if Current_Clock.Dotclock > Target_Dotclock
311 then
312 Current_Delta := Current_Clock.Dotclock - Target_Dotclock;
313 else
314 Current_Delta := Target_Dotclock - Current_Clock.Dotclock;
315 end if;
316
317 if Current_Delta < Best_Delta
318 then
319 Best_Delta := Current_Delta;
320 Best_Clock := Current_Clock;
321 Valid := True;
322 end if;
323
324 pragma Debug (Debug_Clocks, Debug.Put ("Current/Target/Best_Delta: "));
325 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Current_Clock.Dotclock));
326 pragma Debug (Debug_Clocks, Debug.Put ("/"));
327 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Target_Dotclock));
328 pragma Debug (Debug_Clocks, Debug.Put ("/"));
329 pragma Debug (Debug_Clocks, Debug.Put_Int64 (Best_Delta));
330 pragma Debug (Debug_Clocks, Debug.Put_Line ("."));
331
332 end if;
333 end loop;
334 end loop;
335 end loop;
336 end loop;
337
338 pragma Debug (Valid, Debug.Put_Line ("Valid clock found."));
339 pragma Debug (Valid, Debug.Put ("Best/Target/Delta: "));
340 pragma Debug (Valid, Debug.Put_Int64 (Best_Clock.Dotclock));
341 pragma Debug (Valid, Debug.Put ("/"));
342 pragma Debug (Valid, Debug.Put_Int64 (Target_Dotclock));
343 pragma Debug (Valid, Debug.Put ("/"));
344 pragma Debug (Valid, Debug.Put_Int64 (Best_Delta));
345 pragma Debug (Valid, Debug.Put_Line ("."));
346 pragma Debug (not Valid, Debug.Put_Line ("No valid clock found."));
347
348 end Calculate_Clock_Parameters;
349
350 procedure Program_DPLL
351 (PLL : DPLLs;
352 Display : Display_Type;
353 Clk : Clock_Type)
354 with
355 Global => (In_Out => Registers.Register_State),
356 Pre => True,
357 Post => True
358 is
359 FP, Encoded_P1, Encoded_P2 : Word32;
360 begin
361 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
362
363 FP :=
364 Shift_Left (Word32 (Clk.N - 2), FP_N_SHIFT) or
365 Shift_Left (Word32 (Clk.M1 - 2), FP_M1_SHIFT) or
366 Shift_Left (Word32 (Clk.M2 - 2), FP_M2_SHIFT);
367
368 Registers.Write (FP0 (PLL), FP);
369 Registers.Write (FP1 (PLL), FP);
370
371 Encoded_P1 := Shift_Left (1, Natural (Clk.P1) - 1);
372
373 if Clk.P2 = 5 or Clk.P2 = 7
374 then
375 Encoded_P2 := DPLL_P2_5_OR_7;
376 else
377 Encoded_P2 := DPLL_P2_10_OR_14;
378 end if;
379
380 Registers.Write
381 (Register => DPLL (PLL),
382 Value => DPLL_Mode (Display) or
383 Encoded_P2 or
384 Shift_Left (Encoded_P1, DPLL_P1_DIVIDER_SHIFT) or
385 Encoded_P1);
386 end Program_DPLL;
387
388 procedure On
389 (PLL : in T;
390 Port_Cfg : in Port_Config;
391 Success : out Boolean)
392 is
393 Target_Clock : constant Frequency_Type :=
394 (if Port_Cfg.Display = DP then
395 DP_Symbol_Rate (Port_Cfg.DP.Bandwidth)
396 else
397 Port_Cfg.Mode.Dotclock);
398 Clk : Clock_Type;
399 begin
400 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
401
402 Success := PLL in DPLLs;
403 Clk := Invalid_Clock;
404
405 if Success then
406 if Port_Cfg.Display = DP then
407 Success := True;
408 -- we use static values for DP
409 case Port_Cfg.DP.Bandwidth is
410 when DP_Bandwidth_1_62 =>
411 Clk.N := 3;
412 Clk.M1 := 14;
413 Clk.M2 := 11;
414 Clk.P1 := 2;
415 Clk.P2 := 10;
416 when DP_Bandwidth_2_7 =>
417 Clk.N := 4;
418 Clk.M1 := 16;
419 Clk.M2 := 10;
420 Clk.P1 := 1;
421 Clk.P2 := 10;
422 when others =>
423 Success := False;
424 end case;
425 elsif Target_Clock <= 340_000_000 then
426 Calculate_Clock_Parameters
427 (Display => Port_Cfg.Display,
428 Target_Dotclock => Target_Clock,
429 -- should be, but doesn't has to be always the same:
430 Reference_Clock => 120_000_000,
431 Best_Clock => Clk,
432 Valid => Success);
433 else
434 Success := False;
435 pragma Debug (Debug.Put ("WARNING: Targeted clock too high: "));
436 pragma Debug (Debug.Put_Int64 (Target_Clock));
437 pragma Debug (Debug.Put (" > "));
438 pragma Debug (Debug.Put_Int32 (340_000_000));
439 pragma Debug (Debug.New_Line);
440 pragma Debug (Debug.New_Line);
441 end if;
442 end if;
443
444 if Success then
445 Program_DPLL (PLL, Port_Cfg.Display, Clk);
446
447 Registers.Set_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
448 Registers.Posting_Read (DPLL (PLL));
449 Time.U_Delay (150);
450 end if;
451 end On;
452
453 procedure Off (PLL : T)
454 is
455 begin
456 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
457
458 if PLL in DPLLs then
459 Registers.Unset_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
460 end if;
461 end Off;
462
463 ----------------------------------------------------------------------------
464
465 procedure Initialize
466 is
467 begin
468 PLLs :=
469 (DPLLs =>
470 (Use_Count => 0,
471 Used_For_DP => False,
472 Link_Rate => DP_Bandwidth'First,
473 Mode => Invalid_Mode));
474 end Initialize;
475
476 procedure Alloc_Configurable
477 (Port_Cfg : in Port_Config;
478 PLL : out T;
479 Success : out Boolean)
480 with
481 Pre => True
482 is
483 function Config_Matches (PE : PLL_State) return Boolean
484 is
485 begin
486 return
487 PE.Used_For_DP = (Port_Cfg.Display = DP) and
488 ((PE.Used_For_DP and PE.Link_Rate = Port_Cfg.DP.Bandwidth) or
489 (not PE.Used_For_DP and PE.Mode = Port_Cfg.Mode));
490 end Config_Matches;
491 begin
492 -- try to find shareable PLL
493 for P in DPLLs loop
494 Success := PLLs (P).Use_Count /= 0 and
495 PLLs (P).Use_Count /= Count_Range'Last and
496 Config_Matches (PLLs (P));
497 if Success then
498 PLL := P;
499 PLLs (PLL).Use_Count := PLLs (PLL).Use_Count + 1;
500 return;
501 end if;
502 end loop;
503
504 -- try to find free PLL
505 for P in DPLLs loop
506 if PLLs (P).Use_Count = 0 then
507 PLL := P;
508 On (PLL, Port_Cfg, Success);
509 if Success then
510 PLLs (PLL) :=
511 (Use_Count => 1,
512 Used_For_DP => Port_Cfg.Display = DP,
513 Link_Rate => Port_Cfg.DP.Bandwidth,
514 Mode => Port_Cfg.Mode);
515 end if;
516 return;
517 end if;
518 end loop;
519
520 PLL := Invalid;
521 end Alloc_Configurable;
522
523 procedure Alloc
524 (Port_Cfg : in Port_Config;
525 PLL : out T;
526 Success : out Boolean)
527 is
528 begin
529 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
530
531 if Port_Cfg.Port = DIGI_A then
532 PLL := Invalid;
533 Success := True;
534 else
535 Alloc_Configurable (Port_Cfg, PLL, Success);
536 end if;
537 end Alloc;
538
539 procedure Free (PLL : T)
540 is
541 begin
542 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
543
544 if PLL in DPLLs then
545 if PLLs (PLL).Use_Count /= 0 then
546 PLLs (PLL).Use_Count := PLLs (PLL).Use_Count - 1;
547 if PLLs (PLL).Use_Count = 0 then
548 Off (PLL);
549 end if;
550 end if;
551 end if;
552 end Free;
553
554 procedure All_Off
555 is
556 begin
557 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
558
559 for PLL in DPLLs loop
560 Off (PLL);
561 end loop;
562 end All_Off;
563
564 function Register_Value (PLL : T) return Word32
565 is
566 begin
567 return (if PLL = DPLL_B then 1 else 0);
568 end Register_Value;
569
570end HW.GFX.GMA.PLLs;