gma skl: Add I_boost configuration
Hardcoded to 1 since we don't support Skylake-Y (ULX).
Change-Id: I22fa056531cac18828c867f9c9f5745ec424d38c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20168
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb b/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb
index 091f36d..0fc4ad9 100644
--- a/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb
+++ b/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb
@@ -95,6 +95,18 @@
HW.GFX.DP_Bandwidth_2_7 => PORT_CLK_SEL_LCPLL1350,
HW.GFX.DP_Bandwidth_5_4 => PORT_CLK_SEL_LCPLL2700);
+ DISPIO_CR_TX_BLNC_LEG_DISBL_MASK : constant := 16#1f# * 2 ** 23;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_4_SHIFT : constant := 20;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_4_MASK : constant := 16#07# * 2 ** 20;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_3_SHIFT : constant := 17;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_3_MASK : constant := 16#07# * 2 ** 17;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_2_SHIFT : constant := 14;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_2_MASK : constant := 16#07# * 2 ** 14;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_1_SHIFT : constant := 11;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_1_MASK : constant := 16#07# * 2 ** 11;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_0_SHIFT : constant := 8;
+ DISPIO_CR_TX_BLNC_LEG_SCTL_0_MASK : constant := 16#07# * 2 ** 8;
+
type DDI_Buf_Trans_Regs_Array
is array (Buf_Trans_Range) of Registers.Registers_Index;
@@ -298,6 +310,7 @@
procedure Initialize
is
+ Iboost_Value : constant Word32 := 1;
begin
if Config.Has_DDI_Buffer_Trans then
for Port in Digital_Port range DIGI_A .. Config.Last_Digital_Port loop
@@ -307,6 +320,23 @@
Program_Buffer_Translations (DIGI_E);
end if;
end if;
+
+ if Config.Has_Iboost_Config then
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.DISPIO_CR_TX_BMU_CR0,
+ Mask_Unset => DISPIO_CR_TX_BLNC_LEG_DISBL_MASK or
+ DISPIO_CR_TX_BLNC_LEG_SCTL_4_MASK or
+ DISPIO_CR_TX_BLNC_LEG_SCTL_3_MASK or
+ DISPIO_CR_TX_BLNC_LEG_SCTL_2_MASK or
+ DISPIO_CR_TX_BLNC_LEG_SCTL_1_MASK or
+ DISPIO_CR_TX_BLNC_LEG_SCTL_0_MASK,
+ Mask_Set =>
+ Shift_Left (Iboost_Value, DISPIO_CR_TX_BLNC_LEG_SCTL_4_SHIFT) or
+ Shift_Left (Iboost_Value, DISPIO_CR_TX_BLNC_LEG_SCTL_3_SHIFT) or
+ Shift_Left (Iboost_Value, DISPIO_CR_TX_BLNC_LEG_SCTL_2_SHIFT) or
+ Shift_Left (Iboost_Value, DISPIO_CR_TX_BLNC_LEG_SCTL_1_SHIFT) or
+ Shift_Left (Iboost_Value, DISPIO_CR_TX_BLNC_LEG_SCTL_0_SHIFT));
+ end if;
end Initialize;
----------------------------------------------------------------------------
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index ec41c40..f40054c 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -95,6 +95,7 @@
Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and
CPU /= Broxton;
Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton;
+ Has_Iboost_Config : constant Boolean := CPU >= Skylake;
Need_DP_Aux_Mutex : constant Boolean := False; -- Skylake & (PSR | GTC)
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index ef25770..f3825ea 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -346,6 +346,7 @@
PS_WIN_SZ_1_C,
PS_CTRL_1_C,
BXT_PORT_CL1CM_DW0_BC,
+ DISPIO_CR_TX_BMU_CR0,
BXT_PORT_CL1CM_DW9_BC,
BXT_PORT_CL1CM_DW10_BC,
BXT_PORT_PLL_EBB_0_B,
@@ -1109,6 +1110,9 @@
PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
+ -- Skylake I_boost configuration
+ DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
+
-- Skylake DPLL registers
DPLL1_CFGR1 => 16#06_c040# / Register_Width,
DPLL1_CFGR2 => 16#06_c044# / Register_Width,