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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000018 *
Uwe Hermannd1107642007-08-29 17:52:32 +000019 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000022 */
23
24#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000025
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000026#define MAX_REFLASH_TRIES 0x10
27
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000028/* Check one byte for odd parity */
29uint8_t oddparity(uint8_t val)
30{
31 val = (val ^ (val >> 4)) & 0xf;
32 val = (val ^ (val >> 2)) & 0x3;
33 return (val ^ (val >> 1)) & 0x1;
34}
35
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000036void toggle_ready_jedec(chipaddr dst)
Uwe Hermann51582f22007-08-23 10:20:40 +000037{
38 unsigned int i = 0;
39 uint8_t tmp1, tmp2;
40
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000041 tmp1 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000042
43 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000044 tmp2 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000045 if (tmp1 == tmp2) {
46 break;
47 }
48 tmp1 = tmp2;
49 }
50}
51
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000052void data_polling_jedec(chipaddr dst, uint8_t data)
Uwe Hermann51582f22007-08-23 10:20:40 +000053{
54 unsigned int i = 0;
55 uint8_t tmp;
56
57 data &= 0x80;
58
59 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000060 tmp = chip_readb(dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000061 if (tmp == data) {
62 break;
63 }
64 }
65}
66
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000067void unprotect_jedec(chipaddr bios)
Uwe Hermann51582f22007-08-23 10:20:40 +000068{
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000069 chip_writeb(0xAA, bios + 0x5555);
70 chip_writeb(0x55, bios + 0x2AAA);
71 chip_writeb(0x80, bios + 0x5555);
72 chip_writeb(0xAA, bios + 0x5555);
73 chip_writeb(0x55, bios + 0x2AAA);
74 chip_writeb(0x20, bios + 0x5555);
Uwe Hermann51582f22007-08-23 10:20:40 +000075
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000076 programmer_delay(200);
Uwe Hermann51582f22007-08-23 10:20:40 +000077}
78
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000079void protect_jedec(chipaddr bios)
Uwe Hermann51582f22007-08-23 10:20:40 +000080{
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000081 chip_writeb(0xAA, bios + 0x5555);
82 chip_writeb(0x55, bios + 0x2AAA);
83 chip_writeb(0xA0, bios + 0x5555);
Uwe Hermann51582f22007-08-23 10:20:40 +000084
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000085 programmer_delay(200);
Uwe Hermann51582f22007-08-23 10:20:40 +000086}
87
Ollie Lho761bf1b2004-03-20 16:46:10 +000088int probe_jedec(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000089{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000090 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000091 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +000092 uint32_t largeid1, largeid2;
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +000093 uint32_t flashcontent1, flashcontent2;
Maciej Pijankac6e11112009-06-03 14:46:22 +000094 int probe_timing_enter, probe_timing_exit;
95
96 if (flash->probe_timing > 0)
97 probe_timing_enter = probe_timing_exit = flash->probe_timing;
98 else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */
99 probe_timing_enter = probe_timing_exit = 0;
100 } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */
101 printf_debug("Chip lacks correct probe timing information, "
102 "using default 10mS/40uS\n");
103 probe_timing_enter = 10000;
104 probe_timing_exit = 40;
105 } else {
106 printf("Chip has negative value in probe_timing, failing "
107 "without chip access\n");
108 return 0;
109 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000110
Ollie Lho761bf1b2004-03-20 16:46:10 +0000111 /* Issue JEDEC Product ID Entry command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000112 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000113 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000114 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000115 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000116 chip_writeb(0x90, bios + 0x5555);
Carl-Daniel Hailfinger03d28262007-11-13 14:56:54 +0000117 /* Older chips may need up to 100 us to respond. The ATMEL 29C020
Peter Stuge8653b002008-06-24 02:09:09 +0000118 * needs 10 ms according to the data sheet.
Carl-Daniel Hailfinger03d28262007-11-13 14:56:54 +0000119 */
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000120 programmer_delay(probe_timing_enter);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000121
Ollie Lho761bf1b2004-03-20 16:46:10 +0000122 /* Read product ID */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000123 id1 = chip_readb(bios);
124 id2 = chip_readb(bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000125 largeid1 = id1;
126 largeid2 = id2;
127
128 /* Check if it is a continuation ID, this should be a while loop. */
129 if (id1 == 0x7F) {
130 largeid1 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000131 id1 = chip_readb(bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000132 largeid1 |= id1;
133 }
134 if (id2 == 0x7F) {
135 largeid2 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000136 id2 = chip_readb(bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000137 largeid2 |= id2;
138 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000139
Ollie Lho761bf1b2004-03-20 16:46:10 +0000140 /* Issue JEDEC Product ID Exit command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000141 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000142 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000143 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000144 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000145 chip_writeb(0xF0, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000146 programmer_delay(probe_timing_exit);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000147
Peter Stuge5cafc332009-01-25 23:52:45 +0000148 printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000149 if (!oddparity(id1))
150 printf_debug(", id1 parity violation");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000151
152 /* Read the product ID location again. We should now see normal flash contents. */
153 flashcontent1 = chip_readb(bios);
154 flashcontent2 = chip_readb(bios + 0x01);
155
156 /* Check if it is a continuation ID, this should be a while loop. */
157 if (flashcontent1 == 0x7F) {
158 flashcontent1 <<= 8;
159 flashcontent1 |= chip_readb(bios + 0x100);
160 }
161 if (flashcontent2 == 0x7F) {
162 flashcontent2 <<= 8;
163 flashcontent2 |= chip_readb(bios + 0x101);
164 }
165
166 if (largeid1 == flashcontent1)
167 printf_debug(", id1 is normal flash content");
168 if (largeid2 == flashcontent2)
169 printf_debug(", id2 is normal flash content");
170
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000171 printf_debug("\n");
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000172 if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000173 return 1;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000174
Ollie Lho761bf1b2004-03-20 16:46:10 +0000175 return 0;
Ollie Lho73eca802004-03-19 22:10:07 +0000176}
177
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000178int erase_sector_jedec(chipaddr bios, unsigned int page)
Ollie Lho73eca802004-03-19 22:10:07 +0000179{
Ollie Lho761bf1b2004-03-20 16:46:10 +0000180 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000181 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000182 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000183 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000184 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000185 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000186 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000187
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000188 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000189 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000190 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000191 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000192 chip_writeb(0x30, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000193 programmer_delay(10);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000194
Ollie Lho73eca802004-03-19 22:10:07 +0000195 /* wait for Toggle bit ready */
196 toggle_ready_jedec(bios);
197
Uwe Hermannffec5f32007-08-23 16:08:21 +0000198 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000199}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000200
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000201int erase_block_jedec(chipaddr bios, unsigned int block)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000202{
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000203 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000204 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000205 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000206 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000207 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000208 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000209 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000210
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000211 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000212 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000213 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000214 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000215 chip_writeb(0x50, bios + block);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000216 programmer_delay(10);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000217
218 /* wait for Toggle bit ready */
219 toggle_ready_jedec(bios);
220
Uwe Hermannffec5f32007-08-23 16:08:21 +0000221 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000222}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000223
Ollie Lho761bf1b2004-03-20 16:46:10 +0000224int erase_chip_jedec(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000225{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000226 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000227
Ollie Lho761bf1b2004-03-20 16:46:10 +0000228 /* Issue the JEDEC Chip Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000229 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000230 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000231 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000232 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000233 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000234 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000235
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000236 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000237 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000238 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000239 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000240 chip_writeb(0x10, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000241 programmer_delay(10);
Ollie Lho73eca802004-03-19 22:10:07 +0000242
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000243 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000244
Uwe Hermannffec5f32007-08-23 16:08:21 +0000245 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000246}
247
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000248int write_page_write_jedec(chipaddr bios, uint8_t *src,
249 chipaddr dst, int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000250{
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000251 int i, tried = 0, start_index = 0, ok;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000252 chipaddr d = dst;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000253 uint8_t *s = src;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000254
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000255retry:
Ollie Lho761bf1b2004-03-20 16:46:10 +0000256 /* Issue JEDEC Data Unprotect comand */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000257 chip_writeb(0xAA, bios + 0x5555);
258 chip_writeb(0x55, bios + 0x2AAA);
259 chip_writeb(0xA0, bios + 0x5555);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000260
Ollie Lho98bea8a2004-12-07 03:15:51 +0000261 /* transfer data from source to destination */
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000262 for (i = start_index; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000263 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000264 if (*src != 0xFF)
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000265 chip_writeb(*src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000266 dst++;
267 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000268 }
269
Ollie Lho761bf1b2004-03-20 16:46:10 +0000270 toggle_ready_jedec(dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000271
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000272 dst = d;
273 src = s;
274 ok = 1;
275 for (i = 0; i < page_size; i++) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000276 if (chip_readb(dst) != *src) {
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000277 ok = 0;
278 break;
279 }
280 dst++;
281 src++;
282 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000283
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000284 if (!ok && tried++ < MAX_REFLASH_TRIES) {
285 start_index = i;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000286 goto retry;
287 }
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000288 if (!ok) {
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000289 fprintf(stderr, " page 0x%lx failed!\n",
290 (d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000291 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000292 return !ok;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000293}
294
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000295int write_byte_program_jedec(chipaddr bios, uint8_t *src,
296 chipaddr dst)
Ollie Lho070647d2004-03-22 22:19:17 +0000297{
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000298 int tried = 0, ok = 1;
Ollie Lho1b8b6602004-12-08 02:10:33 +0000299
Ollie Lho98bea8a2004-12-07 03:15:51 +0000300 /* If the data is 0xFF, don't program it */
Ollie Lho070647d2004-03-22 22:19:17 +0000301 if (*src == 0xFF) {
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000302 return -1;
Ollie Lho070647d2004-03-22 22:19:17 +0000303 }
Ollie Lho98bea8a2004-12-07 03:15:51 +0000304
Ollie Lho1b8b6602004-12-08 02:10:33 +0000305retry:
Ollie Lho070647d2004-03-22 22:19:17 +0000306 /* Issue JEDEC Byte Program command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000307 chip_writeb(0xAA, bios + 0x5555);
308 chip_writeb(0x55, bios + 0x2AAA);
309 chip_writeb(0xA0, bios + 0x5555);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000310
311 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000312 chip_writeb(*src, dst);
Ollie Lho070647d2004-03-22 22:19:17 +0000313 toggle_ready_jedec(bios);
Ollie Lho8b8897a2004-03-27 00:18:15 +0000314
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000315 if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000316 goto retry;
317 }
Ollie Lho1b8b6602004-12-08 02:10:33 +0000318
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000319 if (tried >= MAX_REFLASH_TRIES)
Uwe Hermanna7e05482007-05-09 10:17:44 +0000320 ok = 0;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000321
Uwe Hermannffec5f32007-08-23 16:08:21 +0000322 return !ok;
Ollie Lho070647d2004-03-22 22:19:17 +0000323}
324
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000325int write_sector_jedec(chipaddr bios, uint8_t *src,
326 chipaddr dst, unsigned int page_size)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000327{
328 int i;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000329
330 for (i = 0; i < page_size; i++) {
Ollie Lho8b8897a2004-03-27 00:18:15 +0000331 write_byte_program_jedec(bios, src, dst);
332 dst++, src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000333 }
334
Uwe Hermannffec5f32007-08-23 16:08:21 +0000335 return 0;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000336}
337
Ollie Lho184a4042005-11-26 21:55:36 +0000338int write_jedec(struct flashchip *flash, uint8_t *buf)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000339{
340 int i;
Ollie Lho070647d2004-03-22 22:19:17 +0000341 int total_size = flash->total_size * 1024;
342 int page_size = flash->page_size;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000343 chipaddr bios = flash->virtual_memory;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000344
345 erase_chip_jedec(flash);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000346 // dumb check if erase was successful.
347 for (i = 0; i < total_size; i++) {
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000348 if (chip_readb(bios + i) != 0xff) {
Carl-Daniel Hailfinger01624f42009-05-12 15:38:55 +0000349 printf("ERASE FAILED @%d, val %02x!\n", i, chip_readb(bios + i));
Uwe Hermanna7e05482007-05-09 10:17:44 +0000350 return -1;
351 }
352 }
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000353
Uwe Hermanna502dce2007-10-17 23:55:15 +0000354 printf("Programming page: ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000355 for (i = 0; i < total_size / page_size; i++) {
356 printf("%04d at address: 0x%08x", i, i * page_size);
Ollie Lho8b8897a2004-03-27 00:18:15 +0000357 write_page_write_jedec(bios, buf + i * page_size,
358 bios + i * page_size, page_size);
Ollie Lho070647d2004-03-22 22:19:17 +0000359 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000360 }
361 printf("\n");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000362 protect_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000363
Uwe Hermannffec5f32007-08-23 16:08:21 +0000364 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000365}