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Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
Uwe Hermann48ec1b12010-08-08 17:01:18 +000020/* Driver for the NVIDIA MCP6x/MCP7x MCP6X_SPI controller.
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000021 * Based on clean room reverse engineered docs from
22 * http://www.flashrom.org/pipermail/flashrom/2009-December/001180.html
23 * created by Michael Karcher.
24 */
25
26#if defined(__i386__) || defined(__x86_64__)
27
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000028#include <stdlib.h>
29#include <ctype.h>
30#include "flash.h"
31#include "programmer.h"
32
33/* Bit positions for each pin. */
34
35#define MCP6X_SPI_CS 1
36#define MCP6X_SPI_SCK 2
37#define MCP6X_SPI_MOSI 3
38#define MCP6X_SPI_MISO 4
39#define MCP6X_SPI_REQUEST 0
40#define MCP6X_SPI_GRANT 8
41
42void *mcp6x_spibar = NULL;
43
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +000044/* Cached value of last GPIO state. */
45static uint8_t mcp_gpiostate;
46
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000047static void mcp6x_request_spibus(void)
48{
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +000049 mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530);
50 mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST;
51 mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000052
53 /* Wait until we are allowed to use the SPI bus. */
54 while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ;
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +000055
56 /* Update the cache. */
57 mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000058}
59
60static void mcp6x_release_spibus(void)
61{
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +000062 mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST);
63 mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000064}
65
66static void mcp6x_bitbang_set_cs(int val)
67{
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +000068 mcp_gpiostate &= ~(1 << MCP6X_SPI_CS);
69 mcp_gpiostate |= (val << MCP6X_SPI_CS);
70 mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000071}
72
73static void mcp6x_bitbang_set_sck(int val)
74{
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +000075 mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK);
76 mcp_gpiostate |= (val << MCP6X_SPI_SCK);
77 mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000078}
79
80static void mcp6x_bitbang_set_mosi(int val)
81{
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +000082 mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI);
83 mcp_gpiostate |= (val << MCP6X_SPI_MOSI);
84 mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000085}
86
87static int mcp6x_bitbang_get_miso(void)
88{
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +000089 mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530);
90 return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000091}
92
93static const struct bitbang_spi_master bitbang_spi_master_mcp6x = {
94 .type = BITBANG_SPI_MASTER_MCP,
95 .set_cs = mcp6x_bitbang_set_cs,
96 .set_sck = mcp6x_bitbang_set_sck,
97 .set_mosi = mcp6x_bitbang_set_mosi,
98 .get_miso = mcp6x_bitbang_get_miso,
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +000099 .request_bus = mcp6x_request_spibus,
100 .release_bus = mcp6x_release_spibus,
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000101};
102
103int mcp6x_spi_init(int want_spi)
104{
105 uint16_t status;
106 uint32_t mcp6x_spibaraddr;
107 struct pci_dev *smbusdev;
108
109 /* Look for the SMBus device (SMBus PCI class) */
110 smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
111 if (!smbusdev) {
112 if (want_spi) {
113 msg_perr("ERROR: SMBus device not found. Not enabling "
114 "SPI.\n");
115 return 1;
116 } else {
117 msg_pinfo("Odd. SMBus device not found.\n");
118 return 0;
119 }
120 }
121 msg_pdbg("Found SMBus device %04x:%04x at %02x:%02x:%01x\n",
122 smbusdev->vendor_id, smbusdev->device_id,
123 smbusdev->bus, smbusdev->dev, smbusdev->func);
124
125
126 /* Locate the BAR where the SPI interface lives. */
127 mcp6x_spibaraddr = pci_read_long(smbusdev, 0x74);
128 /* BAR size is 64k, bits 15..4 are zero, bit 3..0 declare a
129 * 32-bit non-prefetchable memory BAR.
130 */
131 mcp6x_spibaraddr &= ~0xffff;
132 msg_pdbg("MCP SPI BAR is at 0x%08x\n", mcp6x_spibaraddr);
133
134 /* Accessing a NULL pointer BAR is evil. Don't do it. */
135 if (!mcp6x_spibaraddr && want_spi) {
136 msg_perr("Error: Chipset is strapped for SPI, but MCP SPI BAR "
137 "is invalid.\n");
138 return 1;
139 } else if (!mcp6x_spibaraddr && !want_spi) {
140 msg_pdbg("MCP SPI is not used.\n");
141 return 0;
142 } else if (mcp6x_spibaraddr && !want_spi) {
143 msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"
144 " doesn't have SPI enabled.\n");
145 /* FIXME: Should we enable SPI anyway? */
146 return 0;
147 }
148 /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000149 mcp6x_spibar = physmap("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000150
151#if 0
152 /* FIXME: Run the physunmap in a shutdown function. */
153 physunmap(mcp6x_spibar, 0x544);
154#endif
155
156 status = mmio_readw(mcp6x_spibar + 0x530);
157 msg_pdbg("SPI control is 0x%04x, req=%i, gnt=%i\n",
158 status, (status >> MCP6X_SPI_REQUEST) & 0x1,
159 (status >> MCP6X_SPI_GRANT) & 0x1);
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +0000160 mcp_gpiostate = status & 0xff;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000161
Carl-Daniel Hailfinger7b61df82010-09-14 01:29:49 +0000162 /* Zero halfperiod delay. */
163 if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 0)) {
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000164 /* This should never happen. */
165 msg_perr("MCP6X bitbang SPI master init failed!\n");
166 return 1;
167 }
168
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000169 return 0;
170}
171
172#endif