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Nico Huber735b1862023-01-29 18:28:45 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
Nico Huberf5fcd742023-03-11 17:11:12 +000015#include <stdbool.h>
Nico Huber735b1862023-01-29 18:28:45 +000016#include <stdint.h>
17#include <stdlib.h>
18#include <string.h>
19
20#include "flash.h"
21#include "hwaccess_physmap.h"
22#include "programmer.h"
23#include "spi.h"
24
25#define SPI100_FIFO_SIZE 71
26
27struct spi100 {
28 uint8_t *spibar;
Nico Hubere3c305d2023-01-29 21:45:56 +000029 uint8_t *memory;
30 size_t mapped_len;
Nico Huberf5fcd742023-03-11 17:11:12 +000031 bool no_4ba_mmap;
Nico Hubere3c305d2023-01-29 21:45:56 +000032
Nico Huber735b1862023-01-29 18:28:45 +000033 unsigned int altspeed;
34};
35
36static void spi100_write8(const struct spi100 *spi100, unsigned int reg, uint8_t val)
37{
38 mmio_writeb(val, spi100->spibar + reg);
39}
40
41static void spi100_write16(const struct spi100 *spi100, unsigned int reg, uint16_t val)
42{
43 mmio_writew(val, spi100->spibar + reg);
44}
45
46static void spi100_writen(const struct spi100 *spi100, unsigned int reg, const uint8_t *data, size_t len)
47{
48 for (; len > 0; --len, ++reg, ++data)
49 mmio_writeb(*data, spi100->spibar + reg);
50}
51
52static uint8_t spi100_read8(const struct spi100 *spi100, unsigned int reg)
53{
54 return mmio_readb(spi100->spibar + reg);
55}
56
57static uint16_t spi100_read16(const struct spi100 *spi100, unsigned int reg)
58{
59 return mmio_readw(spi100->spibar + reg);
60}
61
62static uint32_t spi100_read32(const struct spi100 *spi100, unsigned int reg)
63{
64 return mmio_readl(spi100->spibar + reg);
65}
66
67static void spi100_readn(const struct spi100 *spi100, unsigned int reg, uint8_t *data, size_t len)
68{
Nico Huber07058782023-01-29 19:56:39 +000069 mmio_readn_aligned(spi100->spibar + reg, data, len, 4);
Nico Huber735b1862023-01-29 18:28:45 +000070}
71
72static int spi100_check_readwritecnt(const unsigned int writecnt, const unsigned int readcnt)
73{
74 if (writecnt < 1) {
75 msg_perr("ERROR: SPI controller needs to send at least 1 byte.\n");
76 return SPI_INVALID_LENGTH;
77 }
78
79 if (writecnt - 1 > SPI100_FIFO_SIZE) {
80 msg_perr("ERROR: SPI controller can not send %u bytes, it is limited to %u bytes.\n",
81 writecnt, SPI100_FIFO_SIZE + 1);
82 return SPI_INVALID_LENGTH;
83 }
84
85 const unsigned int maxreadcnt = SPI100_FIFO_SIZE - (writecnt - 1);
86 if (readcnt > maxreadcnt) {
87 msg_perr("ERROR: SPI controller can not receive %u bytes for this command,\n"
88 "it is limited to %u bytes write+read count.\n",
89 readcnt, SPI100_FIFO_SIZE + 1);
90 return SPI_INVALID_LENGTH;
91 }
92 return 0;
93}
94
95static int spi100_send_command(const struct flashctx *const flash,
96 const unsigned int writecnt, const unsigned int readcnt,
97 const unsigned char *const writearr, unsigned char *const readarr)
98{
99 const struct spi100 *const spi100 = flash->mst->spi.data;
100
101 int ret = spi100_check_readwritecnt(writecnt, readcnt);
102 if (ret)
103 return ret;
104
105 spi100_write8(spi100, 0x45, writearr[0]); /* First "command" byte is sent separately. */
106 spi100_write8(spi100, 0x48, writecnt - 1);
107 spi100_write8(spi100, 0x4b, readcnt);
108 if (writecnt > 1)
109 spi100_writen(spi100, 0x80, &writearr[1], writecnt - 1);
110
Nico Huberd2472e52023-03-12 00:44:15 +0000111 /* Check if the command/address is allowed */
112 const uint32_t spi_cntrl0 = spi100_read32(spi100, 0x00);
113 if (spi_cntrl0 & (1 << 21)) {
114 msg_perr("ERROR: Illegal access for opcode 0x%02x!", writearr[0]);
115 return SPI_INVALID_OPCODE;
116 } else {
117 msg_pspew("%s: executing opcode 0x%02x.\n", __func__, writearr[0]);
118 }
119
Nico Huber735b1862023-01-29 18:28:45 +0000120 /* Trigger command */
121 spi100_write8(spi100, 0x47, BIT(7));
122
123 /* Wait for completion */
124 int timeout_us = 10*1000*1000;
125 uint32_t spistatus;
126 while (((spistatus = spi100_read32(spi100, 0x4c)) & BIT(31)) && timeout_us--)
127 programmer_delay(1);
128 if (spistatus & BIT(31)) {
129 msg_perr("ERROR: SPI transfer timed out (0x%08x)!\n", spistatus);
130 return SPI_PROGRAMMER_ERROR;
131 }
132 msg_pspew("%s: spistatus: 0x%08x\n", __func__, spistatus);
133
134 if (readcnt)
135 spi100_readn(spi100, 0x80 + writecnt - 1, readarr, readcnt);
136
137 return 0;
138}
139
Nico Hubere3c305d2023-01-29 21:45:56 +0000140static int spi100_read(struct flashctx *const flash, uint8_t *buf, unsigned int start, unsigned int len)
141{
142 const struct spi100 *const spi100 = flash->mst->spi.data;
Nico Huberc3b02dc2023-08-12 01:13:45 +0200143 const chipsize_t chip_size = flashprog_flash_getsize(flash);
Nico Huberf5fcd742023-03-11 17:11:12 +0000144
145 /* Don't consider memory mapping at all
146 if 4BA chips are not mapped as expected. */
147 if (chip_size > 16*MiB && spi100->no_4ba_mmap)
148 return default_spi_read(flash, buf, start, len);
Nico Hubere3c305d2023-01-29 21:45:56 +0000149
Nico Huber2d614d62023-03-11 01:06:15 +0100150 /* Where in the flash does the memory mapped part start?
151 Can be negative if the mapping is bigger than the chip. */
Nico Huberf5fcd742023-03-11 17:11:12 +0000152 const long long mapped_start = chip_size - spi100->mapped_len;
Nico Huber2d614d62023-03-11 01:06:15 +0100153
154 /* Use SPI100 engine for data outside the memory-mapped range. */
155 if ((long long)start < mapped_start) {
156 const chipsize_t unmapped_len = MIN(len, mapped_start - start);
Nico Hubere3c305d2023-01-29 21:45:56 +0000157 const int ret = default_spi_read(flash, buf, start, unmapped_len);
158 if (ret)
159 return ret;
160 start += unmapped_len;
161 buf += unmapped_len;
162 len -= unmapped_len;
163 }
164
Nico Huber2d614d62023-03-11 01:06:15 +0100165 /* Translate `start` to memory-mapped offset. */
166 start -= mapped_start;
167
Nico Hubere3c305d2023-01-29 21:45:56 +0000168 mmio_readn_aligned(spi100->memory + start, buf, len, 8);
169
170 return 0;
171}
172
Nico Huber735b1862023-01-29 18:28:45 +0000173static int spi100_shutdown(void *data)
174{
175 struct spi100 *const spi100 = data;
176
177 const uint16_t speed_cfg = spi100_read16(spi100, 0x22);
178 spi100_write16(spi100, 0x22, (speed_cfg & ~0xf0) | spi100->altspeed << 4);
179
180 free(spi100);
181 return 0;
182}
183
184static struct spi_master spi100_master = {
Nico Huberf5fcd742023-03-11 17:11:12 +0000185 .features = SPI_MASTER_4BA | SPI_MASTER_NO_4BA_MODES,
Nico Huber735b1862023-01-29 18:28:45 +0000186 .max_data_read = SPI100_FIFO_SIZE - 4, /* Account for up to 4 address bytes. */
187 .max_data_write = SPI100_FIFO_SIZE - 4,
188 .command = spi100_send_command,
189 .multicommand = default_spi_send_multicommand,
Nico Hubere3c305d2023-01-29 21:45:56 +0000190 .read = spi100_read,
Nico Huber735b1862023-01-29 18:28:45 +0000191 .write_256 = default_spi_write_256,
192 .probe_opcode = default_spi_probe_opcode,
193 .shutdown = spi100_shutdown,
194};
195
196const char *const spimodes[] = {
197 "Normal read (up to 33MHz)",
198 "Reserved",
199 "Dual IO (1-1-2)",
200 "Quad IO (1-1-4)",
201 "Dual IO (1-2-2)",
202 "Quad IO (1-1-4)",
203 "Normal read (up to 66MHz)",
204 "Fast Read",
205};
206
207const struct {
208 unsigned int khz;
209 const char *speed;
210} spispeeds[] = {
211 { 66666, "66.66 MHz" },
212 { 33333, "33.33 MHz" },
213 { 22222, "22.22 MHz" },
214 { 16666, "16.66 MHz" },
215 { 100000, "100 MHz" },
216 { 800, "800 kHz" },
217 { 0, "Reserved" },
218 { 0, "Reserved" },
219};
220
221static void spi100_print(const struct spi100 *const spi100)
222{
223 const uint32_t spi_cntrl0 = spi100_read32(spi100, 0x00);
224 msg_pdbg("(0x%08" PRIx32 ") ", spi_cntrl0);
225 msg_pdbg("SpiArbEnable=%u, ", spi_cntrl0 >> 19 & 1);
226 msg_pdbg("IllegalAccess=%u, ", spi_cntrl0 >> 21 & 1);
227 msg_pdbg("SpiAccessMacRomEn=%u, ", spi_cntrl0 >> 22 & 1);
228 msg_pdbg("SpiHostAccessRomEn=%u,\n", spi_cntrl0 >> 23 & 1);
229 msg_pdbg(" ");
230 msg_pdbg("ArbWaitCount=%u, ", spi_cntrl0 >> 24 & 7);
231 msg_pdbg("SpiBridgeDisable=%u, ", spi_cntrl0 >> 27 & 1);
232 msg_pdbg("SpiClkGate=%u,\n", spi_cntrl0 >> 28 & 1);
233 msg_pdbg(" ");
234 msg_pdbg("SpiReadMode=%s, ", spimodes[(spi_cntrl0 >> 28 & 6) | (spi_cntrl0 >> 18 & 1)]);
235 msg_pdbg("SpiBusy=%u\n", spi_cntrl0 >> 31 & 1);
236
237 const uint8_t alt_spi_cs = spi100_read8(spi100, 0x1d);
238 msg_pdbg("Using SPI_CS%u\n", alt_spi_cs & 0x3);
239
240 const uint16_t speed_cfg = spi100_read16(spi100, 0x22);
241 msg_pdbg("NormSpeed: %s\n", spispeeds[speed_cfg >> 12 & 0xf].speed);
242 msg_pdbg("FastSpeed: %s\n", spispeeds[speed_cfg >> 8 & 0xf].speed);
243 msg_pdbg("AltSpeed: %s\n", spispeeds[speed_cfg >> 4 & 0xf].speed);
244 msg_pdbg("TpmSpeed: %s\n", spispeeds[speed_cfg >> 0 & 0xf].speed);
245}
246
Nico Huberf5fcd742023-03-11 17:11:12 +0000247static void spi100_check_4ba(struct spi100 *const spi100)
248{
249 const uint16_t rom2_addr_override = spi100_read16(spi100, 0x30);
250 const uint32_t addr32_ctrl0 = spi100_read32(spi100, 0x50);
251 const uint32_t addr32_ctrl3 = spi100_read32(spi100, 0x5c);
252
253 spi100->no_4ba_mmap = false;
254
255 /* Most bits are undocumented ("reserved"), so we play safe. */
256 if (rom2_addr_override != 0x14c0) {
257 msg_pdbg("ROM2 address override *not* in default configuration.\n");
258 spi100->no_4ba_mmap = true;
259 }
260
261 /* Check if the controller would use 4-byte addresses by itself. */
262 if (addr32_ctrl0 & 1) {
263 msg_pdbg("Memory-mapped access uses 32-bit addresses.\n");
264 } else {
265 msg_pdbg("Memory-mapped access uses 24-bit addresses.\n");
266 spi100->no_4ba_mmap = true;
267 }
268
269 /* Another override (xor'ed) for the most-significant address bits. */
270 if (addr32_ctrl3 & 0xff) {
271 msg_pdbg("SPI ROM page bits set: 0x%02x\n", addr32_ctrl3 & 0xff);
272 spi100->no_4ba_mmap = true;
273 }
274}
275
Nico Huber735b1862023-01-29 18:28:45 +0000276static void spi100_set_altspeed(struct spi100 *const spi100)
277{
278 const uint16_t speed_cfg = spi100_read16(spi100, 0x22);
279 const unsigned int normspeed = speed_cfg >> 12 & 0xf;
280 spi100->altspeed = speed_cfg >> 4 & 0xf;
281
282 /* Set SPI speed to 33MHz but not higher than `normal read` speed */
283 unsigned int altspeed;
284 if (spispeeds[normspeed].khz != 0 && spispeeds[normspeed].khz < 33333)
285 altspeed = normspeed;
286 else
287 altspeed = 1;
288
289 if (altspeed != spi100->altspeed) {
290 msg_pinfo("Setting SPI speed to %s.\n", spispeeds[altspeed].speed);
291 spi100_write16(spi100, 0x22, (speed_cfg & ~0xf0) | altspeed << 4);
292 }
293}
294
Nico Hubere3c305d2023-01-29 21:45:56 +0000295int amd_spi100_probe(void *const spibar, void *const memory_mapping, const size_t mapped_len)
Nico Huber735b1862023-01-29 18:28:45 +0000296{
297 struct spi100 *const spi100 = malloc(sizeof(*spi100));
298 if (!spi100) {
299 msg_perr("Out of memory!\n");
300 return ERROR_FATAL;
301 }
302 spi100->spibar = spibar;
Nico Hubere3c305d2023-01-29 21:45:56 +0000303 spi100->memory = memory_mapping;
304 spi100->mapped_len = mapped_len;
Nico Huber735b1862023-01-29 18:28:45 +0000305
306 spi100_print(spi100);
307
308 spi100_set_altspeed(spi100);
309
Nico Huberf5fcd742023-03-11 17:11:12 +0000310 spi100_check_4ba(spi100);
311
Nico Huber735b1862023-01-29 18:28:45 +0000312 return register_spi_master(&spi100_master, spi100);
313}