amd_spi100: Revise 4BA support
With current SoCs, a flash bigger than 16MiB can't be fully
memory mapped. Also, the memory mapping doesn't necessarily
show us the expected window of the flash.
So, we consider a memory-mapped read only if we know that
the SPI controller
* sends 32-bit addresses, and
* doesn't remap any address bits.
Moreover, we disable support for 4BA mode changes, as we
currently don't reset the chip state and don't know if the
controller feels in charge of these.
Sending native 4BA commands, however, shouldn't be a problem,
so enable these.
Change-Id: I899a89067774334fe15b05bf0b7f2baed5068353
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
1 file changed