Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Carl-Daniel Hailfinger |
| 5 | * Copyright (C) 2010 Idwer Vollering |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* |
Bill Paul | bf8ea49 | 2014-03-17 22:07:29 +0000 | [diff] [blame] | 18 | * Datasheets: |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 19 | * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual |
| 20 | * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx |
Bill Paul | bf8ea49 | 2014-03-17 22:07:29 +0000 | [diff] [blame] | 21 | * http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x-family-gbe-controllers-software-dev-manual.html |
| 22 | * |
| 23 | * PCIe GbE Controllers Open Source Software Developer's Manual |
| 24 | * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe-controllers-open-source-manual.html |
| 25 | * |
| 26 | * Intel 82574 Gigabit Ethernet Controller Family Datasheet |
| 27 | * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-controller-datasheet.html |
Ed Swierk | 33180df | 2014-12-05 22:56:13 +0000 | [diff] [blame] | 28 | * |
| 29 | * Intel 82599 10 GbE Controller Datasheet (331520) |
| 30 | * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82599-10-gbe-controller-datasheet.pdf |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 31 | */ |
| 32 | |
| 33 | #include <stdlib.h> |
Stefan Tauner | 6745d6f | 2012-08-26 21:50:36 +0000 | [diff] [blame] | 34 | #include <unistd.h> |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 35 | #include "flash.h" |
| 36 | #include "programmer.h" |
Patrick Georgi | 32508eb | 2012-07-20 20:35:14 +0000 | [diff] [blame] | 37 | #include "hwaccess.h" |
Thomas Heijligen | d96c97c | 2021-11-02 21:03:00 +0100 | [diff] [blame^] | 38 | #include "platform/pci.h" |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 39 | |
| 40 | #define PCI_VENDOR_ID_INTEL 0x8086 |
Stefan Tauner | 6745d6f | 2012-08-26 21:50:36 +0000 | [diff] [blame] | 41 | #define MEMMAP_SIZE getpagesize() |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 42 | |
Stefan Tauner | 8ee180d | 2012-02-27 19:44:16 +0000 | [diff] [blame] | 43 | /* EEPROM/Flash Control & Data Register */ |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 44 | #define EECD 0x10 |
Stefan Tauner | 8ee180d | 2012-02-27 19:44:16 +0000 | [diff] [blame] | 45 | /* Flash Access Register */ |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 46 | #define FLA 0x1c |
| 47 | |
| 48 | /* |
| 49 | * Register bits of EECD. |
Stefan Tauner | 8ee180d | 2012-02-27 19:44:16 +0000 | [diff] [blame] | 50 | * Table 13-6 |
| 51 | * |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 52 | * Bit 04, 05: FWE (Flash Write Enable Control) |
Ed Swierk | 33180df | 2014-12-05 22:56:13 +0000 | [diff] [blame] | 53 | * 00b = not allowed (on some cards this sends an erase command if bit 31 (FL_ER) of FLA is set) |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 54 | * 01b = flash writes disabled |
| 55 | * 10b = flash writes enabled |
| 56 | * 11b = not allowed |
| 57 | */ |
| 58 | #define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */ |
| 59 | #define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */ |
| 60 | |
Stefan Tauner | 8ee180d | 2012-02-27 19:44:16 +0000 | [diff] [blame] | 61 | /* Flash Access register bits |
| 62 | * Table 13-9 |
| 63 | */ |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 64 | #define FL_SCK 0 |
| 65 | #define FL_CS 1 |
| 66 | #define FL_SI 2 |
| 67 | #define FL_SO 3 |
| 68 | #define FL_REQ 4 |
| 69 | #define FL_GNT 5 |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 70 | #define FL_LOCKED 6 |
| 71 | #define FL_ABORT 7 |
| 72 | #define FL_CLR_ERR 8 |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 73 | /* Currently unused */ |
| 74 | // #define FL_BUSY 30 |
| 75 | // #define FL_ER 31 |
| 76 | |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 77 | #define BIT(x) (1<<(x)) |
| 78 | |
Jacob Garber | afc3ad6 | 2019-06-24 16:05:28 -0600 | [diff] [blame] | 79 | static uint8_t *nicintel_spibar; |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 80 | |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 81 | static const struct dev_entry nics_intel_spi[] = { |
Idwer Vollering | bdc4827 | 2010-10-05 11:16:14 +0000 | [diff] [blame] | 82 | {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"}, |
Stefan Tauner | 4b90e6b | 2011-05-18 01:31:24 +0000 | [diff] [blame] | 83 | {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"}, |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 84 | {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"}, |
Idwer Vollering | bdc4827 | 2010-10-05 11:16:14 +0000 | [diff] [blame] | 85 | {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"}, |
Bill Paul | bf8ea49 | 2014-03-17 22:07:29 +0000 | [diff] [blame] | 86 | {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"}, |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 87 | |
Ed Swierk | 33180df | 2014-12-05 22:56:13 +0000 | [diff] [blame] | 88 | {PCI_VENDOR_ID_INTEL, 0x10d8, NT, "Intel", "82599 10 Gigabit Unprogrammed Network Controller"}, |
| 89 | {PCI_VENDOR_ID_INTEL, 0x10f7, NT, "Intel", "82599 10 Gigabit KX4 Dual Port Network Controller"}, |
| 90 | {PCI_VENDOR_ID_INTEL, 0x10f8, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller"}, |
| 91 | {PCI_VENDOR_ID_INTEL, 0x10f9, NT, "Intel", "82599 10 Gigabit CX4 Dual Port Network Controller"}, |
| 92 | {PCI_VENDOR_ID_INTEL, 0x10fb, NT, "Intel", "82599 10-Gigabit SFI/SFP+ Network Controller"}, |
| 93 | {PCI_VENDOR_ID_INTEL, 0x10fc, OK, "Intel", "82599 10 Gigabit XAUI/BX4 Dual Port Network Controller"}, |
| 94 | {PCI_VENDOR_ID_INTEL, 0x1517, NT, "Intel", "82599 10 Gigabit KR Network Controller"}, |
| 95 | {PCI_VENDOR_ID_INTEL, 0x151c, NT, "Intel", "82599 10 Gigabit TN Network Controller"}, |
| 96 | {PCI_VENDOR_ID_INTEL, 0x1529, NT, "Intel", "82599 10 Gigabit Dual Port Network Controller with FCoE"}, |
| 97 | {PCI_VENDOR_ID_INTEL, 0x152a, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller with FCoE"}, |
| 98 | {PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit SFI Network Controller"}, |
| 99 | |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 100 | {PCI_VENDOR_ID_INTEL, 0x1531, OK, "Intel", "I210 Gigabit Network Connection Unprogrammed"}, |
| 101 | {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"}, |
| 102 | {PCI_VENDOR_ID_INTEL, 0x1533, NT, "Intel", "I210 Gigabit Network Connection"}, |
| 103 | {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"}, |
| 104 | {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"}, |
| 105 | {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, |
| 106 | {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, |
| 107 | |
Carl-Daniel Hailfinger | 1c6d2ff | 2012-08-27 00:44:42 +0000 | [diff] [blame] | 108 | {0}, |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | static void nicintel_request_spibus(void) |
| 112 | { |
| 113 | uint32_t tmp; |
| 114 | |
| 115 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 116 | tmp |= BIT(FL_REQ); |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 117 | pci_mmio_writel(tmp, nicintel_spibar + FLA); |
| 118 | |
| 119 | /* Wait until we are allowed to use the SPI bus. */ |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 120 | while (!(pci_mmio_readl(nicintel_spibar + FLA) & BIT(FL_GNT))) ; |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | static void nicintel_release_spibus(void) |
| 124 | { |
| 125 | uint32_t tmp; |
| 126 | |
| 127 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 128 | tmp &= ~BIT(FL_REQ); |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 129 | pci_mmio_writel(tmp, nicintel_spibar + FLA); |
| 130 | } |
| 131 | |
| 132 | static void nicintel_bitbang_set_cs(int val) |
| 133 | { |
| 134 | uint32_t tmp; |
| 135 | |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 136 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 137 | tmp &= ~BIT(FL_CS); |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 138 | tmp |= (val << FL_CS); |
| 139 | pci_mmio_writel(tmp, nicintel_spibar + FLA); |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | static void nicintel_bitbang_set_sck(int val) |
| 143 | { |
| 144 | uint32_t tmp; |
| 145 | |
| 146 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 147 | tmp &= ~BIT(FL_SCK); |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 148 | tmp |= (val << FL_SCK); |
| 149 | pci_mmio_writel(tmp, nicintel_spibar + FLA); |
| 150 | } |
| 151 | |
| 152 | static void nicintel_bitbang_set_mosi(int val) |
| 153 | { |
| 154 | uint32_t tmp; |
| 155 | |
| 156 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 157 | tmp &= ~BIT(FL_SI); |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 158 | tmp |= (val << FL_SI); |
| 159 | pci_mmio_writel(tmp, nicintel_spibar + FLA); |
| 160 | } |
| 161 | |
Angel Pons | f0c03fb | 2021-06-21 13:01:45 +0200 | [diff] [blame] | 162 | static void nicintel_bitbang_set_sck_set_mosi(int sck, int mosi) |
| 163 | { |
| 164 | uint32_t tmp; |
| 165 | |
| 166 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
| 167 | tmp &= ~BIT(FL_SCK); |
| 168 | tmp &= ~BIT(FL_SI); |
| 169 | tmp |= (sck << FL_SCK); |
| 170 | tmp |= (mosi << FL_SI); |
| 171 | pci_mmio_writel(tmp, nicintel_spibar + FLA); |
| 172 | } |
| 173 | |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 174 | static int nicintel_bitbang_get_miso(void) |
| 175 | { |
| 176 | uint32_t tmp; |
| 177 | |
| 178 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
| 179 | tmp = (tmp >> FL_SO) & 0x1; |
| 180 | return tmp; |
| 181 | } |
| 182 | |
Angel Pons | f0c03fb | 2021-06-21 13:01:45 +0200 | [diff] [blame] | 183 | static int nicintel_bitbang_set_sck_get_miso(int sck) |
| 184 | { |
| 185 | uint32_t tmp; |
| 186 | |
| 187 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
| 188 | tmp &= ~BIT(FL_SCK); |
| 189 | tmp |= (sck << FL_SCK); |
| 190 | pci_mmio_writel(tmp, nicintel_spibar + FLA); |
| 191 | return (tmp >> FL_SO) & 0x1; |
| 192 | } |
| 193 | |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 194 | static const struct bitbang_spi_master bitbang_spi_master_nicintel = { |
Thomas Heijligen | 43040f2 | 2022-06-23 14:38:35 +0200 | [diff] [blame] | 195 | .set_cs = nicintel_bitbang_set_cs, |
| 196 | .set_sck = nicintel_bitbang_set_sck, |
| 197 | .set_mosi = nicintel_bitbang_set_mosi, |
| 198 | .set_sck_set_mosi = nicintel_bitbang_set_sck_set_mosi, |
| 199 | .set_sck_get_miso = nicintel_bitbang_set_sck_get_miso, |
| 200 | .get_miso = nicintel_bitbang_get_miso, |
| 201 | .request_bus = nicintel_request_spibus, |
| 202 | .release_bus = nicintel_release_spibus, |
| 203 | .half_period = 1, |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 204 | }; |
| 205 | |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 206 | static int nicintel_spi_shutdown(void *data) |
| 207 | { |
| 208 | uint32_t tmp; |
| 209 | |
Stefan Tauner | 7fb5aa0 | 2013-08-14 15:48:44 +0000 | [diff] [blame] | 210 | /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */ |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 211 | tmp = pci_mmio_readl(nicintel_spibar + EECD); |
| 212 | tmp &= ~FLASH_WRITES_ENABLED; |
| 213 | tmp |= FLASH_WRITES_DISABLED; |
| 214 | pci_mmio_writel(tmp, nicintel_spibar + EECD); |
| 215 | |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 216 | return 0; |
| 217 | } |
| 218 | |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 219 | static int nicintel_spi_82599_enable_flash(void) |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 220 | { |
| 221 | uint32_t tmp; |
| 222 | |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 223 | /* Automatic restore of EECD on shutdown is not possible because EECD |
| 224 | * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, |
| 225 | * but other bits with side effects as well. Those other bits must be |
| 226 | * left untouched. |
| 227 | */ |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 228 | tmp = pci_mmio_readl(nicintel_spibar + EECD); |
| 229 | tmp &= ~FLASH_WRITES_DISABLED; |
| 230 | tmp |= FLASH_WRITES_ENABLED; |
| 231 | pci_mmio_writel(tmp, nicintel_spibar + EECD); |
| 232 | |
Stefan Tauner | 8ee180d | 2012-02-27 19:44:16 +0000 | [diff] [blame] | 233 | /* test if FWE is really set to allow writes */ |
| 234 | tmp = pci_mmio_readl(nicintel_spibar + EECD); |
| 235 | if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) { |
| 236 | msg_perr("Enabling flash write access failed.\n"); |
| 237 | return 1; |
| 238 | } |
| 239 | |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 240 | if (register_shutdown(nicintel_spi_shutdown, NULL)) |
| 241 | return 1; |
| 242 | |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 243 | return 0; |
| 244 | } |
| 245 | |
Richard Hughes | 93e1625 | 2018-12-19 11:54:47 +0000 | [diff] [blame] | 246 | static int nicintel_spi_i210_enable_flash(void) |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 247 | { |
| 248 | uint32_t tmp; |
| 249 | |
| 250 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 251 | if (tmp & BIT(FL_LOCKED)) { |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 252 | msg_perr("Flash is in Secure Mode. Abort.\n"); |
| 253 | return 1; |
| 254 | } |
| 255 | |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 256 | if (!(tmp & BIT(FL_ABORT))) |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 257 | return 0; |
| 258 | |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 259 | tmp |= BIT(FL_CLR_ERR); |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 260 | pci_mmio_writel(tmp, nicintel_spibar + FLA); |
| 261 | tmp = pci_mmio_readl(nicintel_spibar + FLA); |
Ricardo Ribalda Delgado | 75a2a79 | 2017-03-23 23:38:04 +0100 | [diff] [blame] | 262 | if (!(tmp & BIT(FL_ABORT))) { |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 263 | msg_perr("Unable to clear Flash Access Error. Abort\n"); |
| 264 | return 1; |
| 265 | } |
| 266 | |
| 267 | return 0; |
| 268 | } |
| 269 | |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 270 | static int nicintel_spi_init(void) |
Ricardo Ribalda Delgado | 26d33d2 | 2017-03-22 14:30:52 +0100 | [diff] [blame] | 271 | { |
| 272 | struct pci_dev *dev = NULL; |
| 273 | |
| 274 | if (rget_io_perms()) |
| 275 | return 1; |
| 276 | |
| 277 | dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0); |
| 278 | if (!dev) |
| 279 | return 1; |
| 280 | |
| 281 | uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); |
| 282 | if (!io_base_addr) |
| 283 | return 1; |
| 284 | |
| 285 | if ((dev->device_id & 0xfff0) == 0x1530) { |
| 286 | nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000, |
| 287 | MEMMAP_SIZE); |
| 288 | if (!nicintel_spibar || nicintel_spi_i210_enable_flash()) |
| 289 | return 1; |
| 290 | } else if (dev->device_id < 0x10d8) { |
| 291 | nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, |
| 292 | MEMMAP_SIZE); |
| 293 | if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) |
| 294 | return 1; |
| 295 | } else { |
| 296 | nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, |
| 297 | MEMMAP_SIZE); |
| 298 | if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) |
| 299 | return 1; |
| 300 | } |
| 301 | |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 302 | if (register_spi_bitbang_master(&bitbang_spi_master_nicintel)) |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 303 | return 1; |
| 304 | |
Idwer Vollering | 004f4b7 | 2010-09-03 18:21:21 +0000 | [diff] [blame] | 305 | return 0; |
| 306 | } |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 307 | |
| 308 | const struct programmer_entry programmer_nicintel_spi = { |
| 309 | .name = "nicintel_spi", |
| 310 | .type = PCI, |
| 311 | .devs.dev = nics_intel_spi, |
| 312 | .init = nicintel_spi_init, |
| 313 | .map_flash_region = fallback_map, |
| 314 | .unmap_flash_region = fallback_unmap, |
| 315 | .delay = internal_delay, |
| 316 | }; |