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Idwer Vollering004f4b72010-09-03 18:21:21 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Carl-Daniel Hailfinger
5 * Copyright (C) 2010 Idwer Vollering
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Datasheet:
23 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
24 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
25 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
26 */
27
28#include <stdlib.h>
Stefan Tauner6745d6f2012-08-26 21:50:36 +000029#include <unistd.h>
Idwer Vollering004f4b72010-09-03 18:21:21 +000030#include "flash.h"
31#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000032#include "hwaccess.h"
Idwer Vollering004f4b72010-09-03 18:21:21 +000033
34#define PCI_VENDOR_ID_INTEL 0x8086
Stefan Tauner6745d6f2012-08-26 21:50:36 +000035#define MEMMAP_SIZE getpagesize()
Idwer Vollering004f4b72010-09-03 18:21:21 +000036
Stefan Tauner8ee180d2012-02-27 19:44:16 +000037/* EEPROM/Flash Control & Data Register */
Idwer Vollering004f4b72010-09-03 18:21:21 +000038#define EECD 0x10
Stefan Tauner8ee180d2012-02-27 19:44:16 +000039/* Flash Access Register */
Idwer Vollering004f4b72010-09-03 18:21:21 +000040#define FLA 0x1c
41
42/*
43 * Register bits of EECD.
Stefan Tauner8ee180d2012-02-27 19:44:16 +000044 * Table 13-6
45 *
Idwer Vollering004f4b72010-09-03 18:21:21 +000046 * Bit 04, 05: FWE (Flash Write Enable Control)
47 * 00b = not allowed
48 * 01b = flash writes disabled
49 * 10b = flash writes enabled
50 * 11b = not allowed
51 */
52#define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
53#define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
54
Stefan Tauner8ee180d2012-02-27 19:44:16 +000055/* Flash Access register bits
56 * Table 13-9
57 */
Idwer Vollering004f4b72010-09-03 18:21:21 +000058#define FL_SCK 0
59#define FL_CS 1
60#define FL_SI 2
61#define FL_SO 3
62#define FL_REQ 4
63#define FL_GNT 5
64/* Currently unused */
65// #define FL_BUSY 30
66// #define FL_ER 31
67
68uint8_t *nicintel_spibar;
69
70const struct pcidev_status nics_intel_spi[] = {
Idwer Volleringbdc48272010-10-05 11:16:14 +000071 {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"},
Stefan Tauner4b90e6b2011-05-18 01:31:24 +000072 {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"},
Idwer Vollering004f4b72010-09-03 18:21:21 +000073 {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},
Idwer Volleringbdc48272010-10-05 11:16:14 +000074 {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"},
Idwer Vollering004f4b72010-09-03 18:21:21 +000075
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000076 {0},
Idwer Vollering004f4b72010-09-03 18:21:21 +000077};
78
79static void nicintel_request_spibus(void)
80{
81 uint32_t tmp;
82
83 tmp = pci_mmio_readl(nicintel_spibar + FLA);
84 tmp |= 1 << FL_REQ;
85 pci_mmio_writel(tmp, nicintel_spibar + FLA);
86
87 /* Wait until we are allowed to use the SPI bus. */
88 while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ;
89}
90
91static void nicintel_release_spibus(void)
92{
93 uint32_t tmp;
94
95 tmp = pci_mmio_readl(nicintel_spibar + FLA);
96 tmp &= ~(1 << FL_REQ);
97 pci_mmio_writel(tmp, nicintel_spibar + FLA);
98}
99
100static void nicintel_bitbang_set_cs(int val)
101{
102 uint32_t tmp;
103
Idwer Vollering004f4b72010-09-03 18:21:21 +0000104 tmp = pci_mmio_readl(nicintel_spibar + FLA);
105 tmp &= ~(1 << FL_CS);
106 tmp |= (val << FL_CS);
107 pci_mmio_writel(tmp, nicintel_spibar + FLA);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000108}
109
110static void nicintel_bitbang_set_sck(int val)
111{
112 uint32_t tmp;
113
114 tmp = pci_mmio_readl(nicintel_spibar + FLA);
115 tmp &= ~(1 << FL_SCK);
116 tmp |= (val << FL_SCK);
117 pci_mmio_writel(tmp, nicintel_spibar + FLA);
118}
119
120static void nicintel_bitbang_set_mosi(int val)
121{
122 uint32_t tmp;
123
124 tmp = pci_mmio_readl(nicintel_spibar + FLA);
125 tmp &= ~(1 << FL_SI);
126 tmp |= (val << FL_SI);
127 pci_mmio_writel(tmp, nicintel_spibar + FLA);
128}
129
130static int nicintel_bitbang_get_miso(void)
131{
132 uint32_t tmp;
133
134 tmp = pci_mmio_readl(nicintel_spibar + FLA);
135 tmp = (tmp >> FL_SO) & 0x1;
136 return tmp;
137}
138
139static const struct bitbang_spi_master bitbang_spi_master_nicintel = {
140 .type = BITBANG_SPI_MASTER_NICINTEL,
141 .set_cs = nicintel_bitbang_set_cs,
142 .set_sck = nicintel_bitbang_set_sck,
143 .set_mosi = nicintel_bitbang_set_mosi,
144 .get_miso = nicintel_bitbang_get_miso,
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000145 .request_bus = nicintel_request_spibus,
146 .release_bus = nicintel_release_spibus,
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000147 .half_period = 1,
Idwer Vollering004f4b72010-09-03 18:21:21 +0000148};
149
David Hendricks8bb20212011-06-14 01:35:36 +0000150static int nicintel_spi_shutdown(void *data)
151{
152 uint32_t tmp;
153
154 /* Disable writes manually. See the comment about EECD in
155 * nicintel_spi_init() for details.
156 */
157 tmp = pci_mmio_readl(nicintel_spibar + EECD);
158 tmp &= ~FLASH_WRITES_ENABLED;
159 tmp |= FLASH_WRITES_DISABLED;
160 pci_mmio_writel(tmp, nicintel_spibar + EECD);
161
Stefan Tauner6745d6f2012-08-26 21:50:36 +0000162 physunmap(nicintel_spibar, MEMMAP_SIZE);
David Hendricks8bb20212011-06-14 01:35:36 +0000163 pci_cleanup(pacc);
David Hendricks8bb20212011-06-14 01:35:36 +0000164
165 return 0;
166}
167
Idwer Vollering004f4b72010-09-03 18:21:21 +0000168int nicintel_spi_init(void)
169{
170 uint32_t tmp;
171
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000172 if (rget_io_perms())
173 return 1;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000174
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +0000175 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000176
177 nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash",
Stefan Tauner6745d6f2012-08-26 21:50:36 +0000178 io_base_addr, MEMMAP_SIZE);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000179 /* Automatic restore of EECD on shutdown is not possible because EECD
180 * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED,
181 * but other bits with side effects as well. Those other bits must be
182 * left untouched.
183 */
Idwer Vollering004f4b72010-09-03 18:21:21 +0000184 tmp = pci_mmio_readl(nicintel_spibar + EECD);
185 tmp &= ~FLASH_WRITES_DISABLED;
186 tmp |= FLASH_WRITES_ENABLED;
187 pci_mmio_writel(tmp, nicintel_spibar + EECD);
188
Stefan Tauner8ee180d2012-02-27 19:44:16 +0000189 /* test if FWE is really set to allow writes */
190 tmp = pci_mmio_readl(nicintel_spibar + EECD);
191 if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
192 msg_perr("Enabling flash write access failed.\n");
193 return 1;
194 }
195
David Hendricks8bb20212011-06-14 01:35:36 +0000196 if (register_shutdown(nicintel_spi_shutdown, NULL))
197 return 1;
198
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000199 if (bitbang_spi_init(&bitbang_spi_master_nicintel))
Idwer Vollering004f4b72010-09-03 18:21:21 +0000200 return 1;
201
Idwer Vollering004f4b72010-09-03 18:21:21 +0000202 return 0;
203}