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Joseph C. Lehnerc2644a32016-01-16 23:45:25 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2015 Joseph C. Lehner <joseph.c.lehner@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000015 */
16
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000017#include <string.h>
18#include <stdlib.h>
19#include "flash.h"
20#include "programmer.h"
21#include "hwaccess.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010022#include "platform/pci.h"
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000023
24#define MAX_ROM_DECODE (32 * 1024)
25#define ADDR_MASK (MAX_ROM_DECODE - 1)
26
27/*
28 * In the absence of any public docs on the PDC2026x family, this programmer was created through a mix of
29 * reverse-engineering and trial and error.
30 *
31 * The only device tested is an Ultra100 controller, but the logic for programming the other 2026x controllers
32 * is the same, so it should, in theory, work for those as well.
33 *
34 * While the tested Ultra100 controller used a 128 kB MX29F001T chip, A16 and A15 showed continuity to ground,
35 * thus limiting the the programmer on this card to 32 kB. Without other controllers to test this programmer on,
36 * this is currently a hard limit. Note that ROM files for these controllers are 16 kB only.
37 *
38 * Since flashrom does not support accessing flash chips larger than the size limit of the programmer (the
39 * tested Ultra100 uses a 128 kB MX29F001T chip), the chip size is hackishly adjusted in atapromise_limit_chip.
40 */
41
42static uint32_t io_base_addr = 0;
43static uint32_t rom_base_addr = 0;
44
45static uint8_t *atapromise_bar = NULL;
46static size_t rom_size = 0;
47
Thomas Heijligencc853d82021-05-04 15:32:17 +020048static const struct dev_entry ata_promise[] = {
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000049 {0x105a, 0x4d38, NT, "Promise", "PDC20262 (FastTrak66/Ultra66)"},
50 {0x105a, 0x0d30, NT, "Promise", "PDC20265 (FastTrak100 Lite/Ultra100)"},
51 {0x105a, 0x4d30, OK, "Promise", "PDC20267 (FastTrak100/Ultra100)"},
52 {0},
53};
54
55static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
56static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr);
57
58static const struct par_master par_master_atapromise = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020059 .chip_readb = atapromise_chip_readb,
60 .chip_readw = fallback_chip_readw,
61 .chip_readl = fallback_chip_readl,
62 .chip_readn = fallback_chip_readn,
63 .chip_writeb = atapromise_chip_writeb,
64 .chip_writew = fallback_chip_writew,
65 .chip_writel = fallback_chip_writel,
66 .chip_writen = fallback_chip_writen,
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000067};
68
Thomas Heijligencc853d82021-05-04 15:32:17 +020069static void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len)
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000070{
71 /* In case fallback_map ever returns something other than NULL. */
72 return NULL;
73}
74
75static void atapromise_limit_chip(struct flashchip *chip)
76{
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000077 unsigned int i, size;
Carl-Daniel Hailfinger1c2d23a2016-02-18 23:11:52 +000078 unsigned int usable_erasers = 0;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000079
80 size = chip->total_size * 1024;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000081
Carl-Daniel Hailfinger1c2d23a2016-02-18 23:11:52 +000082 /* Chip is small enough or already limited. */
83 if (size <= rom_size)
84 return;
85
86 /* Undefine all block_erasers that don't operate on the whole chip,
87 * and adjust the eraseblock size of those which do.
88 */
89 for (i = 0; i < NUM_ERASEFUNCTIONS; ++i) {
90 if (chip->block_erasers[i].eraseblocks[0].size != size) {
91 chip->block_erasers[i].eraseblocks[0].count = 0;
92 chip->block_erasers[i].block_erase = NULL;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000093 } else {
Carl-Daniel Hailfinger1c2d23a2016-02-18 23:11:52 +000094 chip->block_erasers[i].eraseblocks[0].size = rom_size;
95 usable_erasers++;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000096 }
97 }
98
Carl-Daniel Hailfinger1c2d23a2016-02-18 23:11:52 +000099 if (usable_erasers) {
100 chip->total_size = rom_size / 1024;
101 if (chip->page_size > rom_size)
102 chip->page_size = rom_size;
103 } else {
104 msg_pdbg("Failed to adjust size of chip \"%s\" (%d kB).\n", chip->name, chip->total_size);
105 }
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000106}
107
Thomas Heijligencc853d82021-05-04 15:32:17 +0200108static int atapromise_init(void)
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000109{
110 struct pci_dev *dev = NULL;
111
112 if (rget_io_perms())
113 return 1;
114
115 dev = pcidev_init(ata_promise, PCI_BASE_ADDRESS_4);
116 if (!dev)
117 return 1;
118
119 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4) & 0xfffe;
120 if (!io_base_addr) {
121 return 1;
122 }
123
124 /* Not exactly sure what this does, because flashing seems to work
125 * well without it. However, PTIFLASH does it, so we do it too.
126 */
127 OUTB(1, io_base_addr + 0x10);
128
129 rom_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5);
130 if (!rom_base_addr) {
131 msg_pdbg("Failed to read BAR5\n");
132 return 1;
133 }
134
135 rom_size = dev->rom_size > MAX_ROM_DECODE ? MAX_ROM_DECODE : dev->rom_size;
136 atapromise_bar = (uint8_t*)rphysmap("Promise", rom_base_addr, rom_size);
137 if (atapromise_bar == ERROR_PTR) {
138 return 1;
139 }
140
141 max_rom_decode.parallel = rom_size;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000142
143 msg_pwarn("Do not use this device as a generic programmer. It will leave anything outside\n"
144 "the first %zu kB of the flash chip in an undefined state. It works fine for the\n"
Elyes HAOUASe2c90c42018-08-18 09:04:41 +0200145 "purpose of updating the firmware of this device (padding may necessary).\n",
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000146 rom_size / 1024);
147
Anastasia Klimchukc1f2a472021-08-27 15:47:46 +1000148 return register_par_master(&par_master_atapromise, BUS_PARALLEL, NULL);
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000149}
150
151static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
152{
153 uint32_t data;
154
155 atapromise_limit_chip(flash->chip);
156 data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val;
157 OUTL(data, io_base_addr + 0x14);
158}
159
160static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr)
161{
162 atapromise_limit_chip(flash->chip);
163 return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK));
164}
165
Thomas Heijligencc853d82021-05-04 15:32:17 +0200166const struct programmer_entry programmer_atapromise = {
167 .name = "atapromise",
168 .type = PCI,
169 .devs.dev = ata_promise,
170 .init = atapromise_init,
171 .map_flash_region = atapromise_map,
172 .unmap_flash_region = fallback_unmap,
173 .delay = internal_delay,
174};