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Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef __PROGRAMMER_H__
25#define __PROGRAMMER_H__ 1
26
27enum programmer {
28#if CONFIG_INTERNAL == 1
29 PROGRAMMER_INTERNAL,
30#endif
31#if CONFIG_DUMMY == 1
32 PROGRAMMER_DUMMY,
33#endif
34#if CONFIG_NIC3COM == 1
35 PROGRAMMER_NIC3COM,
36#endif
37#if CONFIG_NICREALTEK == 1
38 PROGRAMMER_NICREALTEK,
Idwer Vollering004f4b72010-09-03 18:21:21 +000039#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000040#if CONFIG_NICNATSEMI == 1
41 PROGRAMMER_NICNATSEMI,
Idwer Vollering004f4b72010-09-03 18:21:21 +000042#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000043#if CONFIG_GFXNVIDIA == 1
44 PROGRAMMER_GFXNVIDIA,
45#endif
46#if CONFIG_DRKAISER == 1
47 PROGRAMMER_DRKAISER,
48#endif
49#if CONFIG_SATASII == 1
50 PROGRAMMER_SATASII,
51#endif
52#if CONFIG_ATAHPT == 1
53 PROGRAMMER_ATAHPT,
54#endif
55#if CONFIG_INTERNAL == 1
56#if defined(__i386__) || defined(__x86_64__)
57 PROGRAMMER_IT87SPI,
58#endif
59#endif
60#if CONFIG_FT2232_SPI == 1
61 PROGRAMMER_FT2232_SPI,
62#endif
63#if CONFIG_SERPROG == 1
64 PROGRAMMER_SERPROG,
65#endif
66#if CONFIG_BUSPIRATE_SPI == 1
67 PROGRAMMER_BUSPIRATE_SPI,
68#endif
69#if CONFIG_DEDIPROG == 1
70 PROGRAMMER_DEDIPROG,
71#endif
72#if CONFIG_RAYER_SPI == 1
73 PROGRAMMER_RAYER_SPI,
74#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +000075#if CONFIG_NICINTEL_SPI == 1
76 PROGRAMMER_NICINTEL_SPI,
77#endif
Mark Marshall90021f22010-12-03 14:48:11 +000078#if CONFIG_OGP_SPI == 1
79 PROGRAMMER_OGP_SPI,
80#endif
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000081#if CONFIG_SATAMV == 1
82 PROGRAMMER_SATAMV,
83#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000084 PROGRAMMER_INVALID /* This must always be the last entry. */
85};
86
87extern enum programmer programmer;
88
89struct programmer_entry {
90 const char *vendor;
91 const char *name;
92
93 int (*init) (void);
94 int (*shutdown) (void);
95
96 void * (*map_flash_region) (const char *descr, unsigned long phys_addr,
97 size_t len);
98 void (*unmap_flash_region) (void *virt_addr, size_t len);
99
100 void (*chip_writeb) (uint8_t val, chipaddr addr);
101 void (*chip_writew) (uint16_t val, chipaddr addr);
102 void (*chip_writel) (uint32_t val, chipaddr addr);
103 void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
104 uint8_t (*chip_readb) (const chipaddr addr);
105 uint16_t (*chip_readw) (const chipaddr addr);
106 uint32_t (*chip_readl) (const chipaddr addr);
107 void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
108 void (*delay) (int usecs);
109};
110
111extern const struct programmer_entry programmer_table[];
112
113int programmer_init(char *param);
114int programmer_shutdown(void);
115
116enum bitbang_spi_master_type {
117 BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */
118#if CONFIG_RAYER_SPI == 1
119 BITBANG_SPI_MASTER_RAYER,
120#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +0000121#if CONFIG_NICINTEL_SPI == 1
122 BITBANG_SPI_MASTER_NICINTEL,
123#endif
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000124#if CONFIG_INTERNAL == 1
125#if defined(__i386__) || defined(__x86_64__)
126 BITBANG_SPI_MASTER_MCP,
127#endif
128#endif
Mark Marshall90021f22010-12-03 14:48:11 +0000129#if CONFIG_OGP_SPI == 1
130 BITBANG_SPI_MASTER_OGP,
131#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000132};
133
134struct bitbang_spi_master {
135 enum bitbang_spi_master_type type;
136
137 /* Note that CS# is active low, so val=0 means the chip is active. */
138 void (*set_cs) (int val);
139 void (*set_sck) (int val);
140 void (*set_mosi) (int val);
141 int (*get_miso) (void);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000142 void (*request_bus) (void);
143 void (*release_bus) (void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000144};
145
146#if CONFIG_INTERNAL == 1
147struct penable {
148 uint16_t vendor_id;
149 uint16_t device_id;
150 int status;
151 const char *vendor_name;
152 const char *device_name;
153 int (*doit) (struct pci_dev *dev, const char *name);
154};
155
156extern const struct penable chipset_enables[];
157
158struct board_pciid_enable {
159 /* Any device, but make it sensible, like the ISA bridge. */
160 uint16_t first_vendor;
161 uint16_t first_device;
162 uint16_t first_card_vendor;
163 uint16_t first_card_device;
164
165 /* Any device, but make it sensible, like
166 * the host bridge. May be NULL.
167 */
168 uint16_t second_vendor;
169 uint16_t second_device;
170 uint16_t second_card_vendor;
171 uint16_t second_card_device;
172
173 /* Pattern to match DMI entries */
174 const char *dmi_pattern;
175
176 /* The vendor / part name from the coreboot table. */
177 const char *lb_vendor;
178 const char *lb_part;
179
180 const char *vendor_name;
181 const char *board_name;
182
183 int max_rom_decode_parallel;
184 int status;
185 int (*enable) (void);
186};
187
188extern const struct board_pciid_enable board_pciid_enables[];
189
190struct board_info {
191 const char *vendor;
192 const char *name;
193 const int working;
194#ifdef CONFIG_PRINT_WIKI
195 const char *url;
196 const char *note;
197#endif
198};
199
200extern const struct board_info boards_known[];
201extern const struct board_info laptops_known[];
202#endif
203
204/* udelay.c */
205void myusec_delay(int usecs);
206void myusec_calibrate_delay(void);
207void internal_delay(int usecs);
208
209#if NEED_PCI == 1
210/* pcidev.c */
211extern uint32_t io_base_addr;
212extern struct pci_access *pacc;
213extern struct pci_dev *pcidev_dev;
214struct pcidev_status {
215 uint16_t vendor_id;
216 uint16_t device_id;
217 int status;
218 const char *vendor_name;
219 const char *device_name;
220};
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +0000221uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs);
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +0000222uintptr_t pcidev_init(int bar, const struct pcidev_status *devs);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000223/* rpci_write_* are reversible writes. The original PCI config space register
224 * contents will be restored on shutdown.
225 */
Idwer Vollering1a6162e2010-12-26 23:55:19 +0000226int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
227int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
228int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000229#endif
230
231/* print.c */
Carl-Daniel Hailfingerd9535582011-03-08 00:09:11 +0000232#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000233void print_supported_pcidevs(const struct pcidev_status *devs);
234#endif
235
236/* board_enable.c */
237void w836xx_ext_enter(uint16_t port);
238void w836xx_ext_leave(uint16_t port);
239int it8705f_write_enable(uint8_t port);
240uint8_t sio_read(uint16_t port, uint8_t reg);
241void sio_write(uint16_t port, uint8_t reg, uint8_t data);
242void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
243int board_flash_enable(const char *vendor, const char *part);
244
245/* chipset_enable.c */
246int chipset_flash_enable(void);
247
248/* processor_enable.c */
249int processor_flash_enable(void);
250
251/* physmap.c */
252void *physmap(const char *descr, unsigned long phys_addr, size_t len);
253void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len);
254void physunmap(void *virt_addr, size_t len);
255int setup_cpu_msr(int cpu);
256void cleanup_cpu_msr(void);
257
258/* cbtable.c */
259void lb_vendor_dev_from_string(char *boardstring);
260int coreboot_init(void);
261extern char *lb_part, *lb_vendor;
262extern int partvendor_from_cbtable;
263
264/* dmi.c */
265extern int has_dmi_support;
266void dmi_init(void);
267int dmi_match(const char *pattern);
268
269/* internal.c */
270#if NEED_PCI == 1
271struct superio {
272 uint16_t vendor;
273 uint16_t port;
274 uint16_t model;
275};
276extern struct superio superio;
277#define SUPERIO_VENDOR_NONE 0x0
278#define SUPERIO_VENDOR_ITE 0x1
279struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
280struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class);
281struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
282struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
283 uint16_t card_vendor, uint16_t card_device);
284#endif
285void get_io_perms(void);
286void release_io_perms(void);
287#if CONFIG_INTERNAL == 1
288extern int is_laptop;
289extern int force_boardenable;
290extern int force_boardmismatch;
291void probe_superio(void);
292int internal_init(void);
293int internal_shutdown(void);
294void internal_chip_writeb(uint8_t val, chipaddr addr);
295void internal_chip_writew(uint16_t val, chipaddr addr);
296void internal_chip_writel(uint32_t val, chipaddr addr);
297uint8_t internal_chip_readb(const chipaddr addr);
298uint16_t internal_chip_readw(const chipaddr addr);
299uint32_t internal_chip_readl(const chipaddr addr);
300void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
301#endif
302
303/* hwaccess.c */
304void mmio_writeb(uint8_t val, void *addr);
305void mmio_writew(uint16_t val, void *addr);
306void mmio_writel(uint32_t val, void *addr);
307uint8_t mmio_readb(void *addr);
308uint16_t mmio_readw(void *addr);
309uint32_t mmio_readl(void *addr);
310void mmio_le_writeb(uint8_t val, void *addr);
311void mmio_le_writew(uint16_t val, void *addr);
312void mmio_le_writel(uint32_t val, void *addr);
313uint8_t mmio_le_readb(void *addr);
314uint16_t mmio_le_readw(void *addr);
315uint32_t mmio_le_readl(void *addr);
316#define pci_mmio_writeb mmio_le_writeb
317#define pci_mmio_writew mmio_le_writew
318#define pci_mmio_writel mmio_le_writel
319#define pci_mmio_readb mmio_le_readb
320#define pci_mmio_readw mmio_le_readw
321#define pci_mmio_readl mmio_le_readl
322
323/* programmer.c */
324int noop_shutdown(void);
325void *fallback_map(const char *descr, unsigned long phys_addr, size_t len);
326void fallback_unmap(void *virt_addr, size_t len);
327uint8_t noop_chip_readb(const chipaddr addr);
328void noop_chip_writeb(uint8_t val, chipaddr addr);
329void fallback_chip_writew(uint16_t val, chipaddr addr);
330void fallback_chip_writel(uint32_t val, chipaddr addr);
331void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
332uint16_t fallback_chip_readw(const chipaddr addr);
333uint32_t fallback_chip_readl(const chipaddr addr);
334void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
335
336/* dummyflasher.c */
337#if CONFIG_DUMMY == 1
338int dummy_init(void);
339int dummy_shutdown(void);
340void *dummy_map(const char *descr, unsigned long phys_addr, size_t len);
341void dummy_unmap(void *virt_addr, size_t len);
342void dummy_chip_writeb(uint8_t val, chipaddr addr);
343void dummy_chip_writew(uint16_t val, chipaddr addr);
344void dummy_chip_writel(uint32_t val, chipaddr addr);
345void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
346uint8_t dummy_chip_readb(const chipaddr addr);
347uint16_t dummy_chip_readw(const chipaddr addr);
348uint32_t dummy_chip_readl(const chipaddr addr);
349void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
350int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
351 const unsigned char *writearr, unsigned char *readarr);
352int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
353int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
354#endif
355
356/* nic3com.c */
357#if CONFIG_NIC3COM == 1
358int nic3com_init(void);
359int nic3com_shutdown(void);
360void nic3com_chip_writeb(uint8_t val, chipaddr addr);
361uint8_t nic3com_chip_readb(const chipaddr addr);
362extern const struct pcidev_status nics_3com[];
363#endif
364
365/* gfxnvidia.c */
366#if CONFIG_GFXNVIDIA == 1
367int gfxnvidia_init(void);
368int gfxnvidia_shutdown(void);
369void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr);
370uint8_t gfxnvidia_chip_readb(const chipaddr addr);
371extern const struct pcidev_status gfx_nvidia[];
372#endif
373
374/* drkaiser.c */
375#if CONFIG_DRKAISER == 1
376int drkaiser_init(void);
377int drkaiser_shutdown(void);
378void drkaiser_chip_writeb(uint8_t val, chipaddr addr);
379uint8_t drkaiser_chip_readb(const chipaddr addr);
380extern const struct pcidev_status drkaiser_pcidev[];
381#endif
382
383/* nicrealtek.c */
384#if CONFIG_NICREALTEK == 1
385int nicrealtek_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000386int nicrealtek_shutdown(void);
387void nicrealtek_chip_writeb(uint8_t val, chipaddr addr);
388uint8_t nicrealtek_chip_readb(const chipaddr addr);
389extern const struct pcidev_status nics_realtek[];
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000390#endif
391
392/* nicnatsemi.c */
393#if CONFIG_NICNATSEMI == 1
394int nicnatsemi_init(void);
395int nicnatsemi_shutdown(void);
396void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr);
397uint8_t nicnatsemi_chip_readb(const chipaddr addr);
398extern const struct pcidev_status nics_natsemi[];
399#endif
400
Idwer Vollering004f4b72010-09-03 18:21:21 +0000401/* nicintel_spi.c */
402#if CONFIG_NICINTEL_SPI == 1
403int nicintel_spi_init(void);
404int nicintel_spi_shutdown(void);
405int nicintel_spi_send_command(unsigned int writecnt, unsigned int readcnt,
406 const unsigned char *writearr, unsigned char *readarr);
407void nicintel_spi_chip_writeb(uint8_t val, chipaddr addr);
408extern const struct pcidev_status nics_intel_spi[];
409#endif
410
Mark Marshall90021f22010-12-03 14:48:11 +0000411/* ogp_spi.c */
412#if CONFIG_OGP_SPI == 1
413int ogp_spi_init(void);
414int ogp_spi_shutdown(void);
415extern const struct pcidev_status ogp_spi[];
416#endif
417
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000418/* satamv.c */
419#if CONFIG_SATAMV == 1
420int satamv_init(void);
421int satamv_shutdown(void);
422void satamv_chip_writeb(uint8_t val, chipaddr addr);
423uint8_t satamv_chip_readb(const chipaddr addr);
424extern const struct pcidev_status satas_mv[];
425#endif
426
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000427/* satasii.c */
428#if CONFIG_SATASII == 1
429int satasii_init(void);
430int satasii_shutdown(void);
431void satasii_chip_writeb(uint8_t val, chipaddr addr);
432uint8_t satasii_chip_readb(const chipaddr addr);
433extern const struct pcidev_status satas_sii[];
434#endif
435
436/* atahpt.c */
437#if CONFIG_ATAHPT == 1
438int atahpt_init(void);
439int atahpt_shutdown(void);
440void atahpt_chip_writeb(uint8_t val, chipaddr addr);
441uint8_t atahpt_chip_readb(const chipaddr addr);
442extern const struct pcidev_status ata_hpt[];
443#endif
444
445/* ft2232_spi.c */
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000446#if CONFIG_FT2232_SPI == 1
447struct usbdev_status {
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000448 uint16_t vendor_id;
449 uint16_t device_id;
450 int status;
451 const char *vendor_name;
452 const char *device_name;
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000453};
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000454int ft2232_spi_init(void);
455int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
456int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
457int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000458extern const struct usbdev_status devs_ft2232spi[];
459void print_supported_usbdevs(const struct usbdev_status *devs);
460#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000461
462/* rayer_spi.c */
463#if CONFIG_RAYER_SPI == 1
464int rayer_spi_init(void);
465#endif
466
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000467/* mcp6x_spi.c */
468#if CONFIG_INTERNAL == 1
469#if defined(__i386__) || defined(__x86_64__)
470int mcp6x_spi_init(int want_spi);
471#endif
472#endif
473
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000474/* bitbang_spi.c */
475int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000476int bitbang_spi_shutdown(const struct bitbang_spi_master *master);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000477int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
478int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
479int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
480
481/* buspirate_spi.c */
482struct buspirate_spispeeds {
483 const char *name;
484 const int speed;
485};
486int buspirate_spi_init(void);
487int buspirate_spi_shutdown(void);
488int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
489int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
490int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
491
492/* dediprog.c */
493int dediprog_init(void);
494int dediprog_shutdown(void);
495int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
496int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
Carl-Daniel Hailfinger306b8182010-11-23 21:28:16 +0000497int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000498
499/* flashrom.c */
500struct decode_sizes {
501 uint32_t parallel;
502 uint32_t lpc;
503 uint32_t fwh;
504 uint32_t spi;
505};
506extern struct decode_sizes max_rom_decode;
507extern int programmer_may_write;
508extern unsigned long flashbase;
509void check_chip_supported(struct flashchip *flash);
510int check_max_decode(enum chipbustype buses, uint32_t size);
511char *extract_programmer_param(char *param_name);
512
513/* layout.c */
514int show_id(uint8_t *bios, int size, int force);
515
516/* spi.c */
517enum spi_controller {
518 SPI_CONTROLLER_NONE,
519#if CONFIG_INTERNAL == 1
520#if defined(__i386__) || defined(__x86_64__)
521 SPI_CONTROLLER_ICH7,
522 SPI_CONTROLLER_ICH9,
David Hendricks4e748392011-02-28 23:58:15 +0000523 SPI_CONTROLLER_IT85XX,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000524 SPI_CONTROLLER_IT87XX,
525 SPI_CONTROLLER_SB600,
526 SPI_CONTROLLER_VIA,
527 SPI_CONTROLLER_WBSIO,
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000528 SPI_CONTROLLER_MCP6X_BITBANG,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000529#endif
530#endif
531#if CONFIG_FT2232_SPI == 1
532 SPI_CONTROLLER_FT2232,
533#endif
534#if CONFIG_DUMMY == 1
535 SPI_CONTROLLER_DUMMY,
536#endif
537#if CONFIG_BUSPIRATE_SPI == 1
538 SPI_CONTROLLER_BUSPIRATE,
539#endif
540#if CONFIG_DEDIPROG == 1
541 SPI_CONTROLLER_DEDIPROG,
542#endif
543#if CONFIG_RAYER_SPI == 1
544 SPI_CONTROLLER_RAYER,
545#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +0000546#if CONFIG_NICINTEL_SPI == 1
547 SPI_CONTROLLER_NICINTEL,
548#endif
Mark Marshall90021f22010-12-03 14:48:11 +0000549#if CONFIG_OGP_SPI == 1
550 SPI_CONTROLLER_OGP,
551#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000552 SPI_CONTROLLER_INVALID /* This must always be the last entry. */
553};
554extern const int spi_programmer_count;
555struct spi_programmer {
556 int (*command)(unsigned int writecnt, unsigned int readcnt,
557 const unsigned char *writearr, unsigned char *readarr);
558 int (*multicommand)(struct spi_command *cmds);
559
560 /* Optimized functions for this programmer */
561 int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len);
562 int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len);
563};
564
565extern enum spi_controller spi_controller;
566extern const struct spi_programmer spi_programmer[];
567int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
568 const unsigned char *writearr, unsigned char *readarr);
569int default_spi_send_multicommand(struct spi_command *cmds);
570
571/* ichspi.c */
572#if CONFIG_INTERNAL == 1
573extern uint32_t ichspi_bbar;
574int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
575 int ich_generation);
576int via_init_spi(struct pci_dev *dev);
577int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
578 const unsigned char *writearr, unsigned char *readarr);
579int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
580int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len);
581int ich_spi_send_multicommand(struct spi_command *cmds);
582#endif
583
David Hendricks4e748392011-02-28 23:58:15 +0000584/* it85spi.c */
585struct superio probe_superio_ite85xx(void);
586int it85xx_spi_init(void);
587int it85xx_shutdown(void);
588int it85xx_probe_spi_flash(const char *name);
589int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
590 const unsigned char *writearr, unsigned char *readarr);
591
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000592/* it87spi.c */
593void enter_conf_mode_ite(uint16_t port);
594void exit_conf_mode_ite(uint16_t port);
595struct superio probe_superio_ite(void);
596int init_superio_ite(void);
597int it87spi_init(void);
598int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
599 const unsigned char *writearr, unsigned char *readarr);
600int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len);
601int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
602
603/* sb600spi.c */
604#if CONFIG_INTERNAL == 1
605int sb600_probe_spi(struct pci_dev *dev);
606int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,
607 const unsigned char *writearr, unsigned char *readarr);
608int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
609int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
610#endif
611
612/* wbsio_spi.c */
613#if CONFIG_INTERNAL == 1
614int wbsio_check_for_spi(void);
615int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt,
616 const unsigned char *writearr, unsigned char *readarr);
617int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
618#endif
619
620/* serprog.c */
621int serprog_init(void);
622int serprog_shutdown(void);
623void serprog_chip_writeb(uint8_t val, chipaddr addr);
624uint8_t serprog_chip_readb(const chipaddr addr);
625void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
626void serprog_delay(int delay);
627
628/* serial.c */
629#if _WIN32
630typedef HANDLE fdtype;
631#else
632typedef int fdtype;
633#endif
634
635void sp_flush_incoming(void);
636fdtype sp_openserport(char *dev, unsigned int baud);
637void __attribute__((noreturn)) sp_die(char *msg);
638extern fdtype sp_fd;
639int serialport_shutdown(void);
640int serialport_write(unsigned char *buf, unsigned int writecnt);
641int serialport_read(unsigned char *buf, unsigned int readcnt);
642
643#endif /* !__PROGRAMMER_H__ */