Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d22a1d4 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it> |
| 6 | * Copyright (C) 2006 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 7 | * Copyright (C) 2007 Carl-Daniel Hailfinger |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 8 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 13 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 18 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 22 | */ |
| 23 | |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 24 | #include <stdio.h> |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 25 | #include <stdint.h> |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 26 | #include "flash.h" |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 27 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 28 | #define MAX_REFLASH_TRIES 0x10 |
| 29 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 30 | /* Check one byte for odd parity */ |
| 31 | uint8_t oddparity(uint8_t val) |
| 32 | { |
| 33 | val = (val ^ (val >> 4)) & 0xf; |
| 34 | val = (val ^ (val >> 2)) & 0x3; |
| 35 | return (val ^ (val >> 1)) & 0x1; |
| 36 | } |
| 37 | |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 38 | void toggle_ready_jedec(volatile uint8_t *dst) |
| 39 | { |
| 40 | unsigned int i = 0; |
| 41 | uint8_t tmp1, tmp2; |
| 42 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 43 | tmp1 = chip_readb(dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 44 | |
| 45 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 46 | tmp2 = chip_readb(dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 47 | if (tmp1 == tmp2) { |
| 48 | break; |
| 49 | } |
| 50 | tmp1 = tmp2; |
| 51 | } |
| 52 | } |
| 53 | |
| 54 | void data_polling_jedec(volatile uint8_t *dst, uint8_t data) |
| 55 | { |
| 56 | unsigned int i = 0; |
| 57 | uint8_t tmp; |
| 58 | |
| 59 | data &= 0x80; |
| 60 | |
| 61 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 62 | tmp = chip_readb(dst) & 0x80; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 63 | if (tmp == data) { |
| 64 | break; |
| 65 | } |
| 66 | } |
| 67 | } |
| 68 | |
| 69 | void unprotect_jedec(volatile uint8_t *bios) |
| 70 | { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 71 | chip_writeb(0xAA, bios + 0x5555); |
| 72 | chip_writeb(0x55, bios + 0x2AAA); |
| 73 | chip_writeb(0x80, bios + 0x5555); |
| 74 | chip_writeb(0xAA, bios + 0x5555); |
| 75 | chip_writeb(0x55, bios + 0x2AAA); |
| 76 | chip_writeb(0x20, bios + 0x5555); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 77 | |
| 78 | usleep(200); |
| 79 | } |
| 80 | |
| 81 | void protect_jedec(volatile uint8_t *bios) |
| 82 | { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 83 | chip_writeb(0xAA, bios + 0x5555); |
| 84 | chip_writeb(0x55, bios + 0x2AAA); |
| 85 | chip_writeb(0xA0, bios + 0x5555); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 86 | |
| 87 | usleep(200); |
| 88 | } |
| 89 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 90 | int probe_jedec(struct flashchip *flash) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 91 | { |
Stefan Reinauer | ce53297 | 2007-05-23 17:20:56 +0000 | [diff] [blame] | 92 | volatile uint8_t *bios = flash->virtual_memory; |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 93 | uint8_t id1, id2; |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 94 | uint32_t largeid1, largeid2; |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 95 | uint32_t flashcontent1, flashcontent2; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 96 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 97 | /* Issue JEDEC Product ID Entry command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 98 | chip_writeb(0xAA, bios + 0x5555); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 99 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 100 | chip_writeb(0x55, bios + 0x2AAA); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 101 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 102 | chip_writeb(0x90, bios + 0x5555); |
Carl-Daniel Hailfinger | 03d2826 | 2007-11-13 14:56:54 +0000 | [diff] [blame] | 103 | /* Older chips may need up to 100 us to respond. The ATMEL 29C020 |
Peter Stuge | 8653b00 | 2008-06-24 02:09:09 +0000 | [diff] [blame] | 104 | * needs 10 ms according to the data sheet. |
Carl-Daniel Hailfinger | 03d2826 | 2007-11-13 14:56:54 +0000 | [diff] [blame] | 105 | */ |
Peter Stuge | 8653b00 | 2008-06-24 02:09:09 +0000 | [diff] [blame] | 106 | myusec_delay(10000); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 107 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 108 | /* Read product ID */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 109 | id1 = chip_readb(bios); |
| 110 | id2 = chip_readb(bios + 0x01); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 111 | largeid1 = id1; |
| 112 | largeid2 = id2; |
| 113 | |
| 114 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 115 | if (id1 == 0x7F) { |
| 116 | largeid1 <<= 8; |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 117 | id1 = chip_readb(bios + 0x100); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 118 | largeid1 |= id1; |
| 119 | } |
| 120 | if (id2 == 0x7F) { |
| 121 | largeid2 <<= 8; |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 122 | id2 = chip_readb(bios + 0x101); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 123 | largeid2 |= id2; |
| 124 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 125 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 126 | /* Issue JEDEC Product ID Exit command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 127 | chip_writeb(0xAA, bios + 0x5555); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 128 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 129 | chip_writeb(0x55, bios + 0x2AAA); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 130 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 131 | chip_writeb(0xF0, bios + 0x5555); |
Carl-Daniel Hailfinger | 03d2826 | 2007-11-13 14:56:54 +0000 | [diff] [blame] | 132 | myusec_delay(40); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 133 | |
Peter Stuge | 5cafc33 | 2009-01-25 23:52:45 +0000 | [diff] [blame] | 134 | printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 135 | if (!oddparity(id1)) |
| 136 | printf_debug(", id1 parity violation"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 137 | |
| 138 | /* Read the product ID location again. We should now see normal flash contents. */ |
| 139 | flashcontent1 = chip_readb(bios); |
| 140 | flashcontent2 = chip_readb(bios + 0x01); |
| 141 | |
| 142 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 143 | if (flashcontent1 == 0x7F) { |
| 144 | flashcontent1 <<= 8; |
| 145 | flashcontent1 |= chip_readb(bios + 0x100); |
| 146 | } |
| 147 | if (flashcontent2 == 0x7F) { |
| 148 | flashcontent2 <<= 8; |
| 149 | flashcontent2 |= chip_readb(bios + 0x101); |
| 150 | } |
| 151 | |
| 152 | if (largeid1 == flashcontent1) |
| 153 | printf_debug(", id1 is normal flash content"); |
| 154 | if (largeid2 == flashcontent2) |
| 155 | printf_debug(", id2 is normal flash content"); |
| 156 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 157 | printf_debug("\n"); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 158 | if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 159 | return 1; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 160 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 161 | return 0; |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 162 | } |
| 163 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 164 | int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 165 | { |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 166 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 167 | chip_writeb(0xAA, bios + 0x5555); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 168 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 169 | chip_writeb(0x55, bios + 0x2AAA); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 170 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 171 | chip_writeb(0x80, bios + 0x5555); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 172 | myusec_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 173 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 174 | chip_writeb(0xAA, bios + 0x5555); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 175 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 176 | chip_writeb(0x55, bios + 0x2AAA); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 177 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 178 | chip_writeb(0x30, bios + page); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 179 | myusec_delay(10); |
| 180 | |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 181 | /* wait for Toggle bit ready */ |
| 182 | toggle_ready_jedec(bios); |
| 183 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 184 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 185 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 186 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 187 | int erase_block_jedec(volatile uint8_t *bios, unsigned int block) |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 188 | { |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 189 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 190 | chip_writeb(0xAA, bios + 0x5555); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 191 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 192 | chip_writeb(0x55, bios + 0x2AAA); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 193 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 194 | chip_writeb(0x80, bios + 0x5555); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 195 | myusec_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 196 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 197 | chip_writeb(0xAA, bios + 0x5555); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 198 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 199 | chip_writeb(0x55, bios + 0x2AAA); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 200 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 201 | chip_writeb(0x50, bios + block); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 202 | myusec_delay(10); |
| 203 | |
| 204 | /* wait for Toggle bit ready */ |
| 205 | toggle_ready_jedec(bios); |
| 206 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 207 | return 0; |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 208 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 209 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 210 | int erase_chip_jedec(struct flashchip *flash) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 211 | { |
Stefan Reinauer | ce53297 | 2007-05-23 17:20:56 +0000 | [diff] [blame] | 212 | volatile uint8_t *bios = flash->virtual_memory; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 213 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 214 | /* Issue the JEDEC Chip Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 215 | chip_writeb(0xAA, bios + 0x5555); |
Ronald G. Minnich | ef5779d | 2002-01-29 20:18:02 +0000 | [diff] [blame] | 216 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 217 | chip_writeb(0x55, bios + 0x2AAA); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 218 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 219 | chip_writeb(0x80, bios + 0x5555); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 220 | myusec_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 221 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 222 | chip_writeb(0xAA, bios + 0x5555); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 223 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 224 | chip_writeb(0x55, bios + 0x2AAA); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 225 | myusec_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 226 | chip_writeb(0x10, bios + 0x5555); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 227 | myusec_delay(10); |
| 228 | |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 229 | toggle_ready_jedec(bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 230 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 231 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 232 | } |
| 233 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 234 | int write_page_write_jedec(volatile uint8_t *bios, uint8_t *src, |
| 235 | volatile uint8_t *dst, int page_size) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 236 | { |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 237 | int i, tried = 0, start_index = 0, ok; |
| 238 | volatile uint8_t *d = dst; |
| 239 | uint8_t *s = src; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 240 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 241 | retry: |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 242 | /* Issue JEDEC Data Unprotect comand */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 243 | chip_writeb(0xAA, bios + 0x5555); |
| 244 | chip_writeb(0x55, bios + 0x2AAA); |
| 245 | chip_writeb(0xA0, bios + 0x5555); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 246 | |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 247 | /* transfer data from source to destination */ |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 248 | for (i = start_index; i < page_size; i++) { |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 249 | /* If the data is 0xFF, don't program it */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 250 | if (*src != 0xFF) |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 251 | chip_writeb(*src, dst); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 252 | dst++; |
| 253 | src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 254 | } |
| 255 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 256 | toggle_ready_jedec(dst - 1); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 257 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 258 | dst = d; |
| 259 | src = s; |
| 260 | ok = 1; |
| 261 | for (i = 0; i < page_size; i++) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 262 | if (chip_readb(dst) != *src) { |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 263 | ok = 0; |
| 264 | break; |
| 265 | } |
| 266 | dst++; |
| 267 | src++; |
| 268 | } |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 269 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 270 | if (!ok && tried++ < MAX_REFLASH_TRIES) { |
| 271 | start_index = i; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 272 | goto retry; |
| 273 | } |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 274 | if (!ok) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 275 | fprintf(stderr, " page %d failed!\n", |
| 276 | (unsigned int)(d - bios) / page_size); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 277 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 278 | return !ok; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 279 | } |
| 280 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 281 | int write_byte_program_jedec(volatile uint8_t *bios, uint8_t *src, |
| 282 | volatile uint8_t *dst) |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 283 | { |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 284 | int tried = 0, ok = 1; |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 285 | |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 286 | /* If the data is 0xFF, don't program it */ |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 287 | if (*src == 0xFF) { |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 288 | return -1; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 289 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 290 | |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 291 | retry: |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 292 | /* Issue JEDEC Byte Program command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 293 | chip_writeb(0xAA, bios + 0x5555); |
| 294 | chip_writeb(0x55, bios + 0x2AAA); |
| 295 | chip_writeb(0xA0, bios + 0x5555); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 296 | |
| 297 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 298 | chip_writeb(*src, dst); |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 299 | toggle_ready_jedec(bios); |
Ollie Lho | 8b8897a | 2004-03-27 00:18:15 +0000 | [diff] [blame] | 300 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 301 | if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 302 | goto retry; |
| 303 | } |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 304 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 305 | if (tried >= MAX_REFLASH_TRIES) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 306 | ok = 0; |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 307 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 308 | return !ok; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 309 | } |
| 310 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 311 | int write_sector_jedec(volatile uint8_t *bios, uint8_t *src, |
| 312 | volatile uint8_t *dst, unsigned int page_size) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 313 | { |
| 314 | int i; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 315 | |
| 316 | for (i = 0; i < page_size; i++) { |
Ollie Lho | 8b8897a | 2004-03-27 00:18:15 +0000 | [diff] [blame] | 317 | write_byte_program_jedec(bios, src, dst); |
| 318 | dst++, src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 319 | } |
| 320 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 321 | return 0; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 322 | } |
| 323 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 324 | int write_jedec(struct flashchip *flash, uint8_t *buf) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 325 | { |
| 326 | int i; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 327 | int total_size = flash->total_size * 1024; |
| 328 | int page_size = flash->page_size; |
Stefan Reinauer | ce53297 | 2007-05-23 17:20:56 +0000 | [diff] [blame] | 329 | volatile uint8_t *bios = flash->virtual_memory; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 330 | |
| 331 | erase_chip_jedec(flash); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 332 | // dumb check if erase was successful. |
| 333 | for (i = 0; i < total_size; i++) { |
Carl-Daniel Hailfinger | 01624f4 | 2009-05-12 15:38:55 +0000 | [diff] [blame] | 334 | if (chip_readb(bios + i) != (uint8_t) 0xff) { |
| 335 | printf("ERASE FAILED @%d, val %02x!\n", i, chip_readb(bios + i)); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 336 | return -1; |
| 337 | } |
| 338 | } |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 339 | |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 340 | printf("Programming page: "); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 341 | for (i = 0; i < total_size / page_size; i++) { |
| 342 | printf("%04d at address: 0x%08x", i, i * page_size); |
Ollie Lho | 8b8897a | 2004-03-27 00:18:15 +0000 | [diff] [blame] | 343 | write_page_write_jedec(bios, buf + i * page_size, |
| 344 | bios + i * page_size, page_size); |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 345 | printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 346 | } |
| 347 | printf("\n"); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 348 | protect_jedec(bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 349 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 350 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 351 | } |