blob: 81b4f9e7e237d7ddda6ebf2254d5d43b31a5c331 [file] [log] [blame]
Uwe Hermannb4dcb712009-05-13 11:36:06 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stdlib.h>
22#include <string.h>
Uwe Hermann92c53ee2009-05-13 12:01:57 +000023#include <fcntl.h>
24#include <sys/types.h>
25#include <sys/stat.h>
Uwe Hermannb4dcb712009-05-13 11:36:06 +000026#include <errno.h>
Uwe Hermannb4dcb712009-05-13 11:36:06 +000027#include "flash.h"
28
29#define BIOS_ROM_ADDR 0x04
30#define BIOS_ROM_DATA 0x08
31#define INT_STATUS 0x0e
Uwe Hermann8403ccb2009-05-16 21:39:19 +000032#define INTERNAL_CONFIG 0x00
Uwe Hermannb4dcb712009-05-13 11:36:06 +000033#define SELECT_REG_WINDOW 0x800
34
Uwe Hermannb4dcb712009-05-13 11:36:06 +000035#define PCI_VENDOR_ID_3COM 0x10b7
36
Uwe Hermann8403ccb2009-05-16 21:39:19 +000037uint32_t internal_conf;
38uint16_t id;
39
Uwe Hermann515ab3d2009-05-15 17:02:34 +000040struct pcidev_status nics_3com[] = {
Uwe Hermannb4dcb712009-05-13 11:36:06 +000041 /* 3C90xB */
Uwe Hermann8403ccb2009-05-16 21:39:19 +000042 {0x10b7, 0x9055, PCI_OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
Uwe Hermann515ab3d2009-05-15 17:02:34 +000043 {0x10b7, 0x9001, PCI_NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
44 {0x10b7, 0x9004, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
45 {0x10b7, 0x9005, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
46 {0x10b7, 0x9006, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
47 {0x10b7, 0x900a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FL" },
48 {0x10b7, 0x905a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FX" },
Uwe Hermanne9d04d42009-06-02 19:54:22 +000049 {0x10b7, 0x9058, PCI_OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000050
51 /* 3C905C */
Uwe Hermann515ab3d2009-05-15 17:02:34 +000052 {0x10b7, 0x9200, PCI_OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000053
54 /* 3C980C */
Uwe Hermann515ab3d2009-05-15 17:02:34 +000055 {0x10b7, 0x9805, PCI_NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000056
57 {},
58};
59
60int nic3com_init(void)
61{
Uwe Hermanna0869322009-05-14 20:41:57 +000062 get_io_perms();
Uwe Hermannb4dcb712009-05-13 11:36:06 +000063
Uwe Hermann515ab3d2009-05-15 17:02:34 +000064 io_base_addr = pcidev_init(PCI_VENDOR_ID_3COM, nics_3com);
Uwe Hermann8403ccb2009-05-16 21:39:19 +000065 id = pcidev_dev->device_id;
66
67 /* 3COM 3C90xB cards need a special fixup. */
68 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +000069 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +000070 /* Select register window 3 and save the receiver status. */
71 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
72 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
73
74 /* Set receiver type to MII for full BIOS ROM access. */
75 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
76 }
Uwe Hermannb4dcb712009-05-13 11:36:06 +000077
78 /*
79 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
80 * cards form a 'register window' into one of multiple (usually 8)
81 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
82 */
83 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
84
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000085 buses_supported = CHIP_BUSTYPE_PARALLEL;
86
Uwe Hermannb4dcb712009-05-13 11:36:06 +000087 return 0;
88}
89
90int nic3com_shutdown(void)
91{
Uwe Hermann8403ccb2009-05-16 21:39:19 +000092 /* 3COM 3C90xB cards need a special fixup. */
93 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +000094 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +000095 /* Select register window 3 and restore the receiver status. */
96 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
97 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
98 }
99
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000100 free(pcidev_bdf);
Christian Ruppert0cdb0312009-05-14 18:57:26 +0000101 pci_cleanup(pacc);
Uwe Hermanna0869322009-05-14 20:41:57 +0000102#if defined(__FreeBSD__) || defined(__DragonFly__)
103 close(io_fd);
104#endif
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000105 return 0;
106}
107
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000108void nic3com_chip_writeb(uint8_t val, chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000109{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000110 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000111 OUTB(val, io_base_addr + BIOS_ROM_DATA);
112}
113
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000114uint8_t nic3com_chip_readb(const chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000115{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000116 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannc7e8a0c2009-05-19 14:14:21 +0000117 return INB(io_base_addr + BIOS_ROM_DATA);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000118}