blob: d3d7bdb3d4f490daed5be38ca5189b2cd0664e08 [file] [log] [blame]
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005 coresystems GmbH <stepan@openbios.org>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00006 *
Uwe Hermannd1107642007-08-29 17:52:32 +00007 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000016 *
Uwe Hermannd1107642007-08-29 17:52:32 +000017 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000020 */
21
22#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000023
24#define AUTO_PG_ERASE1 0x20
25#define AUTO_PG_ERASE2 0xD0
Ollie Lhocf29de82004-03-18 19:40:07 +000026#define AUTO_PGRM 0x10
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000027#define CHIP_ERASE 0x30
28#define RESET 0xFF
29#define READ_ID 0x90
30
Uwe Hermann09e04f72009-05-16 22:36:00 +000031static void protect_28sf040(chipaddr bios)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000032{
Carl-Daniel Hailfingerb8855692009-03-06 00:40:25 +000033 uint8_t tmp;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000034
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000035 tmp = chip_readb(bios + 0x1823);
36 tmp = chip_readb(bios + 0x1820);
37 tmp = chip_readb(bios + 0x1822);
38 tmp = chip_readb(bios + 0x0418);
39 tmp = chip_readb(bios + 0x041B);
40 tmp = chip_readb(bios + 0x0419);
41 tmp = chip_readb(bios + 0x040A);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000042}
43
Uwe Hermann09e04f72009-05-16 22:36:00 +000044static void unprotect_28sf040(chipaddr bios)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000045{
Carl-Daniel Hailfingerb8855692009-03-06 00:40:25 +000046 uint8_t tmp;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000047
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000048 tmp = chip_readb(bios + 0x1823);
49 tmp = chip_readb(bios + 0x1820);
50 tmp = chip_readb(bios + 0x1822);
51 tmp = chip_readb(bios + 0x0418);
52 tmp = chip_readb(bios + 0x041B);
53 tmp = chip_readb(bios + 0x0419);
54 tmp = chip_readb(bios + 0x041A);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000055}
56
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000057static int erase_sector_28sf040(struct flashchip *flash, unsigned long address, int sector_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000058{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000059 chipaddr bios = flash->virtual_memory;
60
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000061 chip_writeb(AUTO_PG_ERASE1, bios);
62 chip_writeb(AUTO_PG_ERASE2, bios + address);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000063
64 /* wait for Toggle bit ready */
65 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000066
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000067 if (check_erased_range(flash, address, sector_size)) {
68 fprintf(stderr, "ERASE FAILED!\n");
69 return -1;
70 }
Uwe Hermannffec5f32007-08-23 16:08:21 +000071 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000072}
73
Uwe Hermann09e04f72009-05-16 22:36:00 +000074static int write_sector_28sf040(chipaddr bios, uint8_t *src, chipaddr dst,
75 unsigned int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000076{
77 int i;
78
79 for (i = 0; i < page_size; i++) {
80 /* transfer data from source to destination */
81 if (*src == 0xFF) {
82 dst++, src++;
83 /* If the data is 0xFF, don't program it */
84 continue;
85 }
86 /*issue AUTO PROGRAM command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000087 chip_writeb(AUTO_PGRM, dst);
88 chip_writeb(*src++, dst++);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000089
90 /* wait for Toggle bit ready */
91 toggle_ready_jedec(bios);
92 }
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000093
Uwe Hermannffec5f32007-08-23 16:08:21 +000094 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000095}
96
Ollie Lho761bf1b2004-03-20 16:46:10 +000097int probe_28sf040(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000098{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000099 chipaddr bios = flash->virtual_memory;
Ed Swierk966dc202007-08-13 04:10:32 +0000100 uint8_t id1, id2;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000101
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000102 chip_writeb(RESET, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000103 programmer_delay(10);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000104
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000105 chip_writeb(READ_ID, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000106 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000107 id1 = chip_readb(bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000108 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000109 id2 = chip_readb(bios + 0x01);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000110
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000111 chip_writeb(RESET, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000112 programmer_delay(10);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000113
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000114 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000115 if (id1 == flash->manufacture_id && id2 == flash->model_id)
116 return 1;
117
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000118 return 0;
119}
120
Ollie Lho761bf1b2004-03-20 16:46:10 +0000121int erase_28sf040(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000122{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000123 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000124
Ollie Lho761bf1b2004-03-20 16:46:10 +0000125 unprotect_28sf040(bios);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000126 chip_writeb(CHIP_ERASE, bios);
127 chip_writeb(CHIP_ERASE, bios);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000128 protect_28sf040(bios);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000129
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000130 programmer_delay(10);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000131 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000132
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000133 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
134 fprintf(stderr, "ERASE FAILED!\n");
135 return -1;
136 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000137 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000138}
139
Ollie Lho184a4042005-11-26 21:55:36 +0000140int write_28sf040(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000141{
142 int i;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000143 int total_size = flash->total_size * 1024;
144 int page_size = flash->page_size;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000145 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000146
Ollie Lho761bf1b2004-03-20 16:46:10 +0000147 unprotect_28sf040(bios);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000148
Uwe Hermanna502dce2007-10-17 23:55:15 +0000149 printf("Programming page: ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000150 for (i = 0; i < total_size / page_size; i++) {
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000151 /* erase the page before programming */
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000152 if (erase_sector_28sf040(flash, i * page_size, page_size)) {
153 fprintf(stderr, "ERASE FAILED!\n");
154 return -1;
155 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000156
157 /* write to the sector */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000158 printf("%04d at address: 0x%08x", i, i * page_size);
159 write_sector_28sf040(bios, buf + i * page_size,
160 bios + i * page_size, page_size);
Ollie Lho8b8897a2004-03-27 00:18:15 +0000161 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000162 }
163 printf("\n");
164
Ollie Lho761bf1b2004-03-20 16:46:10 +0000165 protect_28sf040(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000166
Uwe Hermannffec5f32007-08-23 16:08:21 +0000167 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000168}