Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 5 | * Copyright (C) 2008 coresystems GmbH |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Contains the generic SPI framework |
| 23 | */ |
| 24 | |
| 25 | #include <stdio.h> |
| 26 | #include <pci/pci.h> |
| 27 | #include <stdint.h> |
| 28 | #include <string.h> |
| 29 | #include "flash.h" |
Carl-Daniel Hailfinger | d6cbf76 | 2008-05-13 14:58:23 +0000 | [diff] [blame] | 30 | #include "spi.h" |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 31 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 32 | |
| 33 | void spi_prettyprint_status_register(struct flashchip *flash); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 34 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 35 | int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 36 | { |
| 37 | if (it8716f_flashport) |
Carl-Daniel Hailfinger | a5b8efd | 2008-05-10 23:40:51 +0000 | [diff] [blame] | 38 | return it8716f_spi_command(writecnt, readcnt, writearr, readarr); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 39 | else if (ich7_detected) |
| 40 | return ich_spi_command(writecnt, readcnt, writearr, readarr); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 41 | else if (ich9_detected) |
| 42 | return ich_spi_command(writecnt, readcnt, writearr, readarr); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 43 | printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 44 | return 1; |
| 45 | } |
| 46 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 47 | static int spi_rdid(unsigned char *readarr) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 48 | { |
Carl-Daniel Hailfinger | 228231f | 2008-05-13 14:01:22 +0000 | [diff] [blame] | 49 | const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID}; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 50 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 51 | if (spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd, readarr)) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 52 | return 1; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 53 | printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 54 | return 0; |
| 55 | } |
| 56 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 57 | static int spi_res(unsigned char *readarr) |
| 58 | { |
| 59 | const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0}; |
| 60 | |
| 61 | if (spi_command(JEDEC_RES_OUTSIZE, JEDEC_RES_INSIZE, cmd, readarr)) |
| 62 | return 1; |
| 63 | printf_debug("RES returned %02x.\n", readarr[0]); |
| 64 | return 0; |
| 65 | } |
| 66 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 67 | void spi_write_enable() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 68 | { |
Carl-Daniel Hailfinger | 228231f | 2008-05-13 14:01:22 +0000 | [diff] [blame] | 69 | const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN}; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 70 | |
| 71 | /* Send WREN (Write Enable) */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 72 | spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 73 | } |
| 74 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 75 | void spi_write_disable() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 76 | { |
Carl-Daniel Hailfinger | 228231f | 2008-05-13 14:01:22 +0000 | [diff] [blame] | 77 | const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI}; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 78 | |
| 79 | /* Send WRDI (Write Disable) */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 80 | spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 81 | } |
| 82 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 83 | int probe_spi_rdid(struct flashchip *flash) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 84 | { |
| 85 | unsigned char readarr[3]; |
Carl-Daniel Hailfinger | 1263d2a | 2008-02-06 22:07:58 +0000 | [diff] [blame] | 86 | uint32_t manuf_id; |
| 87 | uint32_t model_id; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 88 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 89 | if (spi_rdid(readarr)) |
| 90 | return 0; |
| 91 | |
| 92 | if (!oddparity(readarr[0])) |
| 93 | printf_debug("RDID byte 0 parity violation.\n"); |
| 94 | |
| 95 | /* Check if this is a continuation vendor ID */ |
| 96 | if (readarr[0] == 0x7f) { |
| 97 | if (!oddparity(readarr[1])) |
| 98 | printf_debug("RDID byte 1 parity violation.\n"); |
| 99 | manuf_id = (readarr[0] << 8) | readarr[1]; |
| 100 | model_id = readarr[2]; |
| 101 | } else { |
| 102 | manuf_id = readarr[0]; |
| 103 | model_id = (readarr[1] << 8) | readarr[2]; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 104 | } |
| 105 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 106 | printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id); |
| 107 | |
| 108 | if (manuf_id == flash->manufacture_id && |
| 109 | model_id == flash->model_id) { |
| 110 | /* Print the status register to tell the |
| 111 | * user about possible write protection. |
| 112 | */ |
| 113 | spi_prettyprint_status_register(flash); |
| 114 | |
| 115 | return 1; |
| 116 | } |
| 117 | |
| 118 | /* Test if this is a pure vendor match. */ |
| 119 | if (manuf_id == flash->manufacture_id && |
| 120 | GENERIC_DEVICE_ID == flash->model_id) |
| 121 | return 1; |
| 122 | |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 123 | return 0; |
| 124 | } |
| 125 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 126 | int probe_spi_res(struct flashchip *flash) |
| 127 | { |
| 128 | unsigned char readarr[3]; |
| 129 | uint32_t model_id; |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 130 | |
| 131 | if (spi_rdid(readarr)) |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 132 | /* We couldn't issue RDID, it's pointless to try RES. */ |
| 133 | return 0; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 134 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 135 | /* Check if RDID returns 0xff 0xff 0xff, then we use RES. */ |
| 136 | if ((readarr[0] != 0xff) || (readarr[1] != 0xff) || |
| 137 | (readarr[2] != 0xff)) |
| 138 | return 0; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 139 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 140 | if (spi_res(readarr)) |
| 141 | return 0; |
| 142 | |
| 143 | model_id = readarr[0]; |
| 144 | printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id); |
| 145 | if (model_id != flash->model_id) |
| 146 | return 0; |
| 147 | |
| 148 | /* Print the status register to tell the |
| 149 | * user about possible write protection. |
| 150 | */ |
| 151 | spi_prettyprint_status_register(flash); |
| 152 | return 1; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 153 | } |
| 154 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 155 | uint8_t spi_read_status_register() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 156 | { |
Carl-Daniel Hailfinger | 228231f | 2008-05-13 14:01:22 +0000 | [diff] [blame] | 157 | const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR}; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 158 | unsigned char readarr[1]; |
| 159 | |
| 160 | /* Read Status Register */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 161 | spi_command(JEDEC_RDSR_OUTSIZE, JEDEC_RDSR_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 162 | return readarr[0]; |
| 163 | } |
| 164 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 165 | /* Prettyprint the status register. Common definitions. |
| 166 | */ |
| 167 | void spi_prettyprint_status_register_common(uint8_t status) |
| 168 | { |
| 169 | printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " |
| 170 | "%sset\n", (status & (1 << 5)) ? "" : "not "); |
| 171 | printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " |
| 172 | "%sset\n", (status & (1 << 4)) ? "" : "not "); |
| 173 | printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " |
| 174 | "%sset\n", (status & (1 << 3)) ? "" : "not "); |
| 175 | printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " |
| 176 | "%sset\n", (status & (1 << 2)) ? "" : "not "); |
| 177 | printf_debug("Chip status register: Write Enable Latch (WEL) is " |
| 178 | "%sset\n", (status & (1 << 1)) ? "" : "not "); |
| 179 | printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " |
| 180 | "%sset\n", (status & (1 << 0)) ? "" : "not "); |
| 181 | } |
| 182 | |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 183 | /* Prettyprint the status register. Works for |
| 184 | * ST M25P series |
| 185 | * MX MX25L series |
| 186 | */ |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 187 | void spi_prettyprint_status_register_st_m25p(uint8_t status) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 188 | { |
| 189 | printf_debug("Chip status register: Status Register Write Disable " |
| 190 | "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
| 191 | printf_debug("Chip status register: Bit 6 is " |
| 192 | "%sset\n", (status & (1 << 6)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 193 | spi_prettyprint_status_register_common(status); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 194 | } |
| 195 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 196 | /* Prettyprint the status register. Works for |
| 197 | * SST 25VF016 |
| 198 | */ |
| 199 | void spi_prettyprint_status_register_sst25vf016(uint8_t status) |
| 200 | { |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 201 | const char *bpt[] = { |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 202 | "none", |
| 203 | "1F0000H-1FFFFFH", |
| 204 | "1E0000H-1FFFFFH", |
| 205 | "1C0000H-1FFFFFH", |
| 206 | "180000H-1FFFFFH", |
| 207 | "100000H-1FFFFFH", |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 208 | "all", "all" |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 209 | }; |
| 210 | printf_debug("Chip status register: Block Protect Write Disable " |
| 211 | "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
| 212 | printf_debug("Chip status register: Auto Address Increment Programming " |
| 213 | "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); |
| 214 | spi_prettyprint_status_register_common(status); |
| 215 | printf_debug("Resulting block protection : %s\n", |
| 216 | bpt[(status & 0x1c) >> 2]); |
| 217 | } |
| 218 | |
| 219 | void spi_prettyprint_status_register(struct flashchip *flash) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 220 | { |
| 221 | uint8_t status; |
| 222 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 223 | status = spi_read_status_register(); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 224 | printf_debug("Chip status register is %02x\n", status); |
| 225 | switch (flash->manufacture_id) { |
| 226 | case ST_ID: |
Carl-Daniel Hailfinger | f43e642 | 2008-05-15 22:32:08 +0000 | [diff] [blame] | 227 | if (((flash->model_id & 0xff00) == 0x2000) || |
| 228 | ((flash->model_id & 0xff00) == 0x2500)) |
| 229 | spi_prettyprint_status_register_st_m25p(status); |
| 230 | break; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 231 | case MX_ID: |
| 232 | if ((flash->model_id & 0xff00) == 0x2000) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 233 | spi_prettyprint_status_register_st_m25p(status); |
| 234 | break; |
| 235 | case SST_ID: |
| 236 | if (flash->model_id == SST_25VF016B) |
| 237 | spi_prettyprint_status_register_sst25vf016(status); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 238 | break; |
| 239 | } |
| 240 | } |
| 241 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 242 | int spi_chip_erase_c7(struct flashchip *flash) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 243 | { |
Carl-Daniel Hailfinger | 228231f | 2008-05-13 14:01:22 +0000 | [diff] [blame] | 244 | const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7}; |
Carl-Daniel Hailfinger | f5df46f | 2007-12-16 21:15:27 +0000 | [diff] [blame] | 245 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 246 | spi_disable_blockprotect(); |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 247 | spi_write_enable(); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 248 | /* Send CE (Chip Erase) */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 249 | spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 250 | /* Wait until the Write-In-Progress bit is cleared. |
| 251 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 252 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 253 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 254 | sleep(1); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 255 | return 0; |
| 256 | } |
| 257 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 258 | /* Block size is usually |
| 259 | * 64k for Macronix |
| 260 | * 32k for SST |
| 261 | * 4-32k non-uniform for EON |
| 262 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 263 | int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 264 | { |
Carl-Daniel Hailfinger | 228231f | 2008-05-13 14:01:22 +0000 | [diff] [blame] | 265 | unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = {JEDEC_BE_D8}; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 266 | |
| 267 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 268 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 269 | cmd[3] = (addr & 0x000000ff); |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 270 | spi_write_enable(); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 271 | /* Send BE (Block Erase) */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 272 | spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 273 | /* Wait until the Write-In-Progress bit is cleared. |
| 274 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 275 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 276 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 277 | usleep(100 * 1000); |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | /* Sector size is usually 4k, though Macronix eliteflash has 64k */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 282 | int spi_sector_erase(const struct flashchip *flash, unsigned long addr) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 283 | { |
Carl-Daniel Hailfinger | 228231f | 2008-05-13 14:01:22 +0000 | [diff] [blame] | 284 | unsigned char cmd[JEDEC_SE_OUTSIZE] = {JEDEC_SE}; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 285 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 286 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 287 | cmd[3] = (addr & 0x000000ff); |
| 288 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 289 | spi_write_enable(); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 290 | /* Send SE (Sector Erase) */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 291 | spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 292 | /* Wait until the Write-In-Progress bit is cleared. |
| 293 | * This usually takes 15-800 ms, so wait in 10 ms steps. |
| 294 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 295 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 296 | usleep(10 * 1000); |
| 297 | return 0; |
| 298 | } |
| 299 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 300 | void spi_page_program(int block, uint8_t *buf, uint8_t *bios) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 301 | { |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 302 | if (it8716f_flashport) { |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 303 | it8716f_spi_page_program(block, buf, bios); |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 304 | return; |
| 305 | } |
| 306 | printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 307 | } |
| 308 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 309 | /* |
| 310 | * This is according the SST25VF016 datasheet, who knows it is more |
| 311 | * generic that this... |
| 312 | */ |
| 313 | void spi_write_status_register(int status) |
| 314 | { |
Carl-Daniel Hailfinger | 228231f | 2008-05-13 14:01:22 +0000 | [diff] [blame] | 315 | const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status}; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 316 | |
| 317 | /* Send WRSR (Write Status Register) */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 318 | spi_command(JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | void spi_byte_program(int address, uint8_t byte) |
| 322 | { |
| 323 | const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {JEDEC_BYTE_PROGRAM, |
| 324 | (address>>16)&0xff, |
| 325 | (address>>8)&0xff, |
| 326 | (address>>0)&0xff, |
| 327 | byte |
| 328 | }; |
| 329 | |
| 330 | /* Send Byte-Program */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 331 | spi_command(JEDEC_BYTE_PROGRAM_OUTSIZE, JEDEC_BYTE_PROGRAM_INSIZE, cmd, NULL); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 332 | } |
| 333 | |
| 334 | void spi_disable_blockprotect(void) |
| 335 | { |
| 336 | uint8_t status; |
| 337 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 338 | status = spi_read_status_register(); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 339 | /* If there is block protection in effect, unprotect it first. */ |
| 340 | if ((status & 0x3c) != 0) { |
| 341 | printf_debug("Some block protection in effect, disabling\n"); |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 342 | spi_write_enable(); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 343 | spi_write_status_register(status & ~0x3c); |
| 344 | } |
| 345 | } |
| 346 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 347 | void spi_nbyte_read(int address, uint8_t *bytes, int len) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 348 | { |
| 349 | const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ, |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 350 | (address >> 16) & 0xff, |
| 351 | (address >> 8) & 0xff, |
| 352 | (address >> 0) & 0xff, |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | /* Send Read */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 356 | spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 357 | } |
| 358 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 359 | int spi_chip_read(struct flashchip *flash, uint8_t *buf) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 360 | { |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 361 | if (it8716f_flashport) |
| 362 | return it8716f_spi_chip_read(flash, buf); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 363 | else if (ich7_detected) |
| 364 | return ich_spi_read(flash, buf); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 365 | else if (ich9_detected) |
| 366 | return ich_spi_read(flash, buf); |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 367 | printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); |
| 368 | return 1; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 369 | } |
| 370 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 371 | int spi_chip_write(struct flashchip *flash, uint8_t *buf) |
| 372 | { |
| 373 | if (it8716f_flashport) |
| 374 | return it8716f_spi_chip_write(flash, buf); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 375 | else if (ich7_detected) |
| 376 | return ich_spi_write(flash, buf); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 377 | else if (ich9_detected) |
| 378 | return ich_spi_write(flash, buf); |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 379 | printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); |
| 380 | return 1; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 381 | } |
| 382 | |