Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 5 | * Copyright (C) 2008 coresystems GmbH |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Contains the generic SPI framework |
| 23 | */ |
| 24 | |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 25 | #include <string.h> |
| 26 | #include "flash.h" |
Carl-Daniel Hailfinger | 0845464 | 2009-06-15 14:14:48 +0000 | [diff] [blame] | 27 | #include "flashchips.h" |
Carl-Daniel Hailfinger | d6cbf76 | 2008-05-13 14:58:23 +0000 | [diff] [blame] | 28 | #include "spi.h" |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 29 | |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 30 | enum spi_controller spi_controller = SPI_CONTROLLER_NONE; |
| 31 | void *spibar = NULL; |
| 32 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 33 | void spi_prettyprint_status_register(struct flashchip *flash); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 34 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 35 | int spi_send_command(unsigned int writecnt, unsigned int readcnt, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 36 | const unsigned char *writearr, unsigned char *readarr) |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 37 | { |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 38 | switch (spi_controller) { |
| 39 | case SPI_CONTROLLER_IT87XX: |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 40 | return it8716f_spi_send_command(writecnt, readcnt, writearr, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 41 | readarr); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 42 | case SPI_CONTROLLER_ICH7: |
| 43 | case SPI_CONTROLLER_ICH9: |
| 44 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 45 | return ich_spi_send_command(writecnt, readcnt, writearr, readarr); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 46 | case SPI_CONTROLLER_SB600: |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 47 | return sb600_spi_send_command(writecnt, readcnt, writearr, readarr); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 48 | case SPI_CONTROLLER_WBSIO: |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 49 | return wbsio_spi_send_command(writecnt, readcnt, writearr, readarr); |
Paul Fox | 05dfbe6 | 2009-06-16 21:08:06 +0000 | [diff] [blame] | 50 | case SPI_CONTROLLER_FT2232: |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 51 | return ft2232_spi_send_command(writecnt, readcnt, writearr, readarr); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 52 | case SPI_CONTROLLER_DUMMY: |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 53 | return dummy_spi_send_command(writecnt, readcnt, writearr, readarr); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 54 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 55 | printf_debug |
| 56 | ("%s called, but no SPI chipset/strapping detected\n", |
| 57 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 58 | } |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 59 | return 1; |
| 60 | } |
| 61 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 62 | int spi_send_multicommand(struct spi_command *spicommands) |
| 63 | { |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 64 | int ret = 0; |
| 65 | while ((spicommands->writecnt || spicommands->readcnt) && !ret) { |
| 66 | ret = spi_send_command(spicommands->writecnt, spicommands->readcnt, |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 67 | spicommands->writearr, spicommands->readarr); |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 68 | /* This awful hack needs to be replaced with a multicommand |
| 69 | * capable ICH/VIA SPI driver. |
| 70 | */ |
| 71 | if ((ret == SPI_INVALID_OPCODE) && |
| 72 | ((spicommands->writearr[0] == JEDEC_WREN) || |
| 73 | (spicommands->writearr[0] == JEDEC_EWSR))) { |
| 74 | switch (spi_controller) { |
| 75 | case SPI_CONTROLLER_ICH7: |
| 76 | case SPI_CONTROLLER_ICH9: |
| 77 | case SPI_CONTROLLER_VIA: |
| 78 | printf_debug(" due to SPI master limitation, ignoring" |
| 79 | " and hoping it will be run as PREOP\n"); |
| 80 | ret = 0; |
| 81 | default: |
| 82 | break; |
| 83 | } |
| 84 | } |
| 85 | spicommands++; |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 86 | } |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 87 | return ret; |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 90 | static int spi_rdid(unsigned char *readarr, int bytes) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 91 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 92 | const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 93 | int ret; |
Carl-Daniel Hailfinger | bfe2e0c | 2009-05-14 12:59:36 +0000 | [diff] [blame] | 94 | int i; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 95 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 96 | ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 97 | if (ret) |
| 98 | return ret; |
Carl-Daniel Hailfinger | bfe2e0c | 2009-05-14 12:59:36 +0000 | [diff] [blame] | 99 | printf_debug("RDID returned"); |
| 100 | for (i = 0; i < bytes; i++) |
| 101 | printf_debug(" 0x%02x", readarr[i]); |
| 102 | printf_debug("\n"); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 103 | return 0; |
| 104 | } |
| 105 | |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 106 | static int spi_rems(unsigned char *readarr) |
| 107 | { |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 108 | unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; |
| 109 | uint32_t readaddr; |
| 110 | int ret; |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 111 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 112 | ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 113 | if (ret == SPI_INVALID_ADDRESS) { |
| 114 | /* Find the lowest even address allowed for reads. */ |
| 115 | readaddr = (spi_get_valid_read_addr() + 1) & ~1; |
| 116 | cmd[1] = (readaddr >> 16) & 0xff, |
| 117 | cmd[2] = (readaddr >> 8) & 0xff, |
| 118 | cmd[3] = (readaddr >> 0) & 0xff, |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 119 | ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 120 | } |
| 121 | if (ret) |
| 122 | return ret; |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 123 | printf_debug("REMS returned %02x %02x.\n", readarr[0], readarr[1]); |
| 124 | return 0; |
| 125 | } |
| 126 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 127 | static int spi_res(unsigned char *readarr) |
| 128 | { |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 129 | unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; |
| 130 | uint32_t readaddr; |
| 131 | int ret; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 132 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 133 | ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 134 | if (ret == SPI_INVALID_ADDRESS) { |
| 135 | /* Find the lowest even address allowed for reads. */ |
| 136 | readaddr = (spi_get_valid_read_addr() + 1) & ~1; |
| 137 | cmd[1] = (readaddr >> 16) & 0xff, |
| 138 | cmd[2] = (readaddr >> 8) & 0xff, |
| 139 | cmd[3] = (readaddr >> 0) & 0xff, |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 140 | ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 141 | } |
| 142 | if (ret) |
| 143 | return ret; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 144 | printf_debug("RES returned %02x.\n", readarr[0]); |
| 145 | return 0; |
| 146 | } |
| 147 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 148 | int spi_write_enable(void) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 149 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 150 | const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 151 | int result; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 152 | |
| 153 | /* Send WREN (Write Enable) */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 154 | result = spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 155 | |
| 156 | if (result) |
| 157 | printf_debug("%s failed", __func__); |
| 158 | if (result == SPI_INVALID_OPCODE) { |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 159 | switch (spi_controller) { |
| 160 | case SPI_CONTROLLER_ICH7: |
| 161 | case SPI_CONTROLLER_ICH9: |
| 162 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 163 | printf_debug(" due to SPI master limitation, ignoring" |
| 164 | " and hoping it will be run as PREOP\n"); |
| 165 | return 0; |
| 166 | default: |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 167 | break; |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 168 | } |
| 169 | } |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 170 | if (result) |
| 171 | printf_debug("\n"); |
| 172 | |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 173 | return result; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 174 | } |
| 175 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 176 | int spi_write_disable(void) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 177 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 178 | const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 179 | |
| 180 | /* Send WRDI (Write Disable) */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 181 | return spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 182 | } |
| 183 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 184 | static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 185 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 186 | unsigned char readarr[4]; |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 187 | uint32_t id1; |
| 188 | uint32_t id2; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 189 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 190 | if (spi_rdid(readarr, bytes)) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 191 | return 0; |
| 192 | |
| 193 | if (!oddparity(readarr[0])) |
| 194 | printf_debug("RDID byte 0 parity violation.\n"); |
| 195 | |
| 196 | /* Check if this is a continuation vendor ID */ |
| 197 | if (readarr[0] == 0x7f) { |
| 198 | if (!oddparity(readarr[1])) |
| 199 | printf_debug("RDID byte 1 parity violation.\n"); |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 200 | id1 = (readarr[0] << 8) | readarr[1]; |
| 201 | id2 = readarr[2]; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 202 | if (bytes > 3) { |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 203 | id2 <<= 8; |
| 204 | id2 |= readarr[3]; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 205 | } |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 206 | } else { |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 207 | id1 = readarr[0]; |
| 208 | id2 = (readarr[1] << 8) | readarr[2]; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 209 | } |
| 210 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 211 | printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 212 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 213 | if (id1 == flash->manufacture_id && id2 == flash->model_id) { |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 214 | /* Print the status register to tell the |
| 215 | * user about possible write protection. |
| 216 | */ |
| 217 | spi_prettyprint_status_register(flash); |
| 218 | |
| 219 | return 1; |
| 220 | } |
| 221 | |
| 222 | /* Test if this is a pure vendor match. */ |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 223 | if (id1 == flash->manufacture_id && |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 224 | GENERIC_DEVICE_ID == flash->model_id) |
| 225 | return 1; |
| 226 | |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 227 | return 0; |
| 228 | } |
| 229 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 230 | int probe_spi_rdid(struct flashchip *flash) |
| 231 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 232 | return probe_spi_rdid_generic(flash, 3); |
| 233 | } |
| 234 | |
| 235 | /* support 4 bytes flash ID */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 236 | int probe_spi_rdid4(struct flashchip *flash) |
| 237 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 238 | /* only some SPI chipsets support 4 bytes commands */ |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 239 | switch (spi_controller) { |
| 240 | case SPI_CONTROLLER_ICH7: |
| 241 | case SPI_CONTROLLER_ICH9: |
| 242 | case SPI_CONTROLLER_VIA: |
| 243 | case SPI_CONTROLLER_SB600: |
| 244 | case SPI_CONTROLLER_WBSIO: |
Paul Fox | 05dfbe6 | 2009-06-16 21:08:06 +0000 | [diff] [blame] | 245 | case SPI_CONTROLLER_FT2232: |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 246 | case SPI_CONTROLLER_DUMMY: |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 247 | return probe_spi_rdid_generic(flash, 4); |
| 248 | default: |
| 249 | printf_debug("4b ID not supported on this SPI controller\n"); |
| 250 | } |
| 251 | |
| 252 | return 0; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 253 | } |
| 254 | |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 255 | int probe_spi_rems(struct flashchip *flash) |
| 256 | { |
| 257 | unsigned char readarr[JEDEC_REMS_INSIZE]; |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 258 | uint32_t id1, id2; |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 259 | |
| 260 | if (spi_rems(readarr)) |
| 261 | return 0; |
| 262 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 263 | id1 = readarr[0]; |
| 264 | id2 = readarr[1]; |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 265 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 266 | printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 267 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 268 | if (id1 == flash->manufacture_id && id2 == flash->model_id) { |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 269 | /* Print the status register to tell the |
| 270 | * user about possible write protection. |
| 271 | */ |
| 272 | spi_prettyprint_status_register(flash); |
| 273 | |
| 274 | return 1; |
| 275 | } |
| 276 | |
| 277 | /* Test if this is a pure vendor match. */ |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 278 | if (id1 == flash->manufacture_id && |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 279 | GENERIC_DEVICE_ID == flash->model_id) |
| 280 | return 1; |
| 281 | |
| 282 | return 0; |
| 283 | } |
| 284 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 285 | int probe_spi_res(struct flashchip *flash) |
| 286 | { |
| 287 | unsigned char readarr[3]; |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 288 | uint32_t id2; |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 289 | |
Carl-Daniel Hailfinger | 92a54ca | 2008-11-27 22:48:48 +0000 | [diff] [blame] | 290 | /* Check if RDID was successful and did not return 0xff 0xff 0xff. |
| 291 | * In that case, RES is pointless. |
| 292 | */ |
| 293 | if (!spi_rdid(readarr, 3) && ((readarr[0] != 0xff) || |
| 294 | (readarr[1] != 0xff) || (readarr[2] != 0xff))) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 295 | return 0; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 296 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 297 | if (spi_res(readarr)) |
| 298 | return 0; |
| 299 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 300 | id2 = readarr[0]; |
| 301 | printf_debug("%s: id 0x%x\n", __FUNCTION__, id2); |
| 302 | if (id2 != flash->model_id) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 303 | return 0; |
| 304 | |
| 305 | /* Print the status register to tell the |
| 306 | * user about possible write protection. |
| 307 | */ |
| 308 | spi_prettyprint_status_register(flash); |
| 309 | return 1; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 310 | } |
| 311 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 312 | uint8_t spi_read_status_register(void) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 313 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 314 | const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; |
Peter Stuge | bf196e9 | 2009-01-26 03:08:45 +0000 | [diff] [blame] | 315 | unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 316 | int ret; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 317 | |
| 318 | /* Read Status Register */ |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 319 | if (spi_controller == SPI_CONTROLLER_SB600) { |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 320 | /* SB600 uses a different way to read status register. */ |
| 321 | return sb600_read_status_register(); |
| 322 | } else { |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 323 | ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 324 | if (ret) |
| 325 | printf_debug("RDSR failed!\n"); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 326 | } |
| 327 | |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 328 | return readarr[0]; |
| 329 | } |
| 330 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 331 | /* Prettyprint the status register. Common definitions. */ |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 332 | void spi_prettyprint_status_register_common(uint8_t status) |
| 333 | { |
| 334 | printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 335 | "%sset\n", (status & (1 << 5)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 336 | printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 337 | "%sset\n", (status & (1 << 4)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 338 | printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 339 | "%sset\n", (status & (1 << 3)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 340 | printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 341 | "%sset\n", (status & (1 << 2)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 342 | printf_debug("Chip status register: Write Enable Latch (WEL) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 343 | "%sset\n", (status & (1 << 1)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 344 | printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 345 | "%sset\n", (status & (1 << 0)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 346 | } |
| 347 | |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 348 | /* Prettyprint the status register. Works for |
| 349 | * ST M25P series |
| 350 | * MX MX25L series |
| 351 | */ |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 352 | void spi_prettyprint_status_register_st_m25p(uint8_t status) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 353 | { |
| 354 | printf_debug("Chip status register: Status Register Write Disable " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 355 | "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 356 | printf_debug("Chip status register: Bit 6 is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 357 | "%sset\n", (status & (1 << 6)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 358 | spi_prettyprint_status_register_common(status); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 359 | } |
| 360 | |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 361 | void spi_prettyprint_status_register_sst25(uint8_t status) |
| 362 | { |
| 363 | printf_debug("Chip status register: Block Protect Write Disable " |
| 364 | "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
| 365 | printf_debug("Chip status register: Auto Address Increment Programming " |
| 366 | "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); |
| 367 | spi_prettyprint_status_register_common(status); |
| 368 | } |
| 369 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 370 | /* Prettyprint the status register. Works for |
| 371 | * SST 25VF016 |
| 372 | */ |
| 373 | void spi_prettyprint_status_register_sst25vf016(uint8_t status) |
| 374 | { |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 375 | const char *bpt[] = { |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 376 | "none", |
| 377 | "1F0000H-1FFFFFH", |
| 378 | "1E0000H-1FFFFFH", |
| 379 | "1C0000H-1FFFFFH", |
| 380 | "180000H-1FFFFFH", |
| 381 | "100000H-1FFFFFH", |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 382 | "all", "all" |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 383 | }; |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 384 | spi_prettyprint_status_register_sst25(status); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 385 | printf_debug("Resulting block protection : %s\n", |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 386 | bpt[(status & 0x1c) >> 2]); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 387 | } |
| 388 | |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 389 | void spi_prettyprint_status_register_sst25vf040b(uint8_t status) |
| 390 | { |
| 391 | const char *bpt[] = { |
| 392 | "none", |
| 393 | "0x70000-0x7ffff", |
| 394 | "0x60000-0x7ffff", |
| 395 | "0x40000-0x7ffff", |
| 396 | "all blocks", "all blocks", "all blocks", "all blocks" |
| 397 | }; |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 398 | spi_prettyprint_status_register_sst25(status); |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 399 | printf_debug("Resulting block protection : %s\n", |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 400 | bpt[(status & 0x1c) >> 2]); |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 401 | } |
| 402 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 403 | void spi_prettyprint_status_register(struct flashchip *flash) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 404 | { |
| 405 | uint8_t status; |
| 406 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 407 | status = spi_read_status_register(); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 408 | printf_debug("Chip status register is %02x\n", status); |
| 409 | switch (flash->manufacture_id) { |
| 410 | case ST_ID: |
Carl-Daniel Hailfinger | f43e642 | 2008-05-15 22:32:08 +0000 | [diff] [blame] | 411 | if (((flash->model_id & 0xff00) == 0x2000) || |
| 412 | ((flash->model_id & 0xff00) == 0x2500)) |
| 413 | spi_prettyprint_status_register_st_m25p(status); |
| 414 | break; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 415 | case MX_ID: |
| 416 | if ((flash->model_id & 0xff00) == 0x2000) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 417 | spi_prettyprint_status_register_st_m25p(status); |
| 418 | break; |
| 419 | case SST_ID: |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 420 | switch (flash->model_id) { |
| 421 | case 0x2541: |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 422 | spi_prettyprint_status_register_sst25vf016(status); |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 423 | break; |
| 424 | case 0x8d: |
| 425 | case 0x258d: |
| 426 | spi_prettyprint_status_register_sst25vf040b(status); |
| 427 | break; |
Carl-Daniel Hailfinger | 5100a8a | 2009-05-13 22:51:27 +0000 | [diff] [blame] | 428 | default: |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 429 | spi_prettyprint_status_register_sst25(status); |
| 430 | break; |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 431 | } |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 432 | break; |
| 433 | } |
| 434 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 435 | |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 436 | int spi_chip_erase_60(struct flashchip *flash) |
| 437 | { |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 438 | int result; |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 439 | struct spi_command spicommands[] = { |
| 440 | { |
| 441 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 442 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 443 | .readcnt = 0, |
| 444 | .readarr = NULL, |
| 445 | }, { |
| 446 | .writecnt = JEDEC_CE_60_OUTSIZE, |
| 447 | .writearr = (const unsigned char[]){ JEDEC_CE_60 }, |
| 448 | .readcnt = 0, |
| 449 | .readarr = NULL, |
| 450 | }, { |
| 451 | .writecnt = 0, |
| 452 | .writearr = NULL, |
| 453 | .readcnt = 0, |
| 454 | .readarr = NULL, |
| 455 | }}; |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 456 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 457 | result = spi_disable_blockprotect(); |
| 458 | if (result) { |
| 459 | printf_debug("spi_disable_blockprotect failed\n"); |
| 460 | return result; |
| 461 | } |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 462 | |
| 463 | result = spi_send_multicommand(spicommands); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 464 | if (result) { |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 465 | printf_debug("%s failed during command execution\n", __func__); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 466 | return result; |
| 467 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 468 | /* Wait until the Write-In-Progress bit is cleared. |
| 469 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 470 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 471 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 472 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 473 | programmer_delay(1000 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 474 | if (check_erased_range(flash, 0, flash->total_size * 1024)) { |
| 475 | fprintf(stderr, "ERASE FAILED!\n"); |
| 476 | return -1; |
| 477 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 478 | return 0; |
| 479 | } |
| 480 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 481 | int spi_chip_erase_c7(struct flashchip *flash) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 482 | { |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 483 | int result; |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 484 | struct spi_command spicommands[] = { |
| 485 | { |
| 486 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 487 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 488 | .readcnt = 0, |
| 489 | .readarr = NULL, |
| 490 | }, { |
| 491 | .writecnt = JEDEC_CE_C7_OUTSIZE, |
| 492 | .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, |
| 493 | .readcnt = 0, |
| 494 | .readarr = NULL, |
| 495 | }, { |
| 496 | .writecnt = 0, |
| 497 | .writearr = NULL, |
| 498 | .readcnt = 0, |
| 499 | .readarr = NULL, |
| 500 | }}; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 501 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 502 | result = spi_disable_blockprotect(); |
| 503 | if (result) { |
| 504 | printf_debug("spi_disable_blockprotect failed\n"); |
| 505 | return result; |
| 506 | } |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 507 | |
| 508 | result = spi_send_multicommand(spicommands); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 509 | if (result) { |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 510 | printf_debug("%s failed during command execution\n", __func__); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 511 | return result; |
| 512 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 513 | /* Wait until the Write-In-Progress bit is cleared. |
| 514 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 515 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 516 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 517 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 518 | programmer_delay(1000 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 519 | if (check_erased_range(flash, 0, flash->total_size * 1024)) { |
| 520 | fprintf(stderr, "ERASE FAILED!\n"); |
| 521 | return -1; |
| 522 | } |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 523 | return 0; |
| 524 | } |
| 525 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 526 | int spi_chip_erase_60_c7(struct flashchip *flash) |
| 527 | { |
| 528 | int result; |
| 529 | result = spi_chip_erase_60(flash); |
| 530 | if (result) { |
| 531 | printf_debug("spi_chip_erase_60 failed, trying c7\n"); |
| 532 | result = spi_chip_erase_c7(flash); |
| 533 | } |
| 534 | return result; |
| 535 | } |
| 536 | |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 537 | int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 538 | { |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 539 | unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52, }; |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 540 | int result; |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 541 | |
| 542 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 543 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 544 | cmd[3] = (addr & 0x000000ff); |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 545 | result = spi_write_enable(); |
| 546 | if (result) |
| 547 | return result; |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 548 | /* Send BE (Block Erase) */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 549 | spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 550 | /* Wait until the Write-In-Progress bit is cleared. |
| 551 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 552 | */ |
| 553 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 554 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 555 | if (check_erased_range(flash, addr, blocklen)) { |
| 556 | fprintf(stderr, "ERASE FAILED!\n"); |
| 557 | return -1; |
| 558 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 559 | return 0; |
| 560 | } |
| 561 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 562 | /* Block size is usually |
| 563 | * 64k for Macronix |
| 564 | * 32k for SST |
| 565 | * 4-32k non-uniform for EON |
| 566 | */ |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 567 | int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 568 | { |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 569 | unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8, }; |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 570 | int result; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 571 | |
| 572 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 573 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 574 | cmd[3] = (addr & 0x000000ff); |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 575 | result = spi_write_enable(); |
| 576 | if (result) |
| 577 | return result; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 578 | /* Send BE (Block Erase) */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 579 | spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 580 | /* Wait until the Write-In-Progress bit is cleared. |
| 581 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 582 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 583 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 584 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 585 | if (check_erased_range(flash, addr, blocklen)) { |
| 586 | fprintf(stderr, "ERASE FAILED!\n"); |
| 587 | return -1; |
| 588 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 589 | return 0; |
| 590 | } |
| 591 | |
Stefan Reinauer | 424ed22 | 2008-10-29 22:13:20 +0000 | [diff] [blame] | 592 | int spi_chip_erase_d8(struct flashchip *flash) |
| 593 | { |
| 594 | int i, rc = 0; |
| 595 | int total_size = flash->total_size * 1024; |
| 596 | int erase_size = 64 * 1024; |
| 597 | |
| 598 | spi_disable_blockprotect(); |
| 599 | |
| 600 | printf("Erasing chip: \n"); |
| 601 | |
| 602 | for (i = 0; i < total_size / erase_size; i++) { |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 603 | rc = spi_block_erase_d8(flash, i * erase_size, erase_size); |
Stefan Reinauer | 424ed22 | 2008-10-29 22:13:20 +0000 | [diff] [blame] | 604 | if (rc) { |
| 605 | printf("Error erasing block at 0x%x\n", i); |
| 606 | break; |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | printf("\n"); |
| 611 | |
| 612 | return rc; |
| 613 | } |
| 614 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 615 | /* Sector size is usually 4k, though Macronix eliteflash has 64k */ |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 616 | int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 617 | { |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 618 | unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE, }; |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 619 | int result; |
| 620 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 621 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 622 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 623 | cmd[3] = (addr & 0x000000ff); |
| 624 | |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 625 | result = spi_write_enable(); |
| 626 | if (result) |
| 627 | return result; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 628 | /* Send SE (Sector Erase) */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 629 | spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 630 | /* Wait until the Write-In-Progress bit is cleared. |
| 631 | * This usually takes 15-800 ms, so wait in 10 ms steps. |
| 632 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 633 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 634 | programmer_delay(10 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 635 | if (check_erased_range(flash, addr, blocklen)) { |
| 636 | fprintf(stderr, "ERASE FAILED!\n"); |
| 637 | return -1; |
| 638 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 639 | return 0; |
| 640 | } |
| 641 | |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 642 | int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
| 643 | { |
| 644 | if ((addr != 0) || (blocklen != flash->total_size * 1024)) { |
| 645 | fprintf(stderr, "%s called with incorrect arguments\n", __func__); |
| 646 | return -1; |
| 647 | } |
| 648 | return spi_chip_erase_60(flash); |
| 649 | } |
| 650 | |
| 651 | int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
| 652 | { |
| 653 | if ((addr != 0) || (blocklen != flash->total_size * 1024)) { |
| 654 | fprintf(stderr, "%s called with incorrect arguments\n", __func__); |
| 655 | return -1; |
| 656 | } |
| 657 | return spi_chip_erase_c7(flash); |
| 658 | } |
| 659 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 660 | int spi_write_status_enable(void) |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 661 | { |
| 662 | const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 663 | int result; |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 664 | |
| 665 | /* Send EWSR (Enable Write Status Register). */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 666 | result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 667 | |
| 668 | if (result) |
| 669 | printf_debug("%s failed", __func__); |
| 670 | if (result == SPI_INVALID_OPCODE) { |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 671 | switch (spi_controller) { |
| 672 | case SPI_CONTROLLER_ICH7: |
| 673 | case SPI_CONTROLLER_ICH9: |
| 674 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 675 | printf_debug(" due to SPI master limitation, ignoring" |
| 676 | " and hoping it will be run as PREOP\n"); |
| 677 | return 0; |
| 678 | default: |
| 679 | break; |
| 680 | } |
| 681 | } |
| 682 | if (result) |
| 683 | printf_debug("\n"); |
| 684 | |
| 685 | return result; |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 686 | } |
| 687 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 688 | /* |
| 689 | * This is according the SST25VF016 datasheet, who knows it is more |
| 690 | * generic that this... |
| 691 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 692 | int spi_write_status_register(int status) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 693 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 694 | const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = |
| 695 | { JEDEC_WRSR, (unsigned char)status }; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 696 | |
| 697 | /* Send WRSR (Write Status Register) */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 698 | return spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 699 | } |
| 700 | |
| 701 | void spi_byte_program(int address, uint8_t byte) |
| 702 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 703 | const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = { |
| 704 | JEDEC_BYTE_PROGRAM, |
| 705 | (address >> 16) & 0xff, |
| 706 | (address >> 8) & 0xff, |
| 707 | (address >> 0) & 0xff, |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 708 | byte |
| 709 | }; |
| 710 | |
| 711 | /* Send Byte-Program */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 712 | spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 713 | } |
| 714 | |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 715 | int spi_nbyte_program(int address, uint8_t *bytes, int len) |
| 716 | { |
| 717 | unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { |
| 718 | JEDEC_BYTE_PROGRAM, |
| 719 | (address >> 16) & 0xff, |
| 720 | (address >> 8) & 0xff, |
| 721 | (address >> 0) & 0xff, |
| 722 | }; |
| 723 | |
| 724 | if (len > 256) { |
| 725 | printf_debug ("%s called for too long a write\n", |
| 726 | __FUNCTION__); |
| 727 | return 1; |
| 728 | } |
| 729 | |
| 730 | memcpy(&cmd[4], bytes, len); |
| 731 | |
| 732 | /* Send Byte-Program */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 733 | return spi_send_command(4 + len, 0, cmd, NULL); |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 734 | } |
| 735 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 736 | int spi_disable_blockprotect(void) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 737 | { |
| 738 | uint8_t status; |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 739 | int result; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 740 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 741 | status = spi_read_status_register(); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 742 | /* If there is block protection in effect, unprotect it first. */ |
| 743 | if ((status & 0x3c) != 0) { |
| 744 | printf_debug("Some block protection in effect, disabling\n"); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 745 | result = spi_write_status_enable(); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 746 | if (result) { |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 747 | printf_debug("spi_write_status_enable failed\n"); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 748 | return result; |
| 749 | } |
| 750 | result = spi_write_status_register(status & ~0x3c); |
| 751 | if (result) { |
| 752 | printf_debug("spi_write_status_register failed\n"); |
| 753 | return result; |
| 754 | } |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 755 | } |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 756 | return 0; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 757 | } |
| 758 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 759 | int spi_nbyte_read(int address, uint8_t *bytes, int len) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 760 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 761 | const unsigned char cmd[JEDEC_READ_OUTSIZE] = { |
| 762 | JEDEC_READ, |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 763 | (address >> 16) & 0xff, |
| 764 | (address >> 8) & 0xff, |
| 765 | (address >> 0) & 0xff, |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 766 | }; |
| 767 | |
| 768 | /* Send Read */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 769 | return spi_send_command(sizeof(cmd), len, cmd, bytes); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 770 | } |
| 771 | |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 772 | /* |
| 773 | * Read a complete flash chip. |
| 774 | * Each page is read separately in chunks with a maximum size of chunksize. |
| 775 | */ |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 776 | int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 777 | { |
| 778 | int rc = 0; |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 779 | int i, j, starthere, lenhere; |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 780 | int page_size = flash->page_size; |
| 781 | int toread; |
| 782 | |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 783 | /* Warning: This loop has a very unusual condition and body. |
| 784 | * The loop needs to go through each page with at least one affected |
| 785 | * byte. The lowest page number is (start / page_size) since that |
| 786 | * division rounds down. The highest page number we want is the page |
| 787 | * where the last byte of the range lives. That last byte has the |
| 788 | * address (start + len - 1), thus the highest page number is |
| 789 | * (start + len - 1) / page_size. Since we want to include that last |
| 790 | * page as well, the loop condition uses <=. |
| 791 | */ |
| 792 | for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { |
| 793 | /* Byte position of the first byte in the range in this page. */ |
| 794 | /* starthere is an offset to the base address of the chip. */ |
| 795 | starthere = max(start, i * page_size); |
| 796 | /* Length of bytes in the range in this page. */ |
| 797 | lenhere = min(start + len, (i + 1) * page_size) - starthere; |
| 798 | for (j = 0; j < lenhere; j += chunksize) { |
| 799 | toread = min(chunksize, lenhere - j); |
| 800 | rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread); |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 801 | if (rc) |
| 802 | break; |
| 803 | } |
| 804 | if (rc) |
| 805 | break; |
| 806 | } |
| 807 | |
| 808 | return rc; |
| 809 | } |
| 810 | |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 811 | int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 812 | { |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 813 | switch (spi_controller) { |
| 814 | case SPI_CONTROLLER_IT87XX: |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 815 | return it8716f_spi_chip_read(flash, buf, start, len); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 816 | case SPI_CONTROLLER_SB600: |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 817 | return sb600_spi_read(flash, buf, start, len); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 818 | case SPI_CONTROLLER_ICH7: |
| 819 | case SPI_CONTROLLER_ICH9: |
| 820 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 821 | return ich_spi_read(flash, buf, start, len); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 822 | case SPI_CONTROLLER_WBSIO: |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 823 | return wbsio_spi_read(flash, buf, start, len); |
Paul Fox | 05dfbe6 | 2009-06-16 21:08:06 +0000 | [diff] [blame] | 824 | case SPI_CONTROLLER_FT2232: |
| 825 | return ft2232_spi_read(flash, buf, start, len); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 826 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 827 | printf_debug |
| 828 | ("%s called, but no SPI chipset/strapping detected\n", |
| 829 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 830 | } |
| 831 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 832 | return 1; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 833 | } |
| 834 | |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 835 | /* |
| 836 | * Program chip using byte programming. (SLOW!) |
| 837 | * This is for chips which can only handle one byte writes |
| 838 | * and for chips where memory mapped programming is impossible |
| 839 | * (e.g. due to size constraints in IT87* for over 512 kB) |
| 840 | */ |
| 841 | int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) |
| 842 | { |
| 843 | int total_size = 1024 * flash->total_size; |
| 844 | int i; |
| 845 | |
| 846 | spi_disable_blockprotect(); |
| 847 | for (i = 0; i < total_size; i++) { |
| 848 | spi_write_enable(); |
| 849 | spi_byte_program(i, buf[i]); |
| 850 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 851 | programmer_delay(10); |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 852 | } |
| 853 | |
| 854 | return 0; |
| 855 | } |
| 856 | |
| 857 | /* |
| 858 | * Program chip using page (256 bytes) programming. |
| 859 | * Some SPI masters can't do this, they use single byte programming instead. |
| 860 | */ |
Carl-Daniel Hailfinger | 8d49701 | 2009-05-09 02:34:18 +0000 | [diff] [blame] | 861 | int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 862 | { |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 863 | switch (spi_controller) { |
| 864 | case SPI_CONTROLLER_IT87XX: |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 865 | return it8716f_spi_chip_write_256(flash, buf); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 866 | case SPI_CONTROLLER_SB600: |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 867 | return sb600_spi_write_1(flash, buf); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 868 | case SPI_CONTROLLER_ICH7: |
| 869 | case SPI_CONTROLLER_ICH9: |
| 870 | case SPI_CONTROLLER_VIA: |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 871 | return ich_spi_write_256(flash, buf); |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 872 | case SPI_CONTROLLER_WBSIO: |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 873 | return wbsio_spi_write_1(flash, buf); |
Paul Fox | 05dfbe6 | 2009-06-16 21:08:06 +0000 | [diff] [blame] | 874 | case SPI_CONTROLLER_FT2232: |
| 875 | return ft2232_spi_write_256(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 876 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 877 | printf_debug |
| 878 | ("%s called, but no SPI chipset/strapping detected\n", |
| 879 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 880 | } |
| 881 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 882 | return 1; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 883 | } |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 884 | |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 885 | uint32_t spi_get_valid_read_addr(void) |
| 886 | { |
| 887 | /* Need to return BBAR for ICH chipsets. */ |
| 888 | return 0; |
| 889 | } |
| 890 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 891 | int spi_aai_write(struct flashchip *flash, uint8_t *buf) |
| 892 | { |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 893 | uint32_t pos = 2, size = flash->total_size * 1024; |
| 894 | unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 895 | int result; |
| 896 | |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 897 | switch (spi_controller) { |
| 898 | case SPI_CONTROLLER_WBSIO: |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 899 | fprintf(stderr, "%s: impossible with Winbond SPI masters," |
| 900 | " degrading to byte program\n", __func__); |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 901 | return spi_chip_write_1(flash, buf); |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 902 | default: |
| 903 | break; |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 904 | } |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 905 | if (flash->erase(flash)) { |
| 906 | fprintf(stderr, "ERASE FAILED!\n"); |
| 907 | return -1; |
| 908 | } |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 909 | result = spi_write_enable(); |
| 910 | if (result) |
| 911 | return result; |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 912 | spi_send_command(6, 0, w, NULL); |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 913 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 914 | programmer_delay(5); /* SST25VF040B Tbp is max 10us */ |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 915 | while (pos < size) { |
| 916 | w[1] = buf[pos++]; |
| 917 | w[2] = buf[pos++]; |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 918 | spi_send_command(3, 0, w, NULL); |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 919 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 920 | programmer_delay(5); /* SST25VF040B Tbp is max 10us */ |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 921 | } |
| 922 | spi_write_disable(); |
| 923 | return 0; |
| 924 | } |