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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000018 *
Uwe Hermannd1107642007-08-29 17:52:32 +000019 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000022 */
23
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000024#include <stdio.h>
Ollie Lho184a4042005-11-26 21:55:36 +000025#include <stdint.h>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000026#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000027
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000028#define MAX_REFLASH_TRIES 0x10
29
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000030/* Check one byte for odd parity */
31uint8_t oddparity(uint8_t val)
32{
33 val = (val ^ (val >> 4)) & 0xf;
34 val = (val ^ (val >> 2)) & 0x3;
35 return (val ^ (val >> 1)) & 0x1;
36}
37
Uwe Hermann51582f22007-08-23 10:20:40 +000038void toggle_ready_jedec(volatile uint8_t *dst)
39{
40 unsigned int i = 0;
41 uint8_t tmp1, tmp2;
42
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000043 tmp1 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000044
45 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000046 tmp2 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000047 if (tmp1 == tmp2) {
48 break;
49 }
50 tmp1 = tmp2;
51 }
52}
53
54void data_polling_jedec(volatile uint8_t *dst, uint8_t data)
55{
56 unsigned int i = 0;
57 uint8_t tmp;
58
59 data &= 0x80;
60
61 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000062 tmp = chip_readb(dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000063 if (tmp == data) {
64 break;
65 }
66 }
67}
68
69void unprotect_jedec(volatile uint8_t *bios)
70{
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000071 chip_writeb(0xAA, bios + 0x5555);
72 chip_writeb(0x55, bios + 0x2AAA);
73 chip_writeb(0x80, bios + 0x5555);
74 chip_writeb(0xAA, bios + 0x5555);
75 chip_writeb(0x55, bios + 0x2AAA);
76 chip_writeb(0x20, bios + 0x5555);
Uwe Hermann51582f22007-08-23 10:20:40 +000077
78 usleep(200);
79}
80
81void protect_jedec(volatile uint8_t *bios)
82{
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000083 chip_writeb(0xAA, bios + 0x5555);
84 chip_writeb(0x55, bios + 0x2AAA);
85 chip_writeb(0xA0, bios + 0x5555);
Uwe Hermann51582f22007-08-23 10:20:40 +000086
87 usleep(200);
88}
89
Ollie Lho761bf1b2004-03-20 16:46:10 +000090int probe_jedec(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000091{
Stefan Reinauerce532972007-05-23 17:20:56 +000092 volatile uint8_t *bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000093 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +000094 uint32_t largeid1, largeid2;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000095
Ollie Lho761bf1b2004-03-20 16:46:10 +000096 /* Issue JEDEC Product ID Entry command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000097 chip_writeb(0xAA, bios + 0x5555);
Ollie Lho761bf1b2004-03-20 16:46:10 +000098 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000099 chip_writeb(0x55, bios + 0x2AAA);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000100 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000101 chip_writeb(0x90, bios + 0x5555);
Carl-Daniel Hailfinger03d28262007-11-13 14:56:54 +0000102 /* Older chips may need up to 100 us to respond. The ATMEL 29C020
Peter Stuge8653b002008-06-24 02:09:09 +0000103 * needs 10 ms according to the data sheet.
Carl-Daniel Hailfinger03d28262007-11-13 14:56:54 +0000104 */
Peter Stuge8653b002008-06-24 02:09:09 +0000105 myusec_delay(10000);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000106
Ollie Lho761bf1b2004-03-20 16:46:10 +0000107 /* Read product ID */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000108 id1 = chip_readb(bios);
109 id2 = chip_readb(bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000110 largeid1 = id1;
111 largeid2 = id2;
112
113 /* Check if it is a continuation ID, this should be a while loop. */
114 if (id1 == 0x7F) {
115 largeid1 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000116 id1 = chip_readb(bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000117 largeid1 |= id1;
118 }
119 if (id2 == 0x7F) {
120 largeid2 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000121 id2 = chip_readb(bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000122 largeid2 |= id2;
123 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000124
Ollie Lho761bf1b2004-03-20 16:46:10 +0000125 /* Issue JEDEC Product ID Exit command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000126 chip_writeb(0xAA, bios + 0x5555);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000127 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000128 chip_writeb(0x55, bios + 0x2AAA);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000129 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000130 chip_writeb(0xF0, bios + 0x5555);
Carl-Daniel Hailfinger03d28262007-11-13 14:56:54 +0000131 myusec_delay(40);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000132
Peter Stuge5cafc332009-01-25 23:52:45 +0000133 printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000134 if (!oddparity(id1))
135 printf_debug(", id1 parity violation");
136 printf_debug("\n");
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000137 if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000138 return 1;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000139
Ollie Lho761bf1b2004-03-20 16:46:10 +0000140 return 0;
Ollie Lho73eca802004-03-19 22:10:07 +0000141}
142
Ollie Lho184a4042005-11-26 21:55:36 +0000143int erase_sector_jedec(volatile uint8_t *bios, unsigned int page)
Ollie Lho73eca802004-03-19 22:10:07 +0000144{
Ollie Lho761bf1b2004-03-20 16:46:10 +0000145 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000146 chip_writeb(0xAA, bios + 0x5555);
Ollie Lho73eca802004-03-19 22:10:07 +0000147 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000148 chip_writeb(0x55, bios + 0x2AAA);
Ollie Lho73eca802004-03-19 22:10:07 +0000149 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000150 chip_writeb(0x80, bios + 0x5555);
Ollie Lho73eca802004-03-19 22:10:07 +0000151 myusec_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000152
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000153 chip_writeb(0xAA, bios + 0x5555);
Ollie Lho73eca802004-03-19 22:10:07 +0000154 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000155 chip_writeb(0x55, bios + 0x2AAA);
Ollie Lho73eca802004-03-19 22:10:07 +0000156 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000157 chip_writeb(0x30, bios + page);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000158 myusec_delay(10);
159
Ollie Lho73eca802004-03-19 22:10:07 +0000160 /* wait for Toggle bit ready */
161 toggle_ready_jedec(bios);
162
Uwe Hermannffec5f32007-08-23 16:08:21 +0000163 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000164}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000165
Ollie Lho184a4042005-11-26 21:55:36 +0000166int erase_block_jedec(volatile uint8_t *bios, unsigned int block)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000167{
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000168 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000169 chip_writeb(0xAA, bios + 0x5555);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000170 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000171 chip_writeb(0x55, bios + 0x2AAA);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000172 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000173 chip_writeb(0x80, bios + 0x5555);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000174 myusec_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000175
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000176 chip_writeb(0xAA, bios + 0x5555);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000177 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000178 chip_writeb(0x55, bios + 0x2AAA);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000179 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000180 chip_writeb(0x50, bios + block);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000181 myusec_delay(10);
182
183 /* wait for Toggle bit ready */
184 toggle_ready_jedec(bios);
185
Uwe Hermannffec5f32007-08-23 16:08:21 +0000186 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000187}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000188
Ollie Lho761bf1b2004-03-20 16:46:10 +0000189int erase_chip_jedec(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000190{
Stefan Reinauerce532972007-05-23 17:20:56 +0000191 volatile uint8_t *bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000192
Ollie Lho761bf1b2004-03-20 16:46:10 +0000193 /* Issue the JEDEC Chip Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000194 chip_writeb(0xAA, bios + 0x5555);
Ronald G. Minnichef5779d2002-01-29 20:18:02 +0000195 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000196 chip_writeb(0x55, bios + 0x2AAA);
Ollie Lho73eca802004-03-19 22:10:07 +0000197 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000198 chip_writeb(0x80, bios + 0x5555);
Ollie Lho73eca802004-03-19 22:10:07 +0000199 myusec_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000200
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000201 chip_writeb(0xAA, bios + 0x5555);
Ollie Lho73eca802004-03-19 22:10:07 +0000202 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000203 chip_writeb(0x55, bios + 0x2AAA);
Ollie Lho73eca802004-03-19 22:10:07 +0000204 myusec_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000205 chip_writeb(0x10, bios + 0x5555);
Ollie Lho73eca802004-03-19 22:10:07 +0000206 myusec_delay(10);
207
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000208 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000209
Uwe Hermannffec5f32007-08-23 16:08:21 +0000210 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000211}
212
Ollie Lho184a4042005-11-26 21:55:36 +0000213int write_page_write_jedec(volatile uint8_t *bios, uint8_t *src,
214 volatile uint8_t *dst, int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000215{
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000216 int i, tried = 0, start_index = 0, ok;
217 volatile uint8_t *d = dst;
218 uint8_t *s = src;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000219
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000220retry:
Ollie Lho761bf1b2004-03-20 16:46:10 +0000221 /* Issue JEDEC Data Unprotect comand */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000222 chip_writeb(0xAA, bios + 0x5555);
223 chip_writeb(0x55, bios + 0x2AAA);
224 chip_writeb(0xA0, bios + 0x5555);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000225
Ollie Lho98bea8a2004-12-07 03:15:51 +0000226 /* transfer data from source to destination */
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000227 for (i = start_index; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000228 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000229 if (*src != 0xFF)
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000230 chip_writeb(*src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000231 dst++;
232 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000233 }
234
Ollie Lho761bf1b2004-03-20 16:46:10 +0000235 toggle_ready_jedec(dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000236
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000237 dst = d;
238 src = s;
239 ok = 1;
240 for (i = 0; i < page_size; i++) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000241 if (chip_readb(dst) != *src) {
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000242 ok = 0;
243 break;
244 }
245 dst++;
246 src++;
247 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000248
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000249 if (!ok && tried++ < MAX_REFLASH_TRIES) {
250 start_index = i;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000251 goto retry;
252 }
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000253 if (!ok) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000254 fprintf(stderr, " page %d failed!\n",
255 (unsigned int)(d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000256 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000257 return !ok;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000258}
259
Ollie Lho184a4042005-11-26 21:55:36 +0000260int write_byte_program_jedec(volatile uint8_t *bios, uint8_t *src,
261 volatile uint8_t *dst)
Ollie Lho070647d2004-03-22 22:19:17 +0000262{
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000263 int tried = 0, ok = 1;
Ollie Lho1b8b6602004-12-08 02:10:33 +0000264
Ollie Lho98bea8a2004-12-07 03:15:51 +0000265 /* If the data is 0xFF, don't program it */
Ollie Lho070647d2004-03-22 22:19:17 +0000266 if (*src == 0xFF) {
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000267 return -1;
Ollie Lho070647d2004-03-22 22:19:17 +0000268 }
Ollie Lho98bea8a2004-12-07 03:15:51 +0000269
Ollie Lho1b8b6602004-12-08 02:10:33 +0000270retry:
Ollie Lho070647d2004-03-22 22:19:17 +0000271 /* Issue JEDEC Byte Program command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000272 chip_writeb(0xAA, bios + 0x5555);
273 chip_writeb(0x55, bios + 0x2AAA);
274 chip_writeb(0xA0, bios + 0x5555);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000275
276 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000277 chip_writeb(*src, dst);
Ollie Lho070647d2004-03-22 22:19:17 +0000278 toggle_ready_jedec(bios);
Ollie Lho8b8897a2004-03-27 00:18:15 +0000279
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000280 if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000281 goto retry;
282 }
Ollie Lho1b8b6602004-12-08 02:10:33 +0000283
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000284 if (tried >= MAX_REFLASH_TRIES)
Uwe Hermanna7e05482007-05-09 10:17:44 +0000285 ok = 0;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000286
Uwe Hermannffec5f32007-08-23 16:08:21 +0000287 return !ok;
Ollie Lho070647d2004-03-22 22:19:17 +0000288}
289
Ollie Lho184a4042005-11-26 21:55:36 +0000290int write_sector_jedec(volatile uint8_t *bios, uint8_t *src,
291 volatile uint8_t *dst, unsigned int page_size)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000292{
293 int i;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000294
295 for (i = 0; i < page_size; i++) {
Ollie Lho8b8897a2004-03-27 00:18:15 +0000296 write_byte_program_jedec(bios, src, dst);
297 dst++, src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000298 }
299
Uwe Hermannffec5f32007-08-23 16:08:21 +0000300 return 0;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000301}
302
Ollie Lho184a4042005-11-26 21:55:36 +0000303int write_jedec(struct flashchip *flash, uint8_t *buf)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000304{
305 int i;
Ollie Lho070647d2004-03-22 22:19:17 +0000306 int total_size = flash->total_size * 1024;
307 int page_size = flash->page_size;
Stefan Reinauerce532972007-05-23 17:20:56 +0000308 volatile uint8_t *bios = flash->virtual_memory;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000309
310 erase_chip_jedec(flash);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000311 // dumb check if erase was successful.
312 for (i = 0; i < total_size; i++) {
313 if (bios[i] != (uint8_t) 0xff) {
Uwe Hermanna502dce2007-10-17 23:55:15 +0000314 printf("ERASE FAILED @%d, val %02x!\n", i, bios[i]);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000315 return -1;
316 }
317 }
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000318
Uwe Hermanna502dce2007-10-17 23:55:15 +0000319 printf("Programming page: ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000320 for (i = 0; i < total_size / page_size; i++) {
321 printf("%04d at address: 0x%08x", i, i * page_size);
Ollie Lho8b8897a2004-03-27 00:18:15 +0000322 write_page_write_jedec(bios, buf + i * page_size,
323 bios + i * page_size, page_size);
Ollie Lho070647d2004-03-22 22:19:17 +0000324 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000325 }
326 printf("\n");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000327 protect_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000328
Uwe Hermannffec5f32007-08-23 16:08:21 +0000329 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000330}