Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 5 | * Copyright (C) 2008 coresystems GmbH |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Contains the generic SPI framework |
| 23 | */ |
| 24 | |
| 25 | #include <stdio.h> |
| 26 | #include <pci/pci.h> |
| 27 | #include <stdint.h> |
| 28 | #include <string.h> |
| 29 | #include "flash.h" |
Carl-Daniel Hailfinger | d6cbf76 | 2008-05-13 14:58:23 +0000 | [diff] [blame] | 30 | #include "spi.h" |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 31 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 32 | void spi_prettyprint_status_register(struct flashchip *flash); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 33 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 34 | int spi_command(unsigned int writecnt, unsigned int readcnt, |
| 35 | const unsigned char *writearr, unsigned char *readarr) |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 36 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 37 | switch (flashbus) { |
| 38 | case BUS_TYPE_IT87XX_SPI: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 39 | return it8716f_spi_command(writecnt, readcnt, writearr, |
| 40 | readarr); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 41 | case BUS_TYPE_ICH7_SPI: |
| 42 | case BUS_TYPE_ICH9_SPI: |
| 43 | case BUS_TYPE_VIA_SPI: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 44 | return ich_spi_command(writecnt, readcnt, writearr, readarr); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 45 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 46 | printf_debug |
| 47 | ("%s called, but no SPI chipset/strapping detected\n", |
| 48 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 49 | } |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 50 | return 1; |
| 51 | } |
| 52 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 53 | static int spi_rdid(unsigned char *readarr, int bytes) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 54 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 55 | const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 56 | |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 57 | if (spi_command(sizeof(cmd), bytes, cmd, readarr)) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 58 | return 1; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 59 | printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], |
| 60 | readarr[2]); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 61 | return 0; |
| 62 | } |
| 63 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 64 | static int spi_res(unsigned char *readarr) |
| 65 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 66 | const unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 67 | |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 68 | if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr)) |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 69 | return 1; |
| 70 | printf_debug("RES returned %02x.\n", readarr[0]); |
| 71 | return 0; |
| 72 | } |
| 73 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 74 | void spi_write_enable() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 75 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 76 | const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 77 | |
| 78 | /* Send WREN (Write Enable) */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 79 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 80 | } |
| 81 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 82 | void spi_write_disable() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 83 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 84 | const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 85 | |
| 86 | /* Send WRDI (Write Disable) */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 87 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 90 | static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 91 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 92 | unsigned char readarr[4]; |
Carl-Daniel Hailfinger | 1263d2a | 2008-02-06 22:07:58 +0000 | [diff] [blame] | 93 | uint32_t manuf_id; |
| 94 | uint32_t model_id; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 95 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 96 | if (spi_rdid(readarr, bytes)) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 97 | return 0; |
| 98 | |
| 99 | if (!oddparity(readarr[0])) |
| 100 | printf_debug("RDID byte 0 parity violation.\n"); |
| 101 | |
| 102 | /* Check if this is a continuation vendor ID */ |
| 103 | if (readarr[0] == 0x7f) { |
| 104 | if (!oddparity(readarr[1])) |
| 105 | printf_debug("RDID byte 1 parity violation.\n"); |
| 106 | manuf_id = (readarr[0] << 8) | readarr[1]; |
| 107 | model_id = readarr[2]; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 108 | if (bytes > 3) { |
| 109 | model_id <<= 8; |
| 110 | model_id |= readarr[3]; |
| 111 | } |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 112 | } else { |
| 113 | manuf_id = readarr[0]; |
| 114 | model_id = (readarr[1] << 8) | readarr[2]; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 115 | } |
| 116 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 117 | printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, |
| 118 | model_id); |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 119 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 120 | if (manuf_id == flash->manufacture_id && model_id == flash->model_id) { |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 121 | /* Print the status register to tell the |
| 122 | * user about possible write protection. |
| 123 | */ |
| 124 | spi_prettyprint_status_register(flash); |
| 125 | |
| 126 | return 1; |
| 127 | } |
| 128 | |
| 129 | /* Test if this is a pure vendor match. */ |
| 130 | if (manuf_id == flash->manufacture_id && |
| 131 | GENERIC_DEVICE_ID == flash->model_id) |
| 132 | return 1; |
| 133 | |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 134 | return 0; |
| 135 | } |
| 136 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 137 | int probe_spi_rdid(struct flashchip *flash) |
| 138 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 139 | return probe_spi_rdid_generic(flash, 3); |
| 140 | } |
| 141 | |
| 142 | /* support 4 bytes flash ID */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 143 | int probe_spi_rdid4(struct flashchip *flash) |
| 144 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 145 | /* only some SPI chipsets support 4 bytes commands */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 146 | switch (flashbus) { |
| 147 | case BUS_TYPE_ICH7_SPI: |
| 148 | case BUS_TYPE_ICH9_SPI: |
| 149 | case BUS_TYPE_VIA_SPI: |
| 150 | return probe_spi_rdid_generic(flash, 4); |
| 151 | default: |
| 152 | printf_debug("4b ID not supported on this SPI controller\n"); |
| 153 | } |
| 154 | |
| 155 | return 0; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 156 | } |
| 157 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 158 | int probe_spi_res(struct flashchip *flash) |
| 159 | { |
| 160 | unsigned char readarr[3]; |
| 161 | uint32_t model_id; |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 162 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 163 | if (spi_rdid(readarr, 3)) |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 164 | /* We couldn't issue RDID, it's pointless to try RES. */ |
| 165 | return 0; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 166 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 167 | /* Check if RDID returns 0xff 0xff 0xff, then we use RES. */ |
| 168 | if ((readarr[0] != 0xff) || (readarr[1] != 0xff) || |
| 169 | (readarr[2] != 0xff)) |
| 170 | return 0; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 171 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 172 | if (spi_res(readarr)) |
| 173 | return 0; |
| 174 | |
| 175 | model_id = readarr[0]; |
| 176 | printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id); |
| 177 | if (model_id != flash->model_id) |
| 178 | return 0; |
| 179 | |
| 180 | /* Print the status register to tell the |
| 181 | * user about possible write protection. |
| 182 | */ |
| 183 | spi_prettyprint_status_register(flash); |
| 184 | return 1; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 185 | } |
| 186 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 187 | uint8_t spi_read_status_register() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 188 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 189 | const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 190 | unsigned char readarr[JEDEC_RDSR_INSIZE]; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 191 | |
| 192 | /* Read Status Register */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 193 | spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 194 | return readarr[0]; |
| 195 | } |
| 196 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 197 | /* Prettyprint the status register. Common definitions. |
| 198 | */ |
| 199 | void spi_prettyprint_status_register_common(uint8_t status) |
| 200 | { |
| 201 | printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 202 | "%sset\n", (status & (1 << 5)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 203 | printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 204 | "%sset\n", (status & (1 << 4)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 205 | printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 206 | "%sset\n", (status & (1 << 3)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 207 | printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 208 | "%sset\n", (status & (1 << 2)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 209 | printf_debug("Chip status register: Write Enable Latch (WEL) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 210 | "%sset\n", (status & (1 << 1)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 211 | printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 212 | "%sset\n", (status & (1 << 0)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 213 | } |
| 214 | |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 215 | /* Prettyprint the status register. Works for |
| 216 | * ST M25P series |
| 217 | * MX MX25L series |
| 218 | */ |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 219 | void spi_prettyprint_status_register_st_m25p(uint8_t status) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 220 | { |
| 221 | printf_debug("Chip status register: Status Register Write Disable " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 222 | "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 223 | printf_debug("Chip status register: Bit 6 is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 224 | "%sset\n", (status & (1 << 6)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 225 | spi_prettyprint_status_register_common(status); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 226 | } |
| 227 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 228 | /* Prettyprint the status register. Works for |
| 229 | * SST 25VF016 |
| 230 | */ |
| 231 | void spi_prettyprint_status_register_sst25vf016(uint8_t status) |
| 232 | { |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 233 | const char *bpt[] = { |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 234 | "none", |
| 235 | "1F0000H-1FFFFFH", |
| 236 | "1E0000H-1FFFFFH", |
| 237 | "1C0000H-1FFFFFH", |
| 238 | "180000H-1FFFFFH", |
| 239 | "100000H-1FFFFFH", |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 240 | "all", "all" |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 241 | }; |
| 242 | printf_debug("Chip status register: Block Protect Write Disable " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 243 | "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 244 | printf_debug("Chip status register: Auto Address Increment Programming " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 245 | "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 246 | spi_prettyprint_status_register_common(status); |
| 247 | printf_debug("Resulting block protection : %s\n", |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 248 | bpt[(status & 0x1c) >> 2]); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | void spi_prettyprint_status_register(struct flashchip *flash) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 252 | { |
| 253 | uint8_t status; |
| 254 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 255 | status = spi_read_status_register(); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 256 | printf_debug("Chip status register is %02x\n", status); |
| 257 | switch (flash->manufacture_id) { |
| 258 | case ST_ID: |
Carl-Daniel Hailfinger | f43e642 | 2008-05-15 22:32:08 +0000 | [diff] [blame] | 259 | if (((flash->model_id & 0xff00) == 0x2000) || |
| 260 | ((flash->model_id & 0xff00) == 0x2500)) |
| 261 | spi_prettyprint_status_register_st_m25p(status); |
| 262 | break; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 263 | case MX_ID: |
| 264 | if ((flash->model_id & 0xff00) == 0x2000) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 265 | spi_prettyprint_status_register_st_m25p(status); |
| 266 | break; |
| 267 | case SST_ID: |
| 268 | if (flash->model_id == SST_25VF016B) |
| 269 | spi_prettyprint_status_register_sst25vf016(status); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 270 | break; |
| 271 | } |
| 272 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 273 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 274 | int spi_chip_erase_c7(struct flashchip *flash) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 275 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 276 | const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; |
| 277 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 278 | spi_disable_blockprotect(); |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 279 | spi_write_enable(); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 280 | /* Send CE (Chip Erase) */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 281 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 282 | /* Wait until the Write-In-Progress bit is cleared. |
| 283 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 284 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 285 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 286 | sleep(1); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 287 | return 0; |
| 288 | } |
| 289 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 290 | /* Block size is usually |
| 291 | * 64k for Macronix |
| 292 | * 32k for SST |
| 293 | * 4-32k non-uniform for EON |
| 294 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 295 | int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 296 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 297 | unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 }; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 298 | |
| 299 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 300 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 301 | cmd[3] = (addr & 0x000000ff); |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 302 | spi_write_enable(); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 303 | /* Send BE (Block Erase) */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 304 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 305 | /* Wait until the Write-In-Progress bit is cleared. |
| 306 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 307 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 308 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 309 | usleep(100 * 1000); |
| 310 | return 0; |
| 311 | } |
| 312 | |
Stefan Reinauer | 424ed22 | 2008-10-29 22:13:20 +0000 | [diff] [blame] | 313 | int spi_chip_erase_d8(struct flashchip *flash) |
| 314 | { |
| 315 | int i, rc = 0; |
| 316 | int total_size = flash->total_size * 1024; |
| 317 | int erase_size = 64 * 1024; |
| 318 | |
| 319 | spi_disable_blockprotect(); |
| 320 | |
| 321 | printf("Erasing chip: \n"); |
| 322 | |
| 323 | for (i = 0; i < total_size / erase_size; i++) { |
| 324 | rc = spi_block_erase_d8(flash, i * erase_size); |
| 325 | if (rc) { |
| 326 | printf("Error erasing block at 0x%x\n", i); |
| 327 | break; |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | printf("\n"); |
| 332 | |
| 333 | return rc; |
| 334 | } |
| 335 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 336 | /* Sector size is usually 4k, though Macronix eliteflash has 64k */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 337 | int spi_sector_erase(const struct flashchip *flash, unsigned long addr) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 338 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 339 | unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE }; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 340 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 341 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 342 | cmd[3] = (addr & 0x000000ff); |
| 343 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 344 | spi_write_enable(); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 345 | /* Send SE (Sector Erase) */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 346 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 347 | /* Wait until the Write-In-Progress bit is cleared. |
| 348 | * This usually takes 15-800 ms, so wait in 10 ms steps. |
| 349 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 350 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 351 | usleep(10 * 1000); |
| 352 | return 0; |
| 353 | } |
| 354 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 355 | /* |
| 356 | * This is according the SST25VF016 datasheet, who knows it is more |
| 357 | * generic that this... |
| 358 | */ |
| 359 | void spi_write_status_register(int status) |
| 360 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 361 | const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = |
| 362 | { JEDEC_WRSR, (unsigned char)status }; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 363 | |
| 364 | /* Send WRSR (Write Status Register) */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 365 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | void spi_byte_program(int address, uint8_t byte) |
| 369 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 370 | const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = { |
| 371 | JEDEC_BYTE_PROGRAM, |
| 372 | (address >> 16) & 0xff, |
| 373 | (address >> 8) & 0xff, |
| 374 | (address >> 0) & 0xff, |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 375 | byte |
| 376 | }; |
| 377 | |
| 378 | /* Send Byte-Program */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 379 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 380 | } |
| 381 | |
| 382 | void spi_disable_blockprotect(void) |
| 383 | { |
| 384 | uint8_t status; |
| 385 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 386 | status = spi_read_status_register(); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 387 | /* If there is block protection in effect, unprotect it first. */ |
| 388 | if ((status & 0x3c) != 0) { |
| 389 | printf_debug("Some block protection in effect, disabling\n"); |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 390 | spi_write_enable(); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 391 | spi_write_status_register(status & ~0x3c); |
| 392 | } |
| 393 | } |
| 394 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 395 | void spi_nbyte_read(int address, uint8_t *bytes, int len) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 396 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 397 | const unsigned char cmd[JEDEC_READ_OUTSIZE] = { |
| 398 | JEDEC_READ, |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 399 | (address >> 16) & 0xff, |
| 400 | (address >> 8) & 0xff, |
| 401 | (address >> 0) & 0xff, |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 402 | }; |
| 403 | |
| 404 | /* Send Read */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 405 | spi_command(sizeof(cmd), len, cmd, bytes); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 406 | } |
| 407 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 408 | int spi_chip_read(struct flashchip *flash, uint8_t *buf) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 409 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 410 | switch (flashbus) { |
| 411 | case BUS_TYPE_IT87XX_SPI: |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 412 | return it8716f_spi_chip_read(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 413 | case BUS_TYPE_ICH7_SPI: |
| 414 | case BUS_TYPE_ICH9_SPI: |
| 415 | case BUS_TYPE_VIA_SPI: |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 416 | return ich_spi_read(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 417 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 418 | printf_debug |
| 419 | ("%s called, but no SPI chipset/strapping detected\n", |
| 420 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 421 | } |
| 422 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 423 | return 1; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 424 | } |
| 425 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 426 | int spi_chip_write(struct flashchip *flash, uint8_t *buf) |
| 427 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 428 | switch (flashbus) { |
| 429 | case BUS_TYPE_IT87XX_SPI: |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 430 | return it8716f_spi_chip_write(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 431 | case BUS_TYPE_ICH7_SPI: |
| 432 | case BUS_TYPE_ICH9_SPI: |
| 433 | case BUS_TYPE_VIA_SPI: |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 434 | return ich_spi_write(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 435 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 436 | printf_debug |
| 437 | ("%s called, but no SPI chipset/strapping detected\n", |
| 438 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 439 | } |
| 440 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 441 | return 1; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 442 | } |