blob: 7a17b2475f65c395bb24bd39627a69dfc341398f [file] [log] [blame]
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000025#include <string.h>
26#include "flash.h"
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000027#include "flashchips.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000028#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000029
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000030enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
31void *spibar = NULL;
32
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +000033void spi_prettyprint_status_register(struct flashchip *flash);
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000034
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000035const struct spi_programmer spi_programmer[] = {
36 { /* SPI_CONTROLLER_NONE */
37 .command = NULL,
38 .multicommand = NULL,
39 .read = NULL,
40 .write_256 = NULL,
41 },
42
43 { /* SPI_CONTROLLER_ICH7 */
44 .command = ich_spi_send_command,
45 .multicommand = ich_spi_send_multicommand,
46 .read = ich_spi_read,
47 .write_256 = ich_spi_write_256,
48 },
49
50 { /* SPI_CONTROLLER_ICH9 */
51 .command = ich_spi_send_command,
52 .multicommand = ich_spi_send_multicommand,
53 .read = ich_spi_read,
54 .write_256 = ich_spi_write_256,
55 },
56
57 { /* SPI_CONTROLLER_IT87XX */
58 .command = it8716f_spi_send_command,
59 .multicommand = default_spi_send_multicommand,
60 .read = it8716f_spi_chip_read,
61 .write_256 = it8716f_spi_chip_write_256,
62 },
63
64 { /* SPI_CONTROLLER_SB600 */
65 .command = sb600_spi_send_command,
66 .multicommand = default_spi_send_multicommand,
67 .read = sb600_spi_read,
68 .write_256 = sb600_spi_write_1,
69 },
70
71 { /* SPI_CONTROLLER_VIA */
72 .command = ich_spi_send_command,
73 .multicommand = ich_spi_send_multicommand,
74 .read = ich_spi_read,
75 .write_256 = ich_spi_write_256,
76 },
77
78 { /* SPI_CONTROLLER_WBSIO */
79 .command = wbsio_spi_send_command,
80 .multicommand = default_spi_send_multicommand,
81 .read = wbsio_spi_read,
82 .write_256 = wbsio_spi_write_1,
83 },
84
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +000085#if FT2232_SPI_SUPPORT == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000086 { /* SPI_CONTROLLER_FT2232 */
87 .command = ft2232_spi_send_command,
88 .multicommand = default_spi_send_multicommand,
89 .read = ft2232_spi_read,
90 .write_256 = ft2232_spi_write_256,
91 },
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +000092#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000093
94 { /* SPI_CONTROLLER_DUMMY */
95 .command = dummy_spi_send_command,
96 .multicommand = default_spi_send_multicommand,
97 .read = NULL,
98 .write_256 = NULL,
99 },
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000100
101 {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000102};
103
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000104const int spi_programmer_count = ARRAY_SIZE(spi_programmer);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000105
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000106int spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000107 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000108{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000109 if (!spi_programmer[spi_controller].command) {
110 fprintf(stderr, "%s called, but SPI is unsupported on this "
111 "hardware. Please report a bug.\n", __func__);
112 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000113 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000114
115 return spi_programmer[spi_controller].command(writecnt, readcnt,
116 writearr, readarr);
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000117}
118
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000119int spi_send_multicommand(struct spi_command *spicommands)
120{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000121 if (!spi_programmer[spi_controller].multicommand) {
122 fprintf(stderr, "%s called, but SPI is unsupported on this "
123 "hardware. Please report a bug.\n", __func__);
124 return 1;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000125 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000126
127 return spi_programmer[spi_controller].multicommand(spicommands);
128}
129
130int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
131 const unsigned char *writearr, unsigned char *readarr)
132{
133 struct spi_command cmd[] = {
134 {
135 .writecnt = writecnt,
136 .readcnt = readcnt,
137 .writearr = writearr,
138 .readarr = readarr,
139 }, {
140 .writecnt = 0,
141 .writearr = NULL,
142 .readcnt = 0,
143 .readarr = NULL,
144 }};
145
146 return spi_send_multicommand(cmd);
147}
148
149int default_spi_send_multicommand(struct spi_command *spicommands)
150{
151 int result = 0;
152 while ((spicommands->writecnt || spicommands->readcnt) && !result) {
153 result = spi_send_command(spicommands->writecnt, spicommands->readcnt,
154 spicommands->writearr, spicommands->readarr);
Carl-Daniel Hailfinger5b2f52f2009-08-03 09:35:20 +0000155 spicommands++;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000156 }
157 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000158}
159
Rudolf Marek48a85e42008-06-30 21:45:17 +0000160static int spi_rdid(unsigned char *readarr, int bytes)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000161{
Uwe Hermann394131e2008-10-18 21:14:13 +0000162 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000163 int ret;
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +0000164 int i;
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000165
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000166 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000167 if (ret)
168 return ret;
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +0000169 printf_debug("RDID returned");
170 for (i = 0; i < bytes; i++)
171 printf_debug(" 0x%02x", readarr[i]);
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000172 printf_debug(". ");
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000173 return 0;
174}
175
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000176static int spi_rems(unsigned char *readarr)
177{
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000178 unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
179 uint32_t readaddr;
180 int ret;
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000181
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000182 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000183 if (ret == SPI_INVALID_ADDRESS) {
184 /* Find the lowest even address allowed for reads. */
185 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
186 cmd[1] = (readaddr >> 16) & 0xff,
187 cmd[2] = (readaddr >> 8) & 0xff,
188 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000189 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000190 }
191 if (ret)
192 return ret;
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000193 printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]);
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000194 return 0;
195}
196
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000197static int spi_res(unsigned char *readarr)
198{
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000199 unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
200 uint32_t readaddr;
201 int ret;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000202
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000203 ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000204 if (ret == SPI_INVALID_ADDRESS) {
205 /* Find the lowest even address allowed for reads. */
206 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
207 cmd[1] = (readaddr >> 16) & 0xff,
208 cmd[2] = (readaddr >> 8) & 0xff,
209 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000210 ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000211 }
212 if (ret)
213 return ret;
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000214 printf_debug("RES returned %02x. ", readarr[0]);
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000215 return 0;
216}
217
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000218int spi_write_enable(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000219{
Uwe Hermann394131e2008-10-18 21:14:13 +0000220 const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000221 int result;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000222
223 /* Send WREN (Write Enable) */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000224 result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000225
226 if (result)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000227 fprintf(stderr, "%s failed\n", __func__);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000228
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000229 return result;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000230}
231
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000232int spi_write_disable(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000233{
Uwe Hermann394131e2008-10-18 21:14:13 +0000234 const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000235
236 /* Send WRDI (Write Disable) */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000237 return spi_send_command(sizeof(cmd), 0, cmd, NULL);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000238}
239
Rudolf Marek48a85e42008-06-30 21:45:17 +0000240static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000241{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000242 unsigned char readarr[4];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000243 uint32_t id1;
244 uint32_t id2;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000245
Rudolf Marek48a85e42008-06-30 21:45:17 +0000246 if (spi_rdid(readarr, bytes))
Peter Stugeda4e5f32008-06-24 01:22:03 +0000247 return 0;
248
249 if (!oddparity(readarr[0]))
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000250 printf_debug("RDID byte 0 parity violation. ");
Peter Stugeda4e5f32008-06-24 01:22:03 +0000251
252 /* Check if this is a continuation vendor ID */
253 if (readarr[0] == 0x7f) {
254 if (!oddparity(readarr[1]))
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000255 printf_debug("RDID byte 1 parity violation. ");
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000256 id1 = (readarr[0] << 8) | readarr[1];
257 id2 = readarr[2];
Rudolf Marek48a85e42008-06-30 21:45:17 +0000258 if (bytes > 3) {
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000259 id2 <<= 8;
260 id2 |= readarr[3];
Rudolf Marek48a85e42008-06-30 21:45:17 +0000261 }
Peter Stugeda4e5f32008-06-24 01:22:03 +0000262 } else {
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000263 id1 = readarr[0];
264 id2 = (readarr[1] << 8) | readarr[2];
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000265 }
266
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000267 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Peter Stugeda4e5f32008-06-24 01:22:03 +0000268
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000269 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
Peter Stugeda4e5f32008-06-24 01:22:03 +0000270 /* Print the status register to tell the
271 * user about possible write protection.
272 */
273 spi_prettyprint_status_register(flash);
274
275 return 1;
276 }
277
278 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000279 if (id1 == flash->manufacture_id &&
Peter Stugeda4e5f32008-06-24 01:22:03 +0000280 GENERIC_DEVICE_ID == flash->model_id)
281 return 1;
282
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000283 return 0;
284}
285
Uwe Hermann394131e2008-10-18 21:14:13 +0000286int probe_spi_rdid(struct flashchip *flash)
287{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000288 return probe_spi_rdid_generic(flash, 3);
289}
290
291/* support 4 bytes flash ID */
Uwe Hermann394131e2008-10-18 21:14:13 +0000292int probe_spi_rdid4(struct flashchip *flash)
293{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000294 /* only some SPI chipsets support 4 bytes commands */
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000295 switch (spi_controller) {
296 case SPI_CONTROLLER_ICH7:
297 case SPI_CONTROLLER_ICH9:
298 case SPI_CONTROLLER_VIA:
299 case SPI_CONTROLLER_SB600:
300 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000301#if FT2232_SPI_SUPPORT == 1
Paul Fox05dfbe62009-06-16 21:08:06 +0000302 case SPI_CONTROLLER_FT2232:
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000303#endif
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000304 case SPI_CONTROLLER_DUMMY:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000305 return probe_spi_rdid_generic(flash, 4);
306 default:
307 printf_debug("4b ID not supported on this SPI controller\n");
308 }
309
310 return 0;
Rudolf Marek48a85e42008-06-30 21:45:17 +0000311}
312
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000313int probe_spi_rems(struct flashchip *flash)
314{
315 unsigned char readarr[JEDEC_REMS_INSIZE];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000316 uint32_t id1, id2;
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000317
318 if (spi_rems(readarr))
319 return 0;
320
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000321 id1 = readarr[0];
322 id2 = readarr[1];
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000323
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000324 printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000325
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000326 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000327 /* Print the status register to tell the
328 * user about possible write protection.
329 */
330 spi_prettyprint_status_register(flash);
331
332 return 1;
333 }
334
335 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000336 if (id1 == flash->manufacture_id &&
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000337 GENERIC_DEVICE_ID == flash->model_id)
338 return 1;
339
340 return 0;
341}
342
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000343int probe_spi_res(struct flashchip *flash)
344{
345 unsigned char readarr[3];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000346 uint32_t id2;
Peter Stugeda4e5f32008-06-24 01:22:03 +0000347
Carl-Daniel Hailfinger92a54ca2008-11-27 22:48:48 +0000348 /* Check if RDID was successful and did not return 0xff 0xff 0xff.
349 * In that case, RES is pointless.
350 */
351 if (!spi_rdid(readarr, 3) && ((readarr[0] != 0xff) ||
352 (readarr[1] != 0xff) || (readarr[2] != 0xff)))
Peter Stugeda4e5f32008-06-24 01:22:03 +0000353 return 0;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000354
Peter Stugeda4e5f32008-06-24 01:22:03 +0000355 if (spi_res(readarr))
356 return 0;
357
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000358 id2 = readarr[0];
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000359 printf_debug("%s: id 0x%x\n", __func__, id2);
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000360 if (id2 != flash->model_id)
Peter Stugeda4e5f32008-06-24 01:22:03 +0000361 return 0;
362
363 /* Print the status register to tell the
364 * user about possible write protection.
365 */
366 spi_prettyprint_status_register(flash);
367 return 1;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000368}
369
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000370uint8_t spi_read_status_register(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000371{
Uwe Hermann394131e2008-10-18 21:14:13 +0000372 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000373 /* FIXME: No workarounds for driver/hardware bugs in generic code. */
Peter Stugebf196e92009-01-26 03:08:45 +0000374 unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000375 int ret;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000376
377 /* Read Status Register */
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000378 ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
379 if (ret)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000380 fprintf(stderr, "RDSR failed!\n");
Jason Wanga3f04be2008-11-28 21:36:51 +0000381
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000382 return readarr[0];
383}
384
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000385/* Prettyprint the status register. Common definitions. */
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000386void spi_prettyprint_status_register_common(uint8_t status)
387{
388 printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000389 "%sset\n", (status & (1 << 5)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000390 printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000391 "%sset\n", (status & (1 << 4)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000392 printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000393 "%sset\n", (status & (1 << 3)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000394 printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000395 "%sset\n", (status & (1 << 2)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000396 printf_debug("Chip status register: Write Enable Latch (WEL) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000397 "%sset\n", (status & (1 << 1)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000398 printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000399 "%sset\n", (status & (1 << 0)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000400}
401
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000402/* Prettyprint the status register. Works for
403 * ST M25P series
404 * MX MX25L series
405 */
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000406void spi_prettyprint_status_register_st_m25p(uint8_t status)
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000407{
408 printf_debug("Chip status register: Status Register Write Disable "
Uwe Hermann394131e2008-10-18 21:14:13 +0000409 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000410 printf_debug("Chip status register: Bit 6 is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000411 "%sset\n", (status & (1 << 6)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000412 spi_prettyprint_status_register_common(status);
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000413}
414
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000415void spi_prettyprint_status_register_sst25(uint8_t status)
416{
417 printf_debug("Chip status register: Block Protect Write Disable "
418 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
419 printf_debug("Chip status register: Auto Address Increment Programming "
420 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
421 spi_prettyprint_status_register_common(status);
422}
423
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000424/* Prettyprint the status register. Works for
425 * SST 25VF016
426 */
427void spi_prettyprint_status_register_sst25vf016(uint8_t status)
428{
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000429 const char *bpt[] = {
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000430 "none",
431 "1F0000H-1FFFFFH",
432 "1E0000H-1FFFFFH",
433 "1C0000H-1FFFFFH",
434 "180000H-1FFFFFH",
435 "100000H-1FFFFFH",
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000436 "all", "all"
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000437 };
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000438 spi_prettyprint_status_register_sst25(status);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000439 printf_debug("Resulting block protection : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000440 bpt[(status & 0x1c) >> 2]);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000441}
442
Peter Stuge5fecee42009-01-26 03:23:50 +0000443void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
444{
445 const char *bpt[] = {
446 "none",
447 "0x70000-0x7ffff",
448 "0x60000-0x7ffff",
449 "0x40000-0x7ffff",
450 "all blocks", "all blocks", "all blocks", "all blocks"
451 };
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000452 spi_prettyprint_status_register_sst25(status);
Peter Stuge5fecee42009-01-26 03:23:50 +0000453 printf_debug("Resulting block protection : %s\n",
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000454 bpt[(status & 0x1c) >> 2]);
Peter Stuge5fecee42009-01-26 03:23:50 +0000455}
456
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000457void spi_prettyprint_status_register(struct flashchip *flash)
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000458{
459 uint8_t status;
460
Peter Stugefa8c5502008-05-10 23:07:52 +0000461 status = spi_read_status_register();
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000462 printf_debug("Chip status register is %02x\n", status);
463 switch (flash->manufacture_id) {
464 case ST_ID:
Carl-Daniel Hailfingerf43e6422008-05-15 22:32:08 +0000465 if (((flash->model_id & 0xff00) == 0x2000) ||
466 ((flash->model_id & 0xff00) == 0x2500))
467 spi_prettyprint_status_register_st_m25p(status);
468 break;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000469 case MX_ID:
470 if ((flash->model_id & 0xff00) == 0x2000)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000471 spi_prettyprint_status_register_st_m25p(status);
472 break;
473 case SST_ID:
Peter Stuge5fecee42009-01-26 03:23:50 +0000474 switch (flash->model_id) {
475 case 0x2541:
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000476 spi_prettyprint_status_register_sst25vf016(status);
Peter Stuge5fecee42009-01-26 03:23:50 +0000477 break;
478 case 0x8d:
479 case 0x258d:
480 spi_prettyprint_status_register_sst25vf040b(status);
481 break;
Carl-Daniel Hailfinger5100a8a2009-05-13 22:51:27 +0000482 default:
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000483 spi_prettyprint_status_register_sst25(status);
484 break;
Peter Stuge5fecee42009-01-26 03:23:50 +0000485 }
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000486 break;
487 }
488}
Uwe Hermann394131e2008-10-18 21:14:13 +0000489
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000490int spi_chip_erase_60(struct flashchip *flash)
491{
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000492 int result;
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000493 struct spi_command spicommands[] = {
494 {
495 .writecnt = JEDEC_WREN_OUTSIZE,
496 .writearr = (const unsigned char[]){ JEDEC_WREN },
497 .readcnt = 0,
498 .readarr = NULL,
499 }, {
500 .writecnt = JEDEC_CE_60_OUTSIZE,
501 .writearr = (const unsigned char[]){ JEDEC_CE_60 },
502 .readcnt = 0,
503 .readarr = NULL,
504 }, {
505 .writecnt = 0,
506 .writearr = NULL,
507 .readcnt = 0,
508 .readarr = NULL,
509 }};
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000510
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000511 result = spi_disable_blockprotect();
512 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000513 fprintf(stderr, "spi_disable_blockprotect failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000514 return result;
515 }
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000516
517 result = spi_send_multicommand(spicommands);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000518 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000519 fprintf(stderr, "%s failed during command execution\n",
520 __func__);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000521 return result;
522 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000523 /* Wait until the Write-In-Progress bit is cleared.
524 * This usually takes 1-85 s, so wait in 1 s steps.
525 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000526 /* FIXME: We assume spi_read_status_register will never fail. */
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000527 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000528 programmer_delay(1000 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000529 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
530 fprintf(stderr, "ERASE FAILED!\n");
531 return -1;
532 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000533 return 0;
534}
535
Peter Stugefa8c5502008-05-10 23:07:52 +0000536int spi_chip_erase_c7(struct flashchip *flash)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000537{
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000538 int result;
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000539 struct spi_command spicommands[] = {
540 {
541 .writecnt = JEDEC_WREN_OUTSIZE,
542 .writearr = (const unsigned char[]){ JEDEC_WREN },
543 .readcnt = 0,
544 .readarr = NULL,
545 }, {
546 .writecnt = JEDEC_CE_C7_OUTSIZE,
547 .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
548 .readcnt = 0,
549 .readarr = NULL,
550 }, {
551 .writecnt = 0,
552 .writearr = NULL,
553 .readcnt = 0,
554 .readarr = NULL,
555 }};
Uwe Hermann394131e2008-10-18 21:14:13 +0000556
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000557 result = spi_disable_blockprotect();
558 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000559 fprintf(stderr, "spi_disable_blockprotect failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000560 return result;
561 }
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000562
563 result = spi_send_multicommand(spicommands);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000564 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000565 fprintf(stderr, "%s failed during command execution\n", __func__);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000566 return result;
567 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000568 /* Wait until the Write-In-Progress bit is cleared.
569 * This usually takes 1-85 s, so wait in 1 s steps.
570 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000571 /* FIXME: We assume spi_read_status_register will never fail. */
Peter Stugefa8c5502008-05-10 23:07:52 +0000572 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000573 programmer_delay(1000 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000574 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
575 fprintf(stderr, "ERASE FAILED!\n");
576 return -1;
577 }
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000578 return 0;
579}
580
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000581int spi_chip_erase_60_c7(struct flashchip *flash)
582{
583 int result;
584 result = spi_chip_erase_60(flash);
585 if (result) {
586 printf_debug("spi_chip_erase_60 failed, trying c7\n");
587 result = spi_chip_erase_c7(flash);
588 }
589 return result;
590}
591
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000592int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000593{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000594 int result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000595 struct spi_command spicommands[] = {
596 {
597 .writecnt = JEDEC_WREN_OUTSIZE,
598 .writearr = (const unsigned char[]){ JEDEC_WREN },
599 .readcnt = 0,
600 .readarr = NULL,
601 }, {
602 .writecnt = JEDEC_BE_52_OUTSIZE,
603 .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
604 .readcnt = 0,
605 .readarr = NULL,
606 }, {
607 .writecnt = 0,
608 .writearr = NULL,
609 .readcnt = 0,
610 .readarr = NULL,
611 }};
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000612
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000613 result = spi_send_multicommand(spicommands);
614 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000615 fprintf(stderr, "%s failed during command execution\n",
616 __func__);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000617 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000618 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000619 /* Wait until the Write-In-Progress bit is cleared.
620 * This usually takes 100-4000 ms, so wait in 100 ms steps.
621 */
622 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000623 programmer_delay(100 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000624 if (check_erased_range(flash, addr, blocklen)) {
625 fprintf(stderr, "ERASE FAILED!\n");
626 return -1;
627 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000628 return 0;
629}
630
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000631/* Block size is usually
632 * 64k for Macronix
633 * 32k for SST
634 * 4-32k non-uniform for EON
635 */
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000636int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000637{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000638 int result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000639 struct spi_command spicommands[] = {
640 {
641 .writecnt = JEDEC_WREN_OUTSIZE,
642 .writearr = (const unsigned char[]){ JEDEC_WREN },
643 .readcnt = 0,
644 .readarr = NULL,
645 }, {
646 .writecnt = JEDEC_BE_D8_OUTSIZE,
647 .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
648 .readcnt = 0,
649 .readarr = NULL,
650 }, {
651 .writecnt = 0,
652 .writearr = NULL,
653 .readcnt = 0,
654 .readarr = NULL,
655 }};
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000656
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000657 result = spi_send_multicommand(spicommands);
658 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000659 fprintf(stderr, "%s failed during command execution\n", __func__);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000660 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000661 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000662 /* Wait until the Write-In-Progress bit is cleared.
663 * This usually takes 100-4000 ms, so wait in 100 ms steps.
664 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000665 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000666 programmer_delay(100 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000667 if (check_erased_range(flash, addr, blocklen)) {
668 fprintf(stderr, "ERASE FAILED!\n");
669 return -1;
670 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000671 return 0;
672}
673
Stefan Reinauer424ed222008-10-29 22:13:20 +0000674int spi_chip_erase_d8(struct flashchip *flash)
675{
676 int i, rc = 0;
677 int total_size = flash->total_size * 1024;
678 int erase_size = 64 * 1024;
679
680 spi_disable_blockprotect();
681
682 printf("Erasing chip: \n");
683
684 for (i = 0; i < total_size / erase_size; i++) {
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000685 rc = spi_block_erase_d8(flash, i * erase_size, erase_size);
Stefan Reinauer424ed222008-10-29 22:13:20 +0000686 if (rc) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000687 fprintf(stderr, "Error erasing block at 0x%x\n", i);
Stefan Reinauer424ed222008-10-29 22:13:20 +0000688 break;
689 }
690 }
691
692 printf("\n");
693
694 return rc;
695}
696
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000697/* Sector size is usually 4k, though Macronix eliteflash has 64k */
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000698int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000699{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000700 int result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000701 struct spi_command spicommands[] = {
702 {
703 .writecnt = JEDEC_WREN_OUTSIZE,
704 .writearr = (const unsigned char[]){ JEDEC_WREN },
705 .readcnt = 0,
706 .readarr = NULL,
707 }, {
708 .writecnt = JEDEC_SE_OUTSIZE,
709 .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
710 .readcnt = 0,
711 .readarr = NULL,
712 }, {
713 .writecnt = 0,
714 .writearr = NULL,
715 .readcnt = 0,
716 .readarr = NULL,
717 }};
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000718
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000719 result = spi_send_multicommand(spicommands);
720 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000721 fprintf(stderr, "%s failed during command execution\n",
722 __func__);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000723 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000724 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000725 /* Wait until the Write-In-Progress bit is cleared.
726 * This usually takes 15-800 ms, so wait in 10 ms steps.
727 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000728 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000729 programmer_delay(10 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000730 if (check_erased_range(flash, addr, blocklen)) {
731 fprintf(stderr, "ERASE FAILED!\n");
732 return -1;
733 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000734 return 0;
735}
736
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000737int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
738{
739 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000740 fprintf(stderr, "%s called with incorrect arguments\n",
741 __func__);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000742 return -1;
743 }
744 return spi_chip_erase_60(flash);
745}
746
747int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
748{
749 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000750 fprintf(stderr, "%s called with incorrect arguments\n",
751 __func__);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000752 return -1;
753 }
754 return spi_chip_erase_c7(flash);
755}
756
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000757int spi_write_status_enable(void)
Jason Wanga3f04be2008-11-28 21:36:51 +0000758{
759 const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000760 int result;
Jason Wanga3f04be2008-11-28 21:36:51 +0000761
762 /* Send EWSR (Enable Write Status Register). */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000763 result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000764
765 if (result)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000766 fprintf(stderr, "%s failed\n", __func__);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000767
768 return result;
Jason Wanga3f04be2008-11-28 21:36:51 +0000769}
770
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000771/*
772 * This is according the SST25VF016 datasheet, who knows it is more
773 * generic that this...
774 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000775int spi_write_status_register(int status)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000776{
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000777 int result;
778 struct spi_command spicommands[] = {
779 {
780 .writecnt = JEDEC_EWSR_OUTSIZE,
781 .writearr = (const unsigned char[]){ JEDEC_EWSR },
782 .readcnt = 0,
783 .readarr = NULL,
784 }, {
785 .writecnt = JEDEC_WRSR_OUTSIZE,
786 .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
787 .readcnt = 0,
788 .readarr = NULL,
789 }, {
790 .writecnt = 0,
791 .writearr = NULL,
792 .readcnt = 0,
793 .readarr = NULL,
794 }};
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000795
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000796 result = spi_send_multicommand(spicommands);
797 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000798 fprintf(stderr, "%s failed during command execution\n",
799 __func__);
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000800 }
801 return result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000802}
803
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000804int spi_byte_program(int addr, uint8_t byte)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000805{
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000806 int result;
807 struct spi_command spicommands[] = {
808 {
809 .writecnt = JEDEC_WREN_OUTSIZE,
810 .writearr = (const unsigned char[]){ JEDEC_WREN },
811 .readcnt = 0,
812 .readarr = NULL,
813 }, {
814 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
815 .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte },
816 .readcnt = 0,
817 .readarr = NULL,
818 }, {
819 .writecnt = 0,
820 .writearr = NULL,
821 .readcnt = 0,
822 .readarr = NULL,
823 }};
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000824
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000825 result = spi_send_multicommand(spicommands);
826 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000827 fprintf(stderr, "%s failed during command execution\n",
828 __func__);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000829 }
830 return result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000831}
832
Paul Foxeb3acef2009-06-12 08:10:33 +0000833int spi_nbyte_program(int address, uint8_t *bytes, int len)
834{
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000835 int result;
836 /* FIXME: Switch to malloc based on len unless that kills speed. */
Paul Foxeb3acef2009-06-12 08:10:33 +0000837 unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
838 JEDEC_BYTE_PROGRAM,
839 (address >> 16) & 0xff,
840 (address >> 8) & 0xff,
841 (address >> 0) & 0xff,
842 };
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000843 struct spi_command spicommands[] = {
844 {
845 .writecnt = JEDEC_WREN_OUTSIZE,
846 .writearr = (const unsigned char[]){ JEDEC_WREN },
847 .readcnt = 0,
848 .readarr = NULL,
849 }, {
850 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
851 .writearr = cmd,
852 .readcnt = 0,
853 .readarr = NULL,
854 }, {
855 .writecnt = 0,
856 .writearr = NULL,
857 .readcnt = 0,
858 .readarr = NULL,
859 }};
Paul Foxeb3acef2009-06-12 08:10:33 +0000860
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000861 if (!len) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000862 fprintf(stderr, "%s called for zero-length write\n", __func__);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000863 return 1;
864 }
Paul Foxeb3acef2009-06-12 08:10:33 +0000865 if (len > 256) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000866 fprintf(stderr, "%s called for too long a write\n", __func__);
Paul Foxeb3acef2009-06-12 08:10:33 +0000867 return 1;
868 }
869
870 memcpy(&cmd[4], bytes, len);
871
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000872 result = spi_send_multicommand(spicommands);
873 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000874 fprintf(stderr, "%s failed during command execution\n",
875 __func__);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000876 }
877 return result;
Paul Foxeb3acef2009-06-12 08:10:33 +0000878}
879
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000880int spi_disable_blockprotect(void)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000881{
882 uint8_t status;
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000883 int result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000884
Peter Stugefa8c5502008-05-10 23:07:52 +0000885 status = spi_read_status_register();
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000886 /* If there is block protection in effect, unprotect it first. */
887 if ((status & 0x3c) != 0) {
888 printf_debug("Some block protection in effect, disabling\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000889 result = spi_write_status_register(status & ~0x3c);
890 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000891 fprintf(stderr, "spi_write_status_register failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000892 return result;
893 }
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000894 }
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000895 return 0;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000896}
897
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000898int spi_nbyte_read(int address, uint8_t *bytes, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000899{
Uwe Hermann394131e2008-10-18 21:14:13 +0000900 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
901 JEDEC_READ,
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000902 (address >> 16) & 0xff,
903 (address >> 8) & 0xff,
904 (address >> 0) & 0xff,
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000905 };
906
907 /* Send Read */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000908 return spi_send_command(sizeof(cmd), len, cmd, bytes);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000909}
910
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000911/*
912 * Read a complete flash chip.
913 * Each page is read separately in chunks with a maximum size of chunksize.
914 */
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000915int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000916{
917 int rc = 0;
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000918 int i, j, starthere, lenhere;
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000919 int page_size = flash->page_size;
920 int toread;
921
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000922 /* Warning: This loop has a very unusual condition and body.
923 * The loop needs to go through each page with at least one affected
924 * byte. The lowest page number is (start / page_size) since that
925 * division rounds down. The highest page number we want is the page
926 * where the last byte of the range lives. That last byte has the
927 * address (start + len - 1), thus the highest page number is
928 * (start + len - 1) / page_size. Since we want to include that last
929 * page as well, the loop condition uses <=.
930 */
931 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
932 /* Byte position of the first byte in the range in this page. */
933 /* starthere is an offset to the base address of the chip. */
934 starthere = max(start, i * page_size);
935 /* Length of bytes in the range in this page. */
936 lenhere = min(start + len, (i + 1) * page_size) - starthere;
937 for (j = 0; j < lenhere; j += chunksize) {
938 toread = min(chunksize, lenhere - j);
939 rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000940 if (rc)
941 break;
942 }
943 if (rc)
944 break;
945 }
946
947 return rc;
948}
949
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000950int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000951{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000952 if (!spi_programmer[spi_controller].read) {
953 fprintf(stderr, "%s called, but SPI read is unsupported on this"
954 " hardware. Please report a bug.\n", __func__);
955 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000956 }
957
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000958 return spi_programmer[spi_controller].read(flash, buf, start, len);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000959}
960
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000961/*
962 * Program chip using byte programming. (SLOW!)
963 * This is for chips which can only handle one byte writes
964 * and for chips where memory mapped programming is impossible
965 * (e.g. due to size constraints in IT87* for over 512 kB)
966 */
967int spi_chip_write_1(struct flashchip *flash, uint8_t *buf)
968{
969 int total_size = 1024 * flash->total_size;
970 int i;
971
972 spi_disable_blockprotect();
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +0000973 /* Erase first */
974 printf("Erasing flash before programming... ");
975 if (flash->erase(flash)) {
976 fprintf(stderr, "ERASE FAILED!\n");
977 return -1;
978 }
979 printf("done.\n");
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000980 for (i = 0; i < total_size; i++) {
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000981 spi_byte_program(i, buf[i]);
982 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000983 programmer_delay(10);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000984 }
985
986 return 0;
987}
988
989/*
990 * Program chip using page (256 bytes) programming.
991 * Some SPI masters can't do this, they use single byte programming instead.
992 */
Carl-Daniel Hailfinger8d497012009-05-09 02:34:18 +0000993int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000994{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000995 if (!spi_programmer[spi_controller].write_256) {
996 fprintf(stderr, "%s called, but SPI page write is unsupported "
997 " on this hardware. Please report a bug.\n", __func__);
998 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000999 }
1000
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001001 return spi_programmer[spi_controller].write_256(flash, buf);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +00001002}
Peter Stugefd9217d2009-01-26 03:37:40 +00001003
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +00001004uint32_t spi_get_valid_read_addr(void)
1005{
1006 /* Need to return BBAR for ICH chipsets. */
1007 return 0;
1008}
1009
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001010int spi_aai_write(struct flashchip *flash, uint8_t *buf)
1011{
Peter Stugefd9217d2009-01-26 03:37:40 +00001012 uint32_t pos = 2, size = flash->total_size * 1024;
1013 unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +00001014 int result;
1015
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +00001016 switch (spi_controller) {
1017 case SPI_CONTROLLER_WBSIO:
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001018 fprintf(stderr, "%s: impossible with Winbond SPI masters,"
1019 " degrading to byte program\n", __func__);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +00001020 return spi_chip_write_1(flash, buf);
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001021 default:
1022 break;
Peter Stugefd9217d2009-01-26 03:37:40 +00001023 }
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00001024 if (flash->erase(flash)) {
1025 fprintf(stderr, "ERASE FAILED!\n");
1026 return -1;
1027 }
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +00001028 result = spi_write_enable();
1029 if (result)
1030 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +00001031 spi_send_command(6, 0, w, NULL);
Peter Stugefd9217d2009-01-26 03:37:40 +00001032 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001033 programmer_delay(5); /* SST25VF040B Tbp is max 10us */
Peter Stugefd9217d2009-01-26 03:37:40 +00001034 while (pos < size) {
1035 w[1] = buf[pos++];
1036 w[2] = buf[pos++];
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +00001037 spi_send_command(3, 0, w, NULL);
Peter Stugefd9217d2009-01-26 03:37:40 +00001038 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001039 programmer_delay(5); /* SST25VF040B Tbp is max 10us */
Peter Stugefd9217d2009-01-26 03:37:40 +00001040 }
1041 spi_write_disable();
1042 return 0;
1043}