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Joerg Fischer52a15492010-05-21 22:28:19 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000021#if defined(__i386__) || defined(__x86_64__)
22
Joerg Fischer52a15492010-05-21 22:28:19 +000023#include <stdlib.h>
Joerg Fischer52a15492010-05-21 22:28:19 +000024#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000025#include "programmer.h"
Joerg Fischer52a15492010-05-21 22:28:19 +000026
27#define PCI_VENDOR_ID_REALTEK 0x10ec
28#define PCI_VENDOR_ID_SMC1211 0x1113
29
30#define BIOS_ROM_ADDR 0xD4
31#define BIOS_ROM_DATA 0xD7
32
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000033const struct pcidev_status nics_realtek[] = {
Uwe Hermann829ed842010-05-24 17:39:14 +000034 {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
Uwe Hermann829ed842010-05-24 17:39:14 +000035 {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */
36 {},
Joerg Fischer52a15492010-05-21 22:28:19 +000037};
38
David Hendricks8bb20212011-06-14 01:35:36 +000039static int nicrealtek_shutdown(void *data)
40{
41 /* FIXME: We forgot to disable software access again. */
42 pci_cleanup(pacc);
43 release_io_perms();
44 return 0;
45}
46
Joerg Fischer52a15492010-05-21 22:28:19 +000047int nicrealtek_init(void)
48{
49 get_io_perms();
Uwe Hermann829ed842010-05-24 17:39:14 +000050
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +000051 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);
Uwe Hermann829ed842010-05-24 17:39:14 +000052
Joerg Fischer52a15492010-05-21 22:28:19 +000053 buses_supported = CHIP_BUSTYPE_PARALLEL;
54
David Hendricks8bb20212011-06-14 01:35:36 +000055 if (register_shutdown(nicrealtek_shutdown, NULL))
56 return 1;
Joerg Fischer52a15492010-05-21 22:28:19 +000057 return 0;
58}
59
60void nicrealtek_chip_writeb(uint8_t val, chipaddr addr)
61{
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000062 /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
63 * enable software access.
64 */
Uwe Hermann829ed842010-05-24 17:39:14 +000065 OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
66 io_base_addr + BIOS_ROM_ADDR);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000067 /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
68 * enable software access.
69 */
Uwe Hermann829ed842010-05-24 17:39:14 +000070 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
71 io_base_addr + BIOS_ROM_ADDR);
Joerg Fischer52a15492010-05-21 22:28:19 +000072}
73
74uint8_t nicrealtek_chip_readb(const chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +000075{
Uwe Hermann829ed842010-05-24 17:39:14 +000076 uint8_t val;
Joerg Fischer52a15492010-05-21 22:28:19 +000077
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000078 /* FIXME: Can we skip reading the old data and simply use 0? */
79 /* Read old data. */
Uwe Hermann829ed842010-05-24 17:39:14 +000080 val = INB(io_base_addr + BIOS_ROM_DATA);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000081 /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
82 * enable software access.
83 */
Uwe Hermann829ed842010-05-24 17:39:14 +000084 OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
85 io_base_addr + BIOS_ROM_ADDR);
86
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000087 /* Read new data. */
Uwe Hermann829ed842010-05-24 17:39:14 +000088 val = INB(io_base_addr + BIOS_ROM_DATA);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000089 /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
90 * enable software access.
91 */
Uwe Hermann829ed842010-05-24 17:39:14 +000092 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
93 io_base_addr + BIOS_ROM_ADDR);
94
95 return val;
Joerg Fischer52a15492010-05-21 22:28:19 +000096}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000097
98#else
99#error PCI port I/O access is not supported on this architecture yet.
100#endif