blob: c2abcfb07326013e8915c55fd84f29b7daf9eb39 [file] [log] [blame]
Joerg Fischer52a15492010-05-21 22:28:19 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000021#if defined(__i386__) || defined(__x86_64__)
22
Joerg Fischer52a15492010-05-21 22:28:19 +000023#include <stdlib.h>
Joerg Fischer52a15492010-05-21 22:28:19 +000024#include "flash.h"
25
26#define PCI_VENDOR_ID_REALTEK 0x10ec
27#define PCI_VENDOR_ID_SMC1211 0x1113
28
29#define BIOS_ROM_ADDR 0xD4
30#define BIOS_ROM_DATA 0xD7
31
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000032const struct pcidev_status nics_realtek[] = {
Uwe Hermann829ed842010-05-24 17:39:14 +000033 {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
Joerg Fischer52a15492010-05-21 22:28:19 +000034 {},
35};
36
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000037const struct pcidev_status nics_realteksmc1211[] = {
Uwe Hermann829ed842010-05-24 17:39:14 +000038 {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */
39 {},
Joerg Fischer52a15492010-05-21 22:28:19 +000040};
41
Joerg Fischer52a15492010-05-21 22:28:19 +000042int nicrealtek_init(void)
43{
44 get_io_perms();
Uwe Hermann829ed842010-05-24 17:39:14 +000045
Joerg Fischer52a15492010-05-21 22:28:19 +000046 io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0,
Uwe Hermann829ed842010-05-24 17:39:14 +000047 nics_realtek, programmer_param);
48
Joerg Fischer52a15492010-05-21 22:28:19 +000049 buses_supported = CHIP_BUSTYPE_PARALLEL;
50
51 return 0;
52}
53
Joerg Fischer52a15492010-05-21 22:28:19 +000054int nicsmc1211_init(void)
55{
56 get_io_perms();
Uwe Hermann829ed842010-05-24 17:39:14 +000057
Joerg Fischer52a15492010-05-21 22:28:19 +000058 io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0,
Uwe Hermann829ed842010-05-24 17:39:14 +000059 nics_realteksmc1211, programmer_param);
60
Joerg Fischer52a15492010-05-21 22:28:19 +000061 buses_supported = CHIP_BUSTYPE_PARALLEL;
62
63 return 0;
64}
65
66int nicrealtek_shutdown(void)
67{
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000068 /* FIXME: We forgot to disable software access again. */
Joerg Fischer52a15492010-05-21 22:28:19 +000069 free(programmer_param);
70 pci_cleanup(pacc);
71 release_io_perms();
72 return 0;
73}
74
75void nicrealtek_chip_writeb(uint8_t val, chipaddr addr)
76{
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000077 /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
78 * enable software access.
79 */
Uwe Hermann829ed842010-05-24 17:39:14 +000080 OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
81 io_base_addr + BIOS_ROM_ADDR);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000082 /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
83 * enable software access.
84 */
Uwe Hermann829ed842010-05-24 17:39:14 +000085 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
86 io_base_addr + BIOS_ROM_ADDR);
Joerg Fischer52a15492010-05-21 22:28:19 +000087}
88
89uint8_t nicrealtek_chip_readb(const chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +000090{
Uwe Hermann829ed842010-05-24 17:39:14 +000091 uint8_t val;
Joerg Fischer52a15492010-05-21 22:28:19 +000092
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000093 /* FIXME: Can we skip reading the old data and simply use 0? */
94 /* Read old data. */
Uwe Hermann829ed842010-05-24 17:39:14 +000095 val = INB(io_base_addr + BIOS_ROM_DATA);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000096 /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
97 * enable software access.
98 */
Uwe Hermann829ed842010-05-24 17:39:14 +000099 OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
100 io_base_addr + BIOS_ROM_ADDR);
101
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000102 /* Read new data. */
Uwe Hermann829ed842010-05-24 17:39:14 +0000103 val = INB(io_base_addr + BIOS_ROM_DATA);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000104 /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
105 * enable software access.
106 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000107 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
108 io_base_addr + BIOS_ROM_ADDR);
109
110 return val;
Joerg Fischer52a15492010-05-21 22:28:19 +0000111}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000112
113#else
114#error PCI port I/O access is not supported on this architecture yet.
115#endif