Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 5 | * Copyright (C) 2008 coresystems GmbH |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Contains the generic SPI framework |
| 23 | */ |
| 24 | |
| 25 | #include <stdio.h> |
| 26 | #include <pci/pci.h> |
| 27 | #include <stdint.h> |
| 28 | #include <string.h> |
| 29 | #include "flash.h" |
Carl-Daniel Hailfinger | d6cbf76 | 2008-05-13 14:58:23 +0000 | [diff] [blame] | 30 | #include "spi.h" |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 31 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 32 | void spi_prettyprint_status_register(struct flashchip *flash); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 33 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 34 | int spi_command(unsigned int writecnt, unsigned int readcnt, |
| 35 | const unsigned char *writearr, unsigned char *readarr) |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 36 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 37 | switch (flashbus) { |
| 38 | case BUS_TYPE_IT87XX_SPI: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 39 | return it8716f_spi_command(writecnt, readcnt, writearr, |
| 40 | readarr); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 41 | case BUS_TYPE_ICH7_SPI: |
| 42 | case BUS_TYPE_ICH9_SPI: |
| 43 | case BUS_TYPE_VIA_SPI: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 44 | return ich_spi_command(writecnt, readcnt, writearr, readarr); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 45 | case BUS_TYPE_SB600_SPI: |
| 46 | return sb600_spi_command(writecnt, readcnt, writearr, readarr); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 47 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 48 | printf_debug |
| 49 | ("%s called, but no SPI chipset/strapping detected\n", |
| 50 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 51 | } |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 52 | return 1; |
| 53 | } |
| 54 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 55 | static int spi_rdid(unsigned char *readarr, int bytes) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 56 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 57 | const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 58 | |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 59 | if (spi_command(sizeof(cmd), bytes, cmd, readarr)) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 60 | return 1; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 61 | printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], |
| 62 | readarr[2]); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 63 | return 0; |
| 64 | } |
| 65 | |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 66 | static int spi_rems(unsigned char *readarr) |
| 67 | { |
| 68 | const unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; |
| 69 | |
| 70 | if (spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr)) |
| 71 | return 1; |
| 72 | printf_debug("REMS returned %02x %02x.\n", readarr[0], readarr[1]); |
| 73 | return 0; |
| 74 | } |
| 75 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 76 | static int spi_res(unsigned char *readarr) |
| 77 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 78 | const unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 79 | |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 80 | if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr)) |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 81 | return 1; |
| 82 | printf_debug("RES returned %02x.\n", readarr[0]); |
| 83 | return 0; |
| 84 | } |
| 85 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 86 | int spi_write_enable() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 87 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 88 | const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 89 | |
| 90 | /* Send WREN (Write Enable) */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 91 | return spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 92 | } |
| 93 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 94 | int spi_write_disable() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 95 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 96 | const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 97 | |
| 98 | /* Send WRDI (Write Disable) */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 99 | return spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 100 | } |
| 101 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 102 | static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 103 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 104 | unsigned char readarr[4]; |
Carl-Daniel Hailfinger | 1263d2a | 2008-02-06 22:07:58 +0000 | [diff] [blame] | 105 | uint32_t manuf_id; |
| 106 | uint32_t model_id; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 107 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 108 | if (spi_rdid(readarr, bytes)) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 109 | return 0; |
| 110 | |
| 111 | if (!oddparity(readarr[0])) |
| 112 | printf_debug("RDID byte 0 parity violation.\n"); |
| 113 | |
| 114 | /* Check if this is a continuation vendor ID */ |
| 115 | if (readarr[0] == 0x7f) { |
| 116 | if (!oddparity(readarr[1])) |
| 117 | printf_debug("RDID byte 1 parity violation.\n"); |
| 118 | manuf_id = (readarr[0] << 8) | readarr[1]; |
| 119 | model_id = readarr[2]; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 120 | if (bytes > 3) { |
| 121 | model_id <<= 8; |
| 122 | model_id |= readarr[3]; |
| 123 | } |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 124 | } else { |
| 125 | manuf_id = readarr[0]; |
| 126 | model_id = (readarr[1] << 8) | readarr[2]; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 127 | } |
| 128 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 129 | printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, |
| 130 | model_id); |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 131 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 132 | if (manuf_id == flash->manufacture_id && model_id == flash->model_id) { |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 133 | /* Print the status register to tell the |
| 134 | * user about possible write protection. |
| 135 | */ |
| 136 | spi_prettyprint_status_register(flash); |
| 137 | |
| 138 | return 1; |
| 139 | } |
| 140 | |
| 141 | /* Test if this is a pure vendor match. */ |
| 142 | if (manuf_id == flash->manufacture_id && |
| 143 | GENERIC_DEVICE_ID == flash->model_id) |
| 144 | return 1; |
| 145 | |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 146 | return 0; |
| 147 | } |
| 148 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 149 | int probe_spi_rdid(struct flashchip *flash) |
| 150 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 151 | return probe_spi_rdid_generic(flash, 3); |
| 152 | } |
| 153 | |
| 154 | /* support 4 bytes flash ID */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 155 | int probe_spi_rdid4(struct flashchip *flash) |
| 156 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 157 | /* only some SPI chipsets support 4 bytes commands */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 158 | switch (flashbus) { |
| 159 | case BUS_TYPE_ICH7_SPI: |
| 160 | case BUS_TYPE_ICH9_SPI: |
| 161 | case BUS_TYPE_VIA_SPI: |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 162 | case BUS_TYPE_SB600_SPI: |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 163 | return probe_spi_rdid_generic(flash, 4); |
| 164 | default: |
| 165 | printf_debug("4b ID not supported on this SPI controller\n"); |
| 166 | } |
| 167 | |
| 168 | return 0; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 169 | } |
| 170 | |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 171 | int probe_spi_rems(struct flashchip *flash) |
| 172 | { |
| 173 | unsigned char readarr[JEDEC_REMS_INSIZE]; |
| 174 | uint32_t manuf_id, model_id; |
| 175 | |
| 176 | if (spi_rems(readarr)) |
| 177 | return 0; |
| 178 | |
| 179 | manuf_id = readarr[0]; |
| 180 | model_id = readarr[1]; |
| 181 | |
| 182 | printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, |
| 183 | model_id); |
| 184 | |
| 185 | if (manuf_id == flash->manufacture_id && model_id == flash->model_id) { |
| 186 | /* Print the status register to tell the |
| 187 | * user about possible write protection. |
| 188 | */ |
| 189 | spi_prettyprint_status_register(flash); |
| 190 | |
| 191 | return 1; |
| 192 | } |
| 193 | |
| 194 | /* Test if this is a pure vendor match. */ |
| 195 | if (manuf_id == flash->manufacture_id && |
| 196 | GENERIC_DEVICE_ID == flash->model_id) |
| 197 | return 1; |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 202 | int probe_spi_res(struct flashchip *flash) |
| 203 | { |
| 204 | unsigned char readarr[3]; |
| 205 | uint32_t model_id; |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 206 | |
Carl-Daniel Hailfinger | 92a54ca | 2008-11-27 22:48:48 +0000 | [diff] [blame] | 207 | /* Check if RDID was successful and did not return 0xff 0xff 0xff. |
| 208 | * In that case, RES is pointless. |
| 209 | */ |
| 210 | if (!spi_rdid(readarr, 3) && ((readarr[0] != 0xff) || |
| 211 | (readarr[1] != 0xff) || (readarr[2] != 0xff))) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 212 | return 0; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 213 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 214 | if (spi_res(readarr)) |
| 215 | return 0; |
| 216 | |
| 217 | model_id = readarr[0]; |
| 218 | printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id); |
| 219 | if (model_id != flash->model_id) |
| 220 | return 0; |
| 221 | |
| 222 | /* Print the status register to tell the |
| 223 | * user about possible write protection. |
| 224 | */ |
| 225 | spi_prettyprint_status_register(flash); |
| 226 | return 1; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 227 | } |
| 228 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 229 | uint8_t spi_read_status_register() |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 230 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 231 | const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 232 | unsigned char readarr[JEDEC_RDSR_INSIZE]; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 233 | |
| 234 | /* Read Status Register */ |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 235 | if (flashbus == BUS_TYPE_SB600_SPI) { |
| 236 | /* SB600 uses a different way to read status register. */ |
| 237 | return sb600_read_status_register(); |
| 238 | } else { |
| 239 | spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); |
| 240 | } |
| 241 | |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 242 | return readarr[0]; |
| 243 | } |
| 244 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 245 | /* Prettyprint the status register. Common definitions. |
| 246 | */ |
| 247 | void spi_prettyprint_status_register_common(uint8_t status) |
| 248 | { |
| 249 | printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 250 | "%sset\n", (status & (1 << 5)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 251 | printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 252 | "%sset\n", (status & (1 << 4)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 253 | printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 254 | "%sset\n", (status & (1 << 3)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 255 | printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 256 | "%sset\n", (status & (1 << 2)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 257 | printf_debug("Chip status register: Write Enable Latch (WEL) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 258 | "%sset\n", (status & (1 << 1)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 259 | printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 260 | "%sset\n", (status & (1 << 0)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 261 | } |
| 262 | |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 263 | /* Prettyprint the status register. Works for |
| 264 | * ST M25P series |
| 265 | * MX MX25L series |
| 266 | */ |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 267 | void spi_prettyprint_status_register_st_m25p(uint8_t status) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 268 | { |
| 269 | printf_debug("Chip status register: Status Register Write Disable " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 270 | "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 271 | printf_debug("Chip status register: Bit 6 is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 272 | "%sset\n", (status & (1 << 6)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 273 | spi_prettyprint_status_register_common(status); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 274 | } |
| 275 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 276 | /* Prettyprint the status register. Works for |
| 277 | * SST 25VF016 |
| 278 | */ |
| 279 | void spi_prettyprint_status_register_sst25vf016(uint8_t status) |
| 280 | { |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 281 | const char *bpt[] = { |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 282 | "none", |
| 283 | "1F0000H-1FFFFFH", |
| 284 | "1E0000H-1FFFFFH", |
| 285 | "1C0000H-1FFFFFH", |
| 286 | "180000H-1FFFFFH", |
| 287 | "100000H-1FFFFFH", |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 288 | "all", "all" |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 289 | }; |
| 290 | printf_debug("Chip status register: Block Protect Write Disable " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 291 | "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 292 | printf_debug("Chip status register: Auto Address Increment Programming " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 293 | "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 294 | spi_prettyprint_status_register_common(status); |
| 295 | printf_debug("Resulting block protection : %s\n", |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 296 | bpt[(status & 0x1c) >> 2]); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | void spi_prettyprint_status_register(struct flashchip *flash) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 300 | { |
| 301 | uint8_t status; |
| 302 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 303 | status = spi_read_status_register(); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 304 | printf_debug("Chip status register is %02x\n", status); |
| 305 | switch (flash->manufacture_id) { |
| 306 | case ST_ID: |
Carl-Daniel Hailfinger | f43e642 | 2008-05-15 22:32:08 +0000 | [diff] [blame] | 307 | if (((flash->model_id & 0xff00) == 0x2000) || |
| 308 | ((flash->model_id & 0xff00) == 0x2500)) |
| 309 | spi_prettyprint_status_register_st_m25p(status); |
| 310 | break; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 311 | case MX_ID: |
| 312 | if ((flash->model_id & 0xff00) == 0x2000) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 313 | spi_prettyprint_status_register_st_m25p(status); |
| 314 | break; |
| 315 | case SST_ID: |
| 316 | if (flash->model_id == SST_25VF016B) |
| 317 | spi_prettyprint_status_register_sst25vf016(status); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 318 | break; |
| 319 | } |
| 320 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 321 | |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 322 | int spi_chip_erase_60(struct flashchip *flash) |
| 323 | { |
| 324 | const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 325 | int result; |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 326 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 327 | result = spi_disable_blockprotect(); |
| 328 | if (result) { |
| 329 | printf_debug("spi_disable_blockprotect failed\n"); |
| 330 | return result; |
| 331 | } |
| 332 | result = spi_write_enable(); |
| 333 | if (result) { |
| 334 | printf_debug("spi_write_enable failed\n"); |
| 335 | return result; |
| 336 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 337 | /* Send CE (Chip Erase) */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 338 | result = spi_command(sizeof(cmd), 0, cmd, NULL); |
| 339 | if (result) { |
| 340 | printf_debug("spi_chip_erase_60 failed sending erase\n"); |
| 341 | return result; |
| 342 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 343 | /* Wait until the Write-In-Progress bit is cleared. |
| 344 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 345 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 346 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 347 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
| 348 | sleep(1); |
| 349 | return 0; |
| 350 | } |
| 351 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 352 | int spi_chip_erase_c7(struct flashchip *flash) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 353 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 354 | const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 355 | int result; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 356 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 357 | result = spi_disable_blockprotect(); |
| 358 | if (result) { |
| 359 | printf_debug("spi_disable_blockprotect failed\n"); |
| 360 | return result; |
| 361 | } |
| 362 | result = spi_write_enable(); |
| 363 | if (result) { |
| 364 | printf_debug("spi_write_enable failed\n"); |
| 365 | return result; |
| 366 | } |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 367 | /* Send CE (Chip Erase) */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 368 | result = spi_command(sizeof(cmd), 0, cmd, NULL); |
| 369 | if (result) { |
| 370 | printf_debug("spi_chip_erase_60 failed sending erase\n"); |
| 371 | return result; |
| 372 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 373 | /* Wait until the Write-In-Progress bit is cleared. |
| 374 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 375 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 376 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 377 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 378 | sleep(1); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 379 | return 0; |
| 380 | } |
| 381 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 382 | int spi_chip_erase_60_c7(struct flashchip *flash) |
| 383 | { |
| 384 | int result; |
| 385 | result = spi_chip_erase_60(flash); |
| 386 | if (result) { |
| 387 | printf_debug("spi_chip_erase_60 failed, trying c7\n"); |
| 388 | result = spi_chip_erase_c7(flash); |
| 389 | } |
| 390 | return result; |
| 391 | } |
| 392 | |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 393 | int spi_block_erase_52(const struct flashchip *flash, unsigned long addr) |
| 394 | { |
| 395 | unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52}; |
| 396 | |
| 397 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 398 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 399 | cmd[3] = (addr & 0x000000ff); |
| 400 | spi_write_enable(); |
| 401 | /* Send BE (Block Erase) */ |
| 402 | spi_command(sizeof(cmd), 0, cmd, NULL); |
| 403 | /* Wait until the Write-In-Progress bit is cleared. |
| 404 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 405 | */ |
| 406 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
| 407 | usleep(100 * 1000); |
| 408 | return 0; |
| 409 | } |
| 410 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 411 | /* Block size is usually |
| 412 | * 64k for Macronix |
| 413 | * 32k for SST |
| 414 | * 4-32k non-uniform for EON |
| 415 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 416 | int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 417 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 418 | unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 }; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 419 | |
| 420 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 421 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 422 | cmd[3] = (addr & 0x000000ff); |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 423 | spi_write_enable(); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 424 | /* Send BE (Block Erase) */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 425 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 426 | /* Wait until the Write-In-Progress bit is cleared. |
| 427 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 428 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 429 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 430 | usleep(100 * 1000); |
| 431 | return 0; |
| 432 | } |
| 433 | |
Stefan Reinauer | 424ed22 | 2008-10-29 22:13:20 +0000 | [diff] [blame] | 434 | int spi_chip_erase_d8(struct flashchip *flash) |
| 435 | { |
| 436 | int i, rc = 0; |
| 437 | int total_size = flash->total_size * 1024; |
| 438 | int erase_size = 64 * 1024; |
| 439 | |
| 440 | spi_disable_blockprotect(); |
| 441 | |
| 442 | printf("Erasing chip: \n"); |
| 443 | |
| 444 | for (i = 0; i < total_size / erase_size; i++) { |
| 445 | rc = spi_block_erase_d8(flash, i * erase_size); |
| 446 | if (rc) { |
| 447 | printf("Error erasing block at 0x%x\n", i); |
| 448 | break; |
| 449 | } |
| 450 | } |
| 451 | |
| 452 | printf("\n"); |
| 453 | |
| 454 | return rc; |
| 455 | } |
| 456 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 457 | /* Sector size is usually 4k, though Macronix eliteflash has 64k */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 458 | int spi_sector_erase(const struct flashchip *flash, unsigned long addr) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 459 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 460 | unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE }; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 461 | cmd[1] = (addr & 0x00ff0000) >> 16; |
| 462 | cmd[2] = (addr & 0x0000ff00) >> 8; |
| 463 | cmd[3] = (addr & 0x000000ff); |
| 464 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 465 | spi_write_enable(); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 466 | /* Send SE (Sector Erase) */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 467 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 468 | /* Wait until the Write-In-Progress bit is cleared. |
| 469 | * This usually takes 15-800 ms, so wait in 10 ms steps. |
| 470 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 471 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 472 | usleep(10 * 1000); |
| 473 | return 0; |
| 474 | } |
| 475 | |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 476 | int spi_write_status_enable() |
| 477 | { |
| 478 | const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; |
| 479 | |
| 480 | /* Send EWSR (Enable Write Status Register). */ |
| 481 | return spi_command(JEDEC_EWSR_OUTSIZE, JEDEC_EWSR_INSIZE, cmd, NULL); |
| 482 | } |
| 483 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 484 | /* |
| 485 | * This is according the SST25VF016 datasheet, who knows it is more |
| 486 | * generic that this... |
| 487 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 488 | int spi_write_status_register(int status) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 489 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 490 | const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = |
| 491 | { JEDEC_WRSR, (unsigned char)status }; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 492 | |
| 493 | /* Send WRSR (Write Status Register) */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 494 | return spi_command(sizeof(cmd), 0, cmd, NULL); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 495 | } |
| 496 | |
| 497 | void spi_byte_program(int address, uint8_t byte) |
| 498 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 499 | const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = { |
| 500 | JEDEC_BYTE_PROGRAM, |
| 501 | (address >> 16) & 0xff, |
| 502 | (address >> 8) & 0xff, |
| 503 | (address >> 0) & 0xff, |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 504 | byte |
| 505 | }; |
| 506 | |
| 507 | /* Send Byte-Program */ |
Peter Stuge | f83221b | 2008-07-07 06:38:51 +0000 | [diff] [blame] | 508 | spi_command(sizeof(cmd), 0, cmd, NULL); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 509 | } |
| 510 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 511 | int spi_disable_blockprotect(void) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 512 | { |
| 513 | uint8_t status; |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 514 | int result; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 515 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 516 | status = spi_read_status_register(); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 517 | /* If there is block protection in effect, unprotect it first. */ |
| 518 | if ((status & 0x3c) != 0) { |
| 519 | printf_debug("Some block protection in effect, disabling\n"); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 520 | result = spi_write_status_enable(); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 521 | if (result) { |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 522 | printf_debug("spi_write_status_enable failed\n"); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 523 | return result; |
| 524 | } |
| 525 | result = spi_write_status_register(status & ~0x3c); |
| 526 | if (result) { |
| 527 | printf_debug("spi_write_status_register failed\n"); |
| 528 | return result; |
| 529 | } |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 530 | } |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 531 | return 0; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 532 | } |
| 533 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 534 | int spi_nbyte_read(int address, uint8_t *bytes, int len) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 535 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 536 | const unsigned char cmd[JEDEC_READ_OUTSIZE] = { |
| 537 | JEDEC_READ, |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 538 | (address >> 16) & 0xff, |
| 539 | (address >> 8) & 0xff, |
| 540 | (address >> 0) & 0xff, |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 541 | }; |
| 542 | |
| 543 | /* Send Read */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 544 | return spi_command(sizeof(cmd), len, cmd, bytes); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 545 | } |
| 546 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 547 | int spi_chip_read(struct flashchip *flash, uint8_t *buf) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 548 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 549 | switch (flashbus) { |
| 550 | case BUS_TYPE_IT87XX_SPI: |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 551 | return it8716f_spi_chip_read(flash, buf); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 552 | case BUS_TYPE_SB600_SPI: |
| 553 | return sb600_spi_read(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 554 | case BUS_TYPE_ICH7_SPI: |
| 555 | case BUS_TYPE_ICH9_SPI: |
| 556 | case BUS_TYPE_VIA_SPI: |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 557 | return ich_spi_read(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 558 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 559 | printf_debug |
| 560 | ("%s called, but no SPI chipset/strapping detected\n", |
| 561 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 562 | } |
| 563 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 564 | return 1; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 565 | } |
| 566 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 567 | int spi_chip_write(struct flashchip *flash, uint8_t *buf) |
| 568 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 569 | switch (flashbus) { |
| 570 | case BUS_TYPE_IT87XX_SPI: |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 571 | return it8716f_spi_chip_write(flash, buf); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 572 | case BUS_TYPE_SB600_SPI: |
| 573 | return sb600_spi_write(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 574 | case BUS_TYPE_ICH7_SPI: |
| 575 | case BUS_TYPE_ICH9_SPI: |
| 576 | case BUS_TYPE_VIA_SPI: |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 577 | return ich_spi_write(flash, buf); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 578 | default: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 579 | printf_debug |
| 580 | ("%s called, but no SPI chipset/strapping detected\n", |
| 581 | __FUNCTION__); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 582 | } |
| 583 | |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 584 | return 1; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 585 | } |