blob: e25237ad6303c493fe5026cf2828c16faa1ebbd2 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Dominik Geyerb46acba2008-05-16 12:55:55 +00008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000022 */
23
24/*
25 * This module is designed for supporting the devices
26 * ST M25P40
27 * ST M25P80
28 * ST M25P16
29 * ST M25P32 already tested
30 * ST M25P64
31 * AT 25DF321 already tested
32 *
33 */
34
35#include <stdio.h>
36#include <string.h>
37#include <stdint.h>
38#include <sys/mman.h>
39#include <pci/pci.h>
40#include "flash.h"
41#include "spi.h"
42
Stefan Reinauera9424d52008-06-27 16:28:34 +000043/* ICH9 controller register definition */
44#define ICH9_REG_FADDR 0x08 /* 32 Bits */
45#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
46
47#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000048#define SSFS_SCIP 0x00000001
49#define SSFS_CDS 0x00000004
50#define SSFS_FCERR 0x00000008
51#define SSFS_AEL 0x00000010
Stefan Reinauera9424d52008-06-27 16:28:34 +000052
53#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000054#define SSFC_SCGO 0x00000200
55#define SSFC_ACS 0x00000400
56#define SSFC_SPOP 0x00000800
57#define SSFC_COP 0x00001000
58#define SSFC_DBC 0x00010000
59#define SSFC_DS 0x00400000
60#define SSFC_SME 0x00800000
61#define SSFC_SCF 0x01000000
62#define SSFC_SCF_20MHZ 0x00000000
63#define SSFC_SCF_33MHZ 0x01000000
Stefan Reinauera9424d52008-06-27 16:28:34 +000064
65#define ICH9_REG_PREOP 0x94 /* 16 Bits */
66#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
67#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000068
69// ICH9R SPI commands
70#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
71#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
72#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
73#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
74
Stefan Reinauera9424d52008-06-27 16:28:34 +000075// ICH7 registers
76#define ICH7_REG_SPIS 0x00 /* 16 Bits */
77#define SPIS_SCIP 0x00000001
78#define SPIS_CDS 0x00000004
79#define SPIS_FCERR 0x00000008
80
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000081/* VIA SPI is compatible with ICH7, but maxdata
82 to transfer is 16 bytes.
83
84 DATA byte count on ICH7 is 8:13, on VIA 8:11
85
86 bit 12 is port select CS0 CS1
87 bit 13 is FAST READ enable
88 bit 7 is used with fast read and one shot controls CS de-assert?
89*/
90
Stefan Reinauera9424d52008-06-27 16:28:34 +000091#define ICH7_REG_SPIC 0x02 /* 16 Bits */
92#define SPIC_SCGO 0x0002
93#define SPIC_ACS 0x0004
94#define SPIC_SPOP 0x0008
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000095#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +000096
97#define ICH7_REG_SPIA 0x04 /* 32 Bits */
98#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
99#define ICH7_REG_PREOP 0x54 /* 16 Bits */
100#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
101#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
102
FENG yu ningc05a2952008-12-08 18:16:58 +0000103/* ICH SPI configuration lock-down. May be set during chipset enabling. */
104int ichspi_lock = 0;
105
Dominik Geyerb46acba2008-05-16 12:55:55 +0000106typedef struct _OPCODE {
107 uint8_t opcode; //This commands spi opcode
108 uint8_t spi_type; //This commands spi type
109 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
110} OPCODE;
111
112/* Opcode definition:
113 * Preop 1: Write Enable
114 * Preop 2: Write Status register enable
115 *
116 * OP 0: Write address
117 * OP 1: Read Address
118 * OP 2: ERASE block
119 * OP 3: Read Status register
120 * OP 4: Read ID
121 * OP 5: Write Status register
122 * OP 6: chip private (read JDEC id)
123 * OP 7: Chip erase
124 */
125typedef struct _OPCODES {
126 uint8_t preop[2];
127 OPCODE opcode[8];
128} OPCODES;
129
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000130static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000131
132/* HW access functions */
133static inline uint32_t REGREAD32(int X)
134{
135 volatile uint32_t regval;
Uwe Hermann394131e2008-10-18 21:14:13 +0000136 regval = *(volatile uint32_t *)((uint8_t *) spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000137 return regval;
138}
139
140static inline uint16_t REGREAD16(int X)
141{
142 volatile uint16_t regval;
Uwe Hermann394131e2008-10-18 21:14:13 +0000143 regval = *(volatile uint16_t *)((uint8_t *) spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000144 return regval;
145}
146
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000147#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y)
148#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y)
149#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000150
Dominik Geyerb46acba2008-05-16 12:55:55 +0000151/* Common SPI functions */
FENG yu ningc05a2952008-12-08 18:16:58 +0000152static inline int find_opcode(OPCODES *op, uint8_t opcode);
153static inline int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000154static int generate_opcodes(OPCODES * op);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000155static int program_opcodes(OPCODES * op);
Stefan Reinauer43119562008-11-02 19:51:50 +0000156static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000157 uint8_t datalength, uint8_t * data);
158static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000159 int offset, int maxdata);
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000160static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000161 int offset, int maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000162
FENG yu ningf041e9b2008-12-15 02:32:11 +0000163/* for pairing opcodes with their required preop */
164struct preop_opcode_pair {
165 uint8_t preop;
166 uint8_t opcode;
167};
168
169struct preop_opcode_pair pops[] = {
170 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
171 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
172 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
173 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
174 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
175 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
176 {JEDEC_EWSR, JEDEC_WRSR},
177 {0,}
178};
179
Dominik Geyerb46acba2008-05-16 12:55:55 +0000180OPCODES O_ST_M25P = {
181 {
182 JEDEC_WREN,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000183 0},
Dominik Geyerb46acba2008-05-16 12:55:55 +0000184 {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000185 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Write Byte
186 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
187 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector
188 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
189 {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down
190 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register
191 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
192 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase
193 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000194};
195
FENG yu ningc05a2952008-12-08 18:16:58 +0000196OPCODES O_EXISTING = {};
197
198static inline int find_opcode(OPCODES *op, uint8_t opcode)
199{
200 int a;
201
202 for (a = 0; a < 8; a++) {
203 if (op->opcode[a].opcode == opcode)
204 return a;
205 }
206
207 return -1;
208}
209
210static inline int find_preop(OPCODES *op, uint8_t preop)
211{
212 int a;
213
214 for (a = 0; a < 2; a++) {
215 if (op->preop[a] == preop)
216 return a;
217 }
218
219 return -1;
220}
221
FENG yu ningf041e9b2008-12-15 02:32:11 +0000222static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000223{
FENG yu ningf041e9b2008-12-15 02:32:11 +0000224 int a, b, i;
FENG yu ningc05a2952008-12-08 18:16:58 +0000225 uint16_t preop, optype;
226 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000227
228 if (op == NULL) {
229 printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__);
230 return -1;
231 }
232
233 switch (flashbus) {
234 case BUS_TYPE_ICH7_SPI:
235 case BUS_TYPE_VIA_SPI:
236 preop = REGREAD16(ICH7_REG_PREOP);
237 optype = REGREAD16(ICH7_REG_OPTYPE);
238 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
239 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
240 break;
241 case BUS_TYPE_ICH9_SPI:
242 preop = REGREAD16(ICH9_REG_PREOP);
243 optype = REGREAD16(ICH9_REG_OPTYPE);
244 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
245 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
246 break;
247 default:
248 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
249 return -1;
250 }
251
252 op->preop[0] = (uint8_t) preop;
253 op->preop[1] = (uint8_t) (preop >> 8);
254
255 for (a = 0; a < 8; a++) {
256 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
257 optype >>= 2;
258 }
259
260 for (a = 0; a < 4; a++) {
261 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
262 opmenu[0] >>= 8;
263 }
264
265 for (a = 4; a < 8; a++) {
266 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
267 opmenu[1] >>= 8;
268 }
269
270 /* atomic (link opcode with required pre-op) */
271 for (a = 4; a < 8; a++)
272 op->opcode[a].atomic = 0;
273
FENG yu ningf041e9b2008-12-15 02:32:11 +0000274 for (i = 0; pops[i].opcode; i++) {
275 a = find_opcode(op, pops[i].opcode);
276 b = find_preop(op, pops[i].preop);
277 if ((a != -1) && (b != -1))
278 op->opcode[a].atomic = (uint8_t) ++b;
FENG yu ningc05a2952008-12-08 18:16:58 +0000279 }
280
281 return 0;
282}
283
Dominik Geyerb46acba2008-05-16 12:55:55 +0000284int program_opcodes(OPCODES * op)
285{
286 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000287 uint16_t preop, optype;
288 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000289
290 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000291 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000292 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000293 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000294 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000295
Stefan Reinauera9424d52008-06-27 16:28:34 +0000296 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000297 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000298 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000299 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000300 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000301
Stefan Reinauera9424d52008-06-27 16:28:34 +0000302 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000303 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000304 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000305 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000306 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000307
Dominik Geyerb46acba2008-05-16 12:55:55 +0000308 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000309 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000310 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000311 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000312 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000313
Peter Stuge016d4e12009-01-15 02:13:18 +0000314 printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000315 switch (flashbus) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000316 case BUS_TYPE_ICH7_SPI:
317 case BUS_TYPE_VIA_SPI:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000318 REGWRITE16(ICH7_REG_PREOP, preop);
319 REGWRITE16(ICH7_REG_OPTYPE, optype);
320 REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
321 REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
322 break;
323 case BUS_TYPE_ICH9_SPI:
324 REGWRITE16(ICH9_REG_PREOP, preop);
325 REGWRITE16(ICH9_REG_OPTYPE, optype);
326 REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
327 REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
328 break;
329 default:
330 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
331 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000332 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000333
334 return 0;
335}
336
FENG yu ningf041e9b2008-12-15 02:32:11 +0000337/* This function generates OPCODES from or programs OPCODES to ICH according to
338 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000339 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000340 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000341 */
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000342int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000343{
344 int rc = 0;
345 OPCODES *curopcodes_done;
346
347 if (curopcodes)
348 return 0;
349
350 if (ichspi_lock) {
351 printf_debug("Generating OPCODES... ");
352 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000353 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000354 } else {
355 printf_debug("Programming OPCODES... ");
356 curopcodes_done = &O_ST_M25P;
357 rc = program_opcodes(curopcodes_done);
358 }
359
360 if (rc) {
361 curopcodes = NULL;
362 printf_debug("failed\n");
363 return 1;
364 } else {
365 curopcodes = curopcodes_done;
366 printf_debug("done\n");
367 return 0;
368 }
369}
370
Stefan Reinauer43119562008-11-02 19:51:50 +0000371static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000372 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000373{
374 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000375 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000376 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000377 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000378 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000379 uint64_t opmenu;
380 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000381
382 /* Is it a write command? */
383 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
384 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
385 write_cmd = 1;
386 }
387
388 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000389 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000390
391 /* Program data into FDATA0 to N */
392 if (write_cmd && (datalength != 0)) {
393 temp32 = 0;
394 for (a = 0; a < datalength; a++) {
395 if ((a % 4) == 0) {
396 temp32 = 0;
397 }
398
399 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
400
401 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000402 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
403 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000404 }
405 }
406 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000407 REGWRITE32(ICH7_REG_SPID0 +
408 ((a - 1) - ((a - 1) % 4)), temp32);
409 }
410
411 }
412
413 /* Assemble SPIS */
414 temp16 = 0;
415 /* clear error status registers */
416 temp16 |= (SPIS_CDS + SPIS_FCERR);
417 REGWRITE16(ICH7_REG_SPIS, temp16);
418
419 /* Assemble SPIC */
420 temp16 = 0;
421
422 if (datalength != 0) {
423 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000424 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000425 }
426
427 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000428 opmenu = REGREAD32(ICH7_REG_OPMENU);
429 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
430
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000431 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
432 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000433 break;
434 }
435 opmenu >>= 8;
436 }
437 if (opcode_index == 8) {
438 printf_debug("Opcode %x not found.\n", op.opcode);
439 return 1;
440 }
441 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000442
443 /* Handle Atomic */
444 if (op.atomic != 0) {
445 /* Select atomic command */
446 temp16 |= SPIC_ACS;
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000447 /* Select prefix opcode */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000448 if ((op.atomic - 1) == 1) {
449 /*Select prefix opcode 2 */
450 temp16 |= SPIC_SPOP;
451 }
452 }
453
454 /* Start */
455 temp16 |= SPIC_SCGO;
456
457 /* write it */
458 REGWRITE16(ICH7_REG_SPIC, temp16);
459
460 /* wait for cycle complete */
461 timeout = 1000 * 60; // 60s is a looong timeout.
462 while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
463 myusec_delay(1000);
464 }
465 if (!timeout) {
466 printf_debug("timeout\n");
467 }
468
469 if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
470 printf_debug("Transaction error!\n");
471 return 1;
472 }
473
474 if ((!write_cmd) && (datalength != 0)) {
475 for (a = 0; a < datalength; a++) {
476 if ((a % 4) == 0) {
477 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
478 }
479
480 data[a] =
481 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
482 >> ((a % 4) * 8);
483 }
484 }
485
486 return 0;
487}
488
Stefan Reinauer43119562008-11-02 19:51:50 +0000489static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000490 uint8_t datalength, uint8_t * data)
491{
492 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000493 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000494 uint32_t temp32;
495 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000496 uint64_t opmenu;
497 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000498
499 /* Is it a write command? */
500 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
501 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
502 write_cmd = 1;
503 }
504
505 /* Programm Offset in Flash into FADDR */
506 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
507
508 /* Program data into FDATA0 to N */
509 if (write_cmd && (datalength != 0)) {
510 temp32 = 0;
511 for (a = 0; a < datalength; a++) {
512 if ((a % 4) == 0) {
513 temp32 = 0;
514 }
515
516 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
517
518 if ((a % 4) == 3) {
519 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
520 temp32);
521 }
522 }
523 if (((a - 1) % 4) != 3) {
524 REGWRITE32(ICH9_REG_FDATA0 +
525 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000526 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000527 }
528
529 /* Assemble SSFS + SSFC */
530 temp32 = 0;
531
532 /* clear error status registers */
533 temp32 |= (SSFS_CDS + SSFS_FCERR);
534 /* USE 20 MhZ */
535 temp32 |= SSFC_SCF_20MHZ;
536
537 if (datalength != 0) {
538 uint32_t datatemp;
539 temp32 |= SSFC_DS;
540 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
541 temp32 |= datatemp;
542 }
543
544 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000545 opmenu = REGREAD32(ICH9_REG_OPMENU);
546 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
547
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000548 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
549 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000550 break;
551 }
552 opmenu >>= 8;
553 }
554 if (opcode_index == 8) {
555 printf_debug("Opcode %x not found.\n", op.opcode);
556 return 1;
557 }
558 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000559
560 /* Handle Atomic */
561 if (op.atomic != 0) {
562 /* Select atomic command */
563 temp32 |= SSFC_ACS;
564 /* Selct prefix opcode */
565 if ((op.atomic - 1) == 1) {
566 /*Select prefix opcode 2 */
567 temp32 |= SSFC_SPOP;
568 }
569 }
570
571 /* Start */
572 temp32 |= SSFC_SCGO;
573
574 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000575 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000576
577 /*wait for cycle complete */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000578 timeout = 1000 * 60; // 60s is a looong timeout.
579 while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
580 myusec_delay(1000);
581 }
582 if (!timeout) {
583 printf_debug("timeout\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000584 }
585
Stefan Reinauera9424d52008-06-27 16:28:34 +0000586 if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000587 printf_debug("Transaction error!\n");
588 return 1;
589 }
590
591 if ((!write_cmd) && (datalength != 0)) {
592 for (a = 0; a < datalength; a++) {
593 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000594 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000595 }
596
597 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000598 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
599 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000600 }
601 }
602
603 return 0;
604}
605
Stefan Reinauer43119562008-11-02 19:51:50 +0000606static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000607 uint8_t datalength, uint8_t * data)
608{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000609 switch (flashbus) {
610 case BUS_TYPE_VIA_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000611 return ich7_run_opcode(op, offset, datalength, data, 16);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000612 case BUS_TYPE_ICH7_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000613 return ich7_run_opcode(op, offset, datalength, data, 64);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000614 case BUS_TYPE_ICH9_SPI:
Stefan Reinauer43119562008-11-02 19:51:50 +0000615 return ich9_run_opcode(op, offset, datalength, data);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000616 default:
617 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
618 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000619
620 /* If we ever get here, something really weird happened */
621 return -1;
622}
623
Uwe Hermann394131e2008-10-18 21:14:13 +0000624static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset,
625 int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000626{
627 int page_size = flash->page_size;
628 uint32_t remaining = flash->page_size;
629 int a;
630
Stefan Reinauera9424d52008-06-27 16:28:34 +0000631 printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n",
632 offset, page_size, buf);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000633
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000634 for (a = 0; a < page_size; a += maxdata) {
635 if (remaining < maxdata) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000636
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000637 if (spi_nbyte_read(offset + (page_size - remaining),
638 &buf[page_size - remaining], remaining)) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000639 printf_debug("Error reading");
640 return 1;
641 }
642 remaining = 0;
643 } else {
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000644 if (spi_nbyte_read(offset + (page_size - remaining),
645 &buf[page_size - remaining], maxdata)) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000646 printf_debug("Error reading");
647 return 1;
648 }
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000649 remaining -= maxdata;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000650 }
651 }
652
653 return 0;
654}
655
656static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000657 int offset, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000658{
659 int page_size = flash->page_size;
660 uint32_t remaining = page_size;
661 int a;
662
Stefan Reinauera9424d52008-06-27 16:28:34 +0000663 printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
664 offset, page_size, bytes);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000665
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000666 for (a = 0; a < page_size; a += maxdata) {
667 if (remaining < maxdata) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000668 if (run_opcode
Stefan Reinauer43119562008-11-02 19:51:50 +0000669 (curopcodes->opcode[0],
Stefan Reinauera9424d52008-06-27 16:28:34 +0000670 offset + (page_size - remaining), remaining,
Dominik Geyerb46acba2008-05-16 12:55:55 +0000671 &bytes[page_size - remaining]) != 0) {
672 printf_debug("Error writing");
673 return 1;
674 }
675 remaining = 0;
676 } else {
677 if (run_opcode
Stefan Reinauer43119562008-11-02 19:51:50 +0000678 (curopcodes->opcode[0],
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000679 offset + (page_size - remaining), maxdata,
Dominik Geyerb46acba2008-05-16 12:55:55 +0000680 &bytes[page_size - remaining]) != 0) {
681 printf_debug("Error writing");
682 return 1;
683 }
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000684 remaining -= maxdata;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000685 }
686 }
687
688 return 0;
689}
690
Dominik Geyerb46acba2008-05-16 12:55:55 +0000691int ich_spi_read(struct flashchip *flash, uint8_t * buf)
692{
693 int i, rc = 0;
694 int total_size = flash->total_size * 1024;
695 int page_size = flash->page_size;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000696 int maxdata = 64;
697
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000698 if (flashbus == BUS_TYPE_VIA_SPI) {
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000699 maxdata = 16;
700 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000701
702 for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
703 rc = ich_spi_read_page(flash, (void *)(buf + i * page_size),
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000704 i * page_size, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000705 }
706
707 return rc;
708}
709
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000710int ich_spi_write_256(struct flashchip *flash, uint8_t * buf)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000711{
712 int i, j, rc = 0;
713 int total_size = flash->total_size * 1024;
714 int page_size = flash->page_size;
715 int erase_size = 64 * 1024;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000716 int maxdata = 64;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000717
718 spi_disable_blockprotect();
719
720 printf("Programming page: \n");
721
722 for (i = 0; i < total_size / erase_size; i++) {
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000723 /* FIMXE: call the chip-specific spi_block_erase_XX instead.
724 * For this, we need to add a block erase function to
725 * struct flashchip.
726 */
727 rc = spi_block_erase_d8(flash, i * erase_size);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000728 if (rc) {
729 printf("Error erasing block at 0x%x\n", i);
730 break;
731 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000732
Peter Stuge6a214162008-07-07 05:14:06 +0000733 if (flashbus == BUS_TYPE_VIA_SPI)
734 maxdata = 16;
735
Dominik Geyerb46acba2008-05-16 12:55:55 +0000736 for (j = 0; j < erase_size / page_size; j++) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000737 ich_spi_write_page(flash,
738 (void *)(buf + (i * erase_size) + (j * page_size)),
739 (i * erase_size) + (j * page_size), maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000740 }
741 }
742
743 printf("\n");
744
745 return rc;
746}
747
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000748int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
749 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000750{
751 int a;
752 int opcode_index = -1;
753 const unsigned char cmd = *writearr;
754 OPCODE *opcode;
755 uint32_t addr = 0;
756 uint8_t *data;
757 int count;
758
Dominik Geyerb46acba2008-05-16 12:55:55 +0000759 /* find cmd in opcodes-table */
760 for (a = 0; a < 8; a++) {
761 if ((curopcodes->opcode[a]).opcode == cmd) {
762 opcode_index = a;
763 break;
764 }
765 }
766
767 /* unknown / not programmed command */
768 if (opcode_index == -1) {
769 printf_debug("Invalid OPCODE 0x%02x\n", cmd);
770 return 1;
771 }
772
773 opcode = &(curopcodes->opcode[opcode_index]);
774
775 /* if opcode-type requires an address */
776 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
777 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000778 addr = (writearr[1] << 16) |
779 (writearr[2] << 8) | (writearr[3] << 0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000780 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000781
Dominik Geyerb46acba2008-05-16 12:55:55 +0000782 /* translate read/write array/count */
783 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000784 data = (uint8_t *) (writearr + 1);
785 count = writecnt - 1;
786 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
787 data = (uint8_t *) (writearr + 4);
788 count = writecnt - 4;
789 } else {
790 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000791 count = readcnt;
792 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000793
Stefan Reinauer43119562008-11-02 19:51:50 +0000794 if (run_opcode(*opcode, addr, count, data) != 0) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000795 printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode);
796 return 1;
797 }
798
799 return 0;
800}