blob: af4b6db0ea0969b49dfc8a62272012393cb9d6fc [file] [log] [blame]
Sean Nelson14ba6682010-02-26 05:48:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00004 * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
Sean Nelson14ba6682010-02-26 05:48:29 +00005 * Copyright (C) 2008 coresystems GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the common SPI chip driver functions
23 */
24
25#include <string.h>
26#include "flash.h"
27#include "flashchips.h"
28#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000030#include "spi.h"
31
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000032static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000033{
Mathias Krausea60faab2011-01-17 07:50:42 +000034 static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
Sean Nelson14ba6682010-02-26 05:48:29 +000035 int ret;
36 int i;
37
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000038 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000039 if (ret)
40 return ret;
Sean Nelsoned479d22010-03-24 23:14:32 +000041 msg_cspew("RDID returned");
Sean Nelson14ba6682010-02-26 05:48:29 +000042 for (i = 0; i < bytes; i++)
Sean Nelsoned479d22010-03-24 23:14:32 +000043 msg_cspew(" 0x%02x", readarr[i]);
44 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000045 return 0;
46}
47
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000048static int spi_rems(struct flashctx *flash, unsigned char *readarr)
Sean Nelson14ba6682010-02-26 05:48:29 +000049{
50 unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
51 uint32_t readaddr;
52 int ret;
53
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000054 ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd,
55 readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000056 if (ret == SPI_INVALID_ADDRESS) {
57 /* Find the lowest even address allowed for reads. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000058 readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1;
Sean Nelson14ba6682010-02-26 05:48:29 +000059 cmd[1] = (readaddr >> 16) & 0xff,
60 cmd[2] = (readaddr >> 8) & 0xff,
61 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000062 ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE,
63 cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000064 }
65 if (ret)
66 return ret;
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +000067 msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]);
Sean Nelson14ba6682010-02-26 05:48:29 +000068 return 0;
69}
70
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000071static int spi_res(struct flashctx *flash, unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000072{
73 unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
74 uint32_t readaddr;
75 int ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000076 int i;
Sean Nelson14ba6682010-02-26 05:48:29 +000077
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000078 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000079 if (ret == SPI_INVALID_ADDRESS) {
80 /* Find the lowest even address allowed for reads. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000081 readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1;
Sean Nelson14ba6682010-02-26 05:48:29 +000082 cmd[1] = (readaddr >> 16) & 0xff,
83 cmd[2] = (readaddr >> 8) & 0xff,
84 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000085 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000086 }
87 if (ret)
88 return ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000089 msg_cspew("RES returned");
90 for (i = 0; i < bytes; i++)
91 msg_cspew(" 0x%02x", readarr[i]);
92 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000093 return 0;
94}
95
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000096int spi_write_enable(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +000097{
Mathias Krausea60faab2011-01-17 07:50:42 +000098 static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
Sean Nelson14ba6682010-02-26 05:48:29 +000099 int result;
100
101 /* Send WREN (Write Enable) */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000102 result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
Sean Nelson14ba6682010-02-26 05:48:29 +0000103
104 if (result)
Sean Nelsoned479d22010-03-24 23:14:32 +0000105 msg_cerr("%s failed\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000106
107 return result;
108}
109
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000110int spi_write_disable(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000111{
Mathias Krausea60faab2011-01-17 07:50:42 +0000112 static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
Sean Nelson14ba6682010-02-26 05:48:29 +0000113
114 /* Send WRDI (Write Disable) */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000115 return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
Sean Nelson14ba6682010-02-26 05:48:29 +0000116}
117
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000118static int probe_spi_rdid_generic(struct flashctx *flash, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +0000119{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000120 const struct flashchip *chip = flash->chip;
Sean Nelson14ba6682010-02-26 05:48:29 +0000121 unsigned char readarr[4];
122 uint32_t id1;
123 uint32_t id2;
124
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000125 if (spi_rdid(flash, readarr, bytes)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000126 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000127 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000128
129 if (!oddparity(readarr[0]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000130 msg_cdbg("RDID byte 0 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000131
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000132 /* Check if this is a continuation vendor ID.
133 * FIXME: Handle continuation device IDs.
134 */
Sean Nelson14ba6682010-02-26 05:48:29 +0000135 if (readarr[0] == 0x7f) {
136 if (!oddparity(readarr[1]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000137 msg_cdbg("RDID byte 1 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000138 id1 = (readarr[0] << 8) | readarr[1];
139 id2 = readarr[2];
140 if (bytes > 3) {
141 id2 <<= 8;
142 id2 |= readarr[3];
143 }
144 } else {
145 id1 = readarr[0];
146 id2 = (readarr[1] << 8) | readarr[2];
147 }
148
Sean Nelsoned479d22010-03-24 23:14:32 +0000149 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000150
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000151 if (id1 == chip->manufacture_id && id2 == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000152 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000153
154 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000155 if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000156 return 1;
157
158 /* Test if there is any vendor ID. */
Urja Rannikko0a5f6e42015-06-22 23:59:15 +0000159 if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff && id1 != 0x00)
Sean Nelson14ba6682010-02-26 05:48:29 +0000160 return 1;
161
162 return 0;
163}
164
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000165int probe_spi_rdid(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000166{
167 return probe_spi_rdid_generic(flash, 3);
168}
169
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000170int probe_spi_rdid4(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000171{
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000172 /* Some SPI controllers do not support commands with writecnt=1 and
173 * readcnt=4.
174 */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000175 switch (flash->mst->spi.type) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000176#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000177#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000178 case SPI_CONTROLLER_IT87XX:
Sean Nelson14ba6682010-02-26 05:48:29 +0000179 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000180 msg_cinfo("4 byte RDID not supported on this SPI controller\n");
181 return 0;
182 break;
Sean Nelson14ba6682010-02-26 05:48:29 +0000183#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000184#endif
Sean Nelson14ba6682010-02-26 05:48:29 +0000185 default:
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000186 return probe_spi_rdid_generic(flash, 4);
Sean Nelson14ba6682010-02-26 05:48:29 +0000187 }
188
189 return 0;
190}
191
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000192int probe_spi_rems(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000193{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000194 const struct flashchip *chip = flash->chip;
Sean Nelson14ba6682010-02-26 05:48:29 +0000195 unsigned char readarr[JEDEC_REMS_INSIZE];
196 uint32_t id1, id2;
197
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000198 if (spi_rems(flash, readarr)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000199 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000200 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000201
202 id1 = readarr[0];
203 id2 = readarr[1];
204
Sean Nelsoned479d22010-03-24 23:14:32 +0000205 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000206
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000207 if (id1 == chip->manufacture_id && id2 == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000208 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000209
210 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000211 if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000212 return 1;
213
214 /* Test if there is any vendor ID. */
Urja Rannikko0a5f6e42015-06-22 23:59:15 +0000215 if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff && id1 != 0x00)
Sean Nelson14ba6682010-02-26 05:48:29 +0000216 return 1;
217
218 return 0;
219}
220
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000221int probe_spi_res1(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000222{
Mathias Krausea60faab2011-01-17 07:50:42 +0000223 static const unsigned char allff[] = {0xff, 0xff, 0xff};
224 static const unsigned char all00[] = {0x00, 0x00, 0x00};
Sean Nelson14ba6682010-02-26 05:48:29 +0000225 unsigned char readarr[3];
226 uint32_t id2;
Sean Nelson14ba6682010-02-26 05:48:29 +0000227
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000228 /* We only want one-byte RES if RDID and REMS are unusable. */
229
Sean Nelson14ba6682010-02-26 05:48:29 +0000230 /* Check if RDID is usable and does not return 0xff 0xff 0xff or
231 * 0x00 0x00 0x00. In that case, RES is pointless.
232 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000233 if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) &&
Sean Nelson14ba6682010-02-26 05:48:29 +0000234 memcmp(readarr, all00, 3)) {
235 msg_cdbg("Ignoring RES in favour of RDID.\n");
236 return 0;
237 }
238 /* Check if REMS is usable and does not return 0xff 0xff or
239 * 0x00 0x00. In that case, RES is pointless.
240 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000241 if (!spi_rems(flash, readarr) &&
242 memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
Sean Nelson14ba6682010-02-26 05:48:29 +0000243 memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
244 msg_cdbg("Ignoring RES in favour of REMS.\n");
245 return 0;
246 }
247
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000248 if (spi_res(flash, readarr, 1)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000249 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000250 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000251
Sean Nelson14ba6682010-02-26 05:48:29 +0000252 id2 = readarr[0];
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000253
Sean Nelsoned479d22010-03-24 23:14:32 +0000254 msg_cdbg("%s: id 0x%x\n", __func__, id2);
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000255
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000256 if (id2 != flash->chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000257 return 0;
258
Sean Nelson14ba6682010-02-26 05:48:29 +0000259 return 1;
260}
261
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000262int probe_spi_res2(struct flashctx *flash)
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000263{
264 unsigned char readarr[2];
265 uint32_t id1, id2;
266
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000267 if (spi_res(flash, readarr, 2)) {
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000268 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000269 }
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000270
271 id1 = readarr[0];
272 id2 = readarr[1];
273
274 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
275
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000276 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000277 return 0;
278
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000279 return 1;
280}
281
Stefan Tauner3f5e35d2013-04-19 01:58:33 +0000282int probe_spi_res3(struct flashctx *flash)
283{
284 unsigned char readarr[3];
285 uint32_t id1, id2;
286
287 if (spi_res(flash, readarr, 3)) {
288 return 0;
289 }
290
291 id1 = (readarr[0] << 8) | readarr[1];
292 id2 = readarr[2];
293
294 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
295
296 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
297 return 0;
298
299 return 1;
300}
301
Stefan Tauner57794ac2012-12-29 15:04:20 +0000302/* Only used for some Atmel chips. */
303int probe_spi_at25f(struct flashctx *flash)
304{
305 static const unsigned char cmd[AT25F_RDID_OUTSIZE] = { AT25F_RDID };
306 unsigned char readarr[AT25F_RDID_INSIZE];
307 uint32_t id1;
308 uint32_t id2;
309
310 if (spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr))
311 return 0;
312
313 id1 = readarr[0];
314 id2 = readarr[1];
315
316 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
317
318 if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id)
319 return 1;
320
321 return 0;
322}
323
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000324int spi_chip_erase_60(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000325{
326 int result;
327 struct spi_command cmds[] = {
328 {
329 .writecnt = JEDEC_WREN_OUTSIZE,
330 .writearr = (const unsigned char[]){ JEDEC_WREN },
331 .readcnt = 0,
332 .readarr = NULL,
333 }, {
334 .writecnt = JEDEC_CE_60_OUTSIZE,
335 .writearr = (const unsigned char[]){ JEDEC_CE_60 },
336 .readcnt = 0,
337 .readarr = NULL,
338 }, {
339 .writecnt = 0,
340 .writearr = NULL,
341 .readcnt = 0,
342 .readarr = NULL,
343 }};
344
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000345 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000346 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000347 msg_cerr("%s failed during command execution\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000348 __func__);
349 return result;
350 }
351 /* Wait until the Write-In-Progress bit is cleared.
352 * This usually takes 1-85 s, so wait in 1 s steps.
353 */
354 /* FIXME: We assume spi_read_status_register will never fail. */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000355 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000356 programmer_delay(1000 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000357 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000358 return 0;
359}
360
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000361int spi_chip_erase_62(struct flashctx *flash)
362{
363 int result;
364 struct spi_command cmds[] = {
365 {
366 .writecnt = JEDEC_WREN_OUTSIZE,
367 .writearr = (const unsigned char[]){ JEDEC_WREN },
368 .readcnt = 0,
369 .readarr = NULL,
370 }, {
371 .writecnt = JEDEC_CE_62_OUTSIZE,
372 .writearr = (const unsigned char[]){ JEDEC_CE_62 },
373 .readcnt = 0,
374 .readarr = NULL,
375 }, {
376 .writecnt = 0,
377 .writearr = NULL,
378 .readcnt = 0,
379 .readarr = NULL,
380 }};
381
382 result = spi_send_multicommand(flash, cmds);
383 if (result) {
384 msg_cerr("%s failed during command execution\n",
385 __func__);
386 return result;
387 }
388 /* Wait until the Write-In-Progress bit is cleared.
389 * This usually takes 2-5 s, so wait in 100 ms steps.
390 */
391 /* FIXME: We assume spi_read_status_register will never fail. */
392 while (spi_read_status_register(flash) & SPI_SR_WIP)
393 programmer_delay(100 * 1000);
394 /* FIXME: Check the status register for errors. */
395 return 0;
396}
397
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000398int spi_chip_erase_c7(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000399{
400 int result;
401 struct spi_command cmds[] = {
402 {
403 .writecnt = JEDEC_WREN_OUTSIZE,
404 .writearr = (const unsigned char[]){ JEDEC_WREN },
405 .readcnt = 0,
406 .readarr = NULL,
407 }, {
408 .writecnt = JEDEC_CE_C7_OUTSIZE,
409 .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
410 .readcnt = 0,
411 .readarr = NULL,
412 }, {
413 .writecnt = 0,
414 .writearr = NULL,
415 .readcnt = 0,
416 .readarr = NULL,
417 }};
418
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000419 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000420 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000421 msg_cerr("%s failed during command execution\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000422 return result;
423 }
424 /* Wait until the Write-In-Progress bit is cleared.
425 * This usually takes 1-85 s, so wait in 1 s steps.
426 */
427 /* FIXME: We assume spi_read_status_register will never fail. */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000428 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000429 programmer_delay(1000 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000430 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000431 return 0;
432}
433
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000434int spi_block_erase_52(struct flashctx *flash, unsigned int addr,
435 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000436{
437 int result;
438 struct spi_command cmds[] = {
439 {
440 .writecnt = JEDEC_WREN_OUTSIZE,
441 .writearr = (const unsigned char[]){ JEDEC_WREN },
442 .readcnt = 0,
443 .readarr = NULL,
444 }, {
445 .writecnt = JEDEC_BE_52_OUTSIZE,
446 .writearr = (const unsigned char[]){
447 JEDEC_BE_52,
448 (addr >> 16) & 0xff,
449 (addr >> 8) & 0xff,
450 (addr & 0xff)
451 },
452 .readcnt = 0,
453 .readarr = NULL,
454 }, {
455 .writecnt = 0,
456 .writearr = NULL,
457 .readcnt = 0,
458 .readarr = NULL,
459 }};
460
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000461 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000462 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000463 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000464 __func__, addr);
465 return result;
466 }
467 /* Wait until the Write-In-Progress bit is cleared.
468 * This usually takes 100-4000 ms, so wait in 100 ms steps.
469 */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000470 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000471 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000472 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000473 return 0;
474}
475
476/* Block size is usually
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000477 * 32M (one die) for Micron
478 */
479int spi_block_erase_c4(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
480{
481 int result;
482 struct spi_command cmds[] = {
483 {
484 .writecnt = JEDEC_WREN_OUTSIZE,
485 .writearr = (const unsigned char[]){ JEDEC_WREN },
486 .readcnt = 0,
487 .readarr = NULL,
488 }, {
489 .writecnt = JEDEC_BE_C4_OUTSIZE,
490 .writearr = (const unsigned char[]){
491 JEDEC_BE_C4,
492 (addr >> 16) & 0xff,
493 (addr >> 8) & 0xff,
494 (addr & 0xff)
495 },
496 .readcnt = 0,
497 .readarr = NULL,
498 }, {
499 .writecnt = 0,
500 .writearr = NULL,
501 .readcnt = 0,
502 .readarr = NULL,
503 }};
504
505 result = spi_send_multicommand(flash, cmds);
506 if (result) {
507 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
508 return result;
509 }
510 /* Wait until the Write-In-Progress bit is cleared.
511 * This usually takes 240-480 s, so wait in 500 ms steps.
512 */
513 while (spi_read_status_register(flash) & SPI_SR_WIP)
514 programmer_delay(500 * 1000 * 1000);
515 /* FIXME: Check the status register for errors. */
516 return 0;
517}
518
519/* Block size is usually
Sean Nelson14ba6682010-02-26 05:48:29 +0000520 * 64k for Macronix
521 * 32k for SST
522 * 4-32k non-uniform for EON
523 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000524int spi_block_erase_d8(struct flashctx *flash, unsigned int addr,
525 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000526{
527 int result;
528 struct spi_command cmds[] = {
529 {
530 .writecnt = JEDEC_WREN_OUTSIZE,
531 .writearr = (const unsigned char[]){ JEDEC_WREN },
532 .readcnt = 0,
533 .readarr = NULL,
534 }, {
535 .writecnt = JEDEC_BE_D8_OUTSIZE,
536 .writearr = (const unsigned char[]){
537 JEDEC_BE_D8,
538 (addr >> 16) & 0xff,
539 (addr >> 8) & 0xff,
540 (addr & 0xff)
541 },
542 .readcnt = 0,
543 .readarr = NULL,
544 }, {
545 .writecnt = 0,
546 .writearr = NULL,
547 .readcnt = 0,
548 .readarr = NULL,
549 }};
550
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000551 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000552 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000553 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000554 __func__, addr);
555 return result;
556 }
557 /* Wait until the Write-In-Progress bit is cleared.
558 * This usually takes 100-4000 ms, so wait in 100 ms steps.
559 */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000560 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000561 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000562 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000563 return 0;
564}
565
566/* Block size is usually
567 * 4k for PMC
568 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000569int spi_block_erase_d7(struct flashctx *flash, unsigned int addr,
570 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000571{
572 int result;
573 struct spi_command cmds[] = {
574 {
575 .writecnt = JEDEC_WREN_OUTSIZE,
576 .writearr = (const unsigned char[]){ JEDEC_WREN },
577 .readcnt = 0,
578 .readarr = NULL,
579 }, {
580 .writecnt = JEDEC_BE_D7_OUTSIZE,
581 .writearr = (const unsigned char[]){
582 JEDEC_BE_D7,
583 (addr >> 16) & 0xff,
584 (addr >> 8) & 0xff,
585 (addr & 0xff)
586 },
587 .readcnt = 0,
588 .readarr = NULL,
589 }, {
590 .writecnt = 0,
591 .writearr = NULL,
592 .readcnt = 0,
593 .readarr = NULL,
594 }};
595
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000596 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000597 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000598 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000599 __func__, addr);
600 return result;
601 }
602 /* Wait until the Write-In-Progress bit is cleared.
603 * This usually takes 100-4000 ms, so wait in 100 ms steps.
604 */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000605 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000606 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000607 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000608 return 0;
609}
610
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000611/* Page erase (usually 256B blocks) */
612int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
613{
614 int result;
615 struct spi_command cmds[] = {
616 {
617 .writecnt = JEDEC_WREN_OUTSIZE,
618 .writearr = (const unsigned char[]){ JEDEC_WREN },
619 .readcnt = 0,
620 .readarr = NULL,
621 }, {
622 .writecnt = JEDEC_PE_OUTSIZE,
623 .writearr = (const unsigned char[]){
624 JEDEC_PE,
625 (addr >> 16) & 0xff,
626 (addr >> 8) & 0xff,
627 (addr & 0xff)
628 },
629 .readcnt = 0,
630 .readarr = NULL,
631 }, {
632 .writecnt = 0,
633 .writearr = NULL,
634 .readcnt = 0,
635 .readarr = NULL,
636 } };
637
638 result = spi_send_multicommand(flash, cmds);
639 if (result) {
640 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
641 return result;
642 }
643
644 /* Wait until the Write-In-Progress bit is cleared.
645 * This takes up to 20 ms usually (on worn out devices up to the 0.5s range), so wait in 1 ms steps. */
646 while (spi_read_status_register(flash) & SPI_SR_WIP)
647 programmer_delay(1 * 1000);
648 /* FIXME: Check the status register for errors. */
649 return 0;
650}
651
Sean Nelson14ba6682010-02-26 05:48:29 +0000652/* Sector size is usually 4k, though Macronix eliteflash has 64k */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000653int spi_block_erase_20(struct flashctx *flash, unsigned int addr,
654 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000655{
656 int result;
657 struct spi_command cmds[] = {
658 {
659 .writecnt = JEDEC_WREN_OUTSIZE,
660 .writearr = (const unsigned char[]){ JEDEC_WREN },
661 .readcnt = 0,
662 .readarr = NULL,
663 }, {
664 .writecnt = JEDEC_SE_OUTSIZE,
665 .writearr = (const unsigned char[]){
666 JEDEC_SE,
667 (addr >> 16) & 0xff,
668 (addr >> 8) & 0xff,
669 (addr & 0xff)
670 },
671 .readcnt = 0,
672 .readarr = NULL,
673 }, {
674 .writecnt = 0,
675 .writearr = NULL,
676 .readcnt = 0,
677 .readarr = NULL,
678 }};
679
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000680 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000681 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000682 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000683 __func__, addr);
684 return result;
685 }
686 /* Wait until the Write-In-Progress bit is cleared.
687 * This usually takes 15-800 ms, so wait in 10 ms steps.
688 */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000689 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000690 programmer_delay(10 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000691 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000692 return 0;
693}
694
Stefan Tauner94b39b42012-10-27 00:06:02 +0000695int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
696{
697 int result;
698 struct spi_command cmds[] = {
699 {
700/* .writecnt = JEDEC_WREN_OUTSIZE,
701 .writearr = (const unsigned char[]){ JEDEC_WREN },
702 .readcnt = 0,
703 .readarr = NULL,
704 }, { */
705 .writecnt = JEDEC_BE_50_OUTSIZE,
706 .writearr = (const unsigned char[]){
707 JEDEC_BE_50,
708 (addr >> 16) & 0xff,
709 (addr >> 8) & 0xff,
710 (addr & 0xff)
711 },
712 .readcnt = 0,
713 .readarr = NULL,
714 }, {
715 .writecnt = 0,
716 .writearr = NULL,
717 .readcnt = 0,
718 .readarr = NULL,
719 }};
720
721 result = spi_send_multicommand(flash, cmds);
722 if (result) {
723 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
724 return result;
725 }
726 /* Wait until the Write-In-Progress bit is cleared.
727 * This usually takes 10 ms, so wait in 1 ms steps.
728 */
729 while (spi_read_status_register(flash) & SPI_SR_WIP)
730 programmer_delay(1 * 1000);
731 /* FIXME: Check the status register for errors. */
732 return 0;
733}
734
735int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
736{
737 int result;
738 struct spi_command cmds[] = {
739 {
740/* .writecnt = JEDEC_WREN_OUTSIZE,
741 .writearr = (const unsigned char[]){ JEDEC_WREN },
742 .readcnt = 0,
743 .readarr = NULL,
744 }, { */
745 .writecnt = JEDEC_BE_81_OUTSIZE,
746 .writearr = (const unsigned char[]){
747 JEDEC_BE_81,
748 (addr >> 16) & 0xff,
749 (addr >> 8) & 0xff,
750 (addr & 0xff)
751 },
752 .readcnt = 0,
753 .readarr = NULL,
754 }, {
755 .writecnt = 0,
756 .writearr = NULL,
757 .readcnt = 0,
758 .readarr = NULL,
759 }};
760
761 result = spi_send_multicommand(flash, cmds);
762 if (result) {
763 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
764 return result;
765 }
766 /* Wait until the Write-In-Progress bit is cleared.
767 * This usually takes 8 ms, so wait in 1 ms steps.
768 */
769 while (spi_read_status_register(flash) & SPI_SR_WIP)
770 programmer_delay(1 * 1000);
771 /* FIXME: Check the status register for errors. */
772 return 0;
773}
774
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000775int spi_block_erase_60(struct flashctx *flash, unsigned int addr,
776 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000777{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000778 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000779 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000780 __func__);
781 return -1;
782 }
783 return spi_chip_erase_60(flash);
784}
785
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000786int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
787{
788 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
789 msg_cerr("%s called with incorrect arguments\n",
790 __func__);
791 return -1;
792 }
793 return spi_chip_erase_62(flash);
794}
795
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000796int spi_block_erase_c7(struct flashctx *flash, unsigned int addr,
797 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000798{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000799 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000800 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000801 __func__);
802 return -1;
803 }
804 return spi_chip_erase_c7(flash);
805}
806
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000807erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode)
808{
809 switch(opcode){
810 case 0xff:
811 case 0x00:
812 /* Not specified, assuming "not supported". */
813 return NULL;
814 case 0x20:
815 return &spi_block_erase_20;
Stefan Tauner730e7e72013-05-01 14:04:19 +0000816 case 0x50:
817 return &spi_block_erase_50;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000818 case 0x52:
819 return &spi_block_erase_52;
820 case 0x60:
821 return &spi_block_erase_60;
Stefan Tauner730e7e72013-05-01 14:04:19 +0000822 case 0x62:
823 return &spi_block_erase_62;
824 case 0x81:
825 return &spi_block_erase_81;
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000826 case 0xc4:
827 return &spi_block_erase_c4;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000828 case 0xc7:
829 return &spi_block_erase_c7;
830 case 0xd7:
831 return &spi_block_erase_d7;
832 case 0xd8:
833 return &spi_block_erase_d8;
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000834 case 0xdb:
835 return &spi_block_erase_db;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000836 default:
837 msg_cinfo("%s: unknown erase opcode (0x%02x). Please report "
838 "this at flashrom@flashrom.org\n", __func__, opcode);
839 return NULL;
840 }
841}
842
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000843int spi_byte_program(struct flashctx *flash, unsigned int addr,
844 uint8_t databyte)
Sean Nelson14ba6682010-02-26 05:48:29 +0000845{
846 int result;
847 struct spi_command cmds[] = {
848 {
849 .writecnt = JEDEC_WREN_OUTSIZE,
850 .writearr = (const unsigned char[]){ JEDEC_WREN },
851 .readcnt = 0,
852 .readarr = NULL,
853 }, {
854 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
855 .writearr = (const unsigned char[]){
856 JEDEC_BYTE_PROGRAM,
857 (addr >> 16) & 0xff,
858 (addr >> 8) & 0xff,
859 (addr & 0xff),
860 databyte
861 },
862 .readcnt = 0,
863 .readarr = NULL,
864 }, {
865 .writecnt = 0,
866 .writearr = NULL,
867 .readcnt = 0,
868 .readarr = NULL,
869 }};
870
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000871 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000872 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000873 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000874 __func__, addr);
875 }
876 return result;
877}
878
Mark Marshallf20b7be2014-05-09 21:16:21 +0000879int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000880{
881 int result;
882 /* FIXME: Switch to malloc based on len unless that kills speed. */
883 unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
884 JEDEC_BYTE_PROGRAM,
885 (addr >> 16) & 0xff,
886 (addr >> 8) & 0xff,
887 (addr >> 0) & 0xff,
888 };
889 struct spi_command cmds[] = {
890 {
891 .writecnt = JEDEC_WREN_OUTSIZE,
892 .writearr = (const unsigned char[]){ JEDEC_WREN },
893 .readcnt = 0,
894 .readarr = NULL,
895 }, {
896 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
897 .writearr = cmd,
898 .readcnt = 0,
899 .readarr = NULL,
900 }, {
901 .writecnt = 0,
902 .writearr = NULL,
903 .readcnt = 0,
904 .readarr = NULL,
905 }};
906
907 if (!len) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000908 msg_cerr("%s called for zero-length write\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000909 return 1;
910 }
911 if (len > 256) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000912 msg_cerr("%s called for too long a write\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000913 return 1;
914 }
915
916 memcpy(&cmd[4], bytes, len);
917
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000918 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000919 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000920 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000921 __func__, addr);
922 }
923 return result;
924}
925
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000926int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes,
927 unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000928{
929 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
930 JEDEC_READ,
931 (address >> 16) & 0xff,
932 (address >> 8) & 0xff,
933 (address >> 0) & 0xff,
934 };
935
936 /* Send Read */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000937 return spi_send_command(flash, sizeof(cmd), len, cmd, bytes);
Sean Nelson14ba6682010-02-26 05:48:29 +0000938}
939
940/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000941 * Read a part of the flash chip.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000942 * FIXME: Use the chunk code from Michael Karcher instead.
Sean Nelson14ba6682010-02-26 05:48:29 +0000943 * Each page is read separately in chunks with a maximum size of chunksize.
944 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000945int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,
946 unsigned int len, unsigned int chunksize)
Sean Nelson14ba6682010-02-26 05:48:29 +0000947{
948 int rc = 0;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000949 unsigned int i, j, starthere, lenhere, toread;
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000950 unsigned int page_size = flash->chip->page_size;
Sean Nelson14ba6682010-02-26 05:48:29 +0000951
952 /* Warning: This loop has a very unusual condition and body.
953 * The loop needs to go through each page with at least one affected
954 * byte. The lowest page number is (start / page_size) since that
955 * division rounds down. The highest page number we want is the page
956 * where the last byte of the range lives. That last byte has the
957 * address (start + len - 1), thus the highest page number is
958 * (start + len - 1) / page_size. Since we want to include that last
959 * page as well, the loop condition uses <=.
960 */
961 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
962 /* Byte position of the first byte in the range in this page. */
963 /* starthere is an offset to the base address of the chip. */
964 starthere = max(start, i * page_size);
965 /* Length of bytes in the range in this page. */
966 lenhere = min(start + len, (i + 1) * page_size) - starthere;
967 for (j = 0; j < lenhere; j += chunksize) {
968 toread = min(chunksize, lenhere - j);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000969 rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread);
Sean Nelson14ba6682010-02-26 05:48:29 +0000970 if (rc)
971 break;
972 }
973 if (rc)
974 break;
975 }
976
977 return rc;
978}
979
980/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000981 * Write a part of the flash chip.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000982 * FIXME: Use the chunk code from Michael Karcher instead.
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000983 * Each page is written separately in chunks with a maximum size of chunksize.
984 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000985int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int start,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000986 unsigned int len, unsigned int chunksize)
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000987{
988 int rc = 0;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000989 unsigned int i, j, starthere, lenhere, towrite;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000990 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000991 * in struct flashctx to do this properly. All chips using
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000992 * spi_chip_write_256 have page_size set to max_writechunk_size, so
993 * we're OK for now.
994 */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000995 unsigned int page_size = flash->chip->page_size;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000996
997 /* Warning: This loop has a very unusual condition and body.
998 * The loop needs to go through each page with at least one affected
999 * byte. The lowest page number is (start / page_size) since that
1000 * division rounds down. The highest page number we want is the page
1001 * where the last byte of the range lives. That last byte has the
1002 * address (start + len - 1), thus the highest page number is
1003 * (start + len - 1) / page_size. Since we want to include that last
1004 * page as well, the loop condition uses <=.
1005 */
1006 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
1007 /* Byte position of the first byte in the range in this page. */
1008 /* starthere is an offset to the base address of the chip. */
1009 starthere = max(start, i * page_size);
1010 /* Length of bytes in the range in this page. */
1011 lenhere = min(start + len, (i + 1) * page_size) - starthere;
1012 for (j = 0; j < lenhere; j += chunksize) {
1013 towrite = min(chunksize, lenhere - j);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001014 rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00001015 if (rc)
1016 break;
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001017 while (spi_read_status_register(flash) & SPI_SR_WIP)
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00001018 programmer_delay(10);
1019 }
1020 if (rc)
1021 break;
1022 }
1023
1024 return rc;
1025}
1026
1027/*
Sean Nelson14ba6682010-02-26 05:48:29 +00001028 * Program chip using byte programming. (SLOW!)
1029 * This is for chips which can only handle one byte writes
1030 * and for chips where memory mapped programming is impossible
1031 * (e.g. due to size constraints in IT87* for over 512 kB)
1032 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001033/* real chunksize is 1, logical chunksize is 1 */
Mark Marshallf20b7be2014-05-09 21:16:21 +00001034int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +00001035{
Stefan Taunerc69c9c82011-11-23 09:13:48 +00001036 unsigned int i;
1037 int result = 0;
Sean Nelson14ba6682010-02-26 05:48:29 +00001038
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001039 for (i = start; i < start + len; i++) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001040 result = spi_byte_program(flash, i, buf[i - start]);
Sean Nelson14ba6682010-02-26 05:48:29 +00001041 if (result)
1042 return 1;
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001043 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +00001044 programmer_delay(10);
1045 }
1046
1047 return 0;
1048}
1049
Mark Marshallf20b7be2014-05-09 21:16:21 +00001050int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001051{
1052 uint32_t pos = start;
Sean Nelson14ba6682010-02-26 05:48:29 +00001053 int result;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001054 unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = {
1055 JEDEC_AAI_WORD_PROGRAM,
1056 };
1057 struct spi_command cmds[] = {
1058 {
1059 .writecnt = JEDEC_WREN_OUTSIZE,
1060 .writearr = (const unsigned char[]){ JEDEC_WREN },
1061 .readcnt = 0,
1062 .readarr = NULL,
1063 }, {
1064 .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE,
1065 .writearr = (const unsigned char[]){
1066 JEDEC_AAI_WORD_PROGRAM,
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001067 (start >> 16) & 0xff,
1068 (start >> 8) & 0xff,
1069 (start & 0xff),
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001070 buf[0],
1071 buf[1]
1072 },
1073 .readcnt = 0,
1074 .readarr = NULL,
1075 }, {
1076 .writecnt = 0,
1077 .writearr = NULL,
1078 .readcnt = 0,
1079 .readarr = NULL,
1080 }};
Sean Nelson14ba6682010-02-26 05:48:29 +00001081
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001082 switch (flash->mst->spi.type) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +00001083#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001084#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001085 case SPI_CONTROLLER_IT87XX:
Sean Nelson14ba6682010-02-26 05:48:29 +00001086 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001087 msg_perr("%s: impossible with this SPI controller,"
Sean Nelson14ba6682010-02-26 05:48:29 +00001088 " degrading to byte program\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001089 return spi_chip_write_1(flash, buf, start, len);
Sean Nelson14ba6682010-02-26 05:48:29 +00001090#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001091#endif
Sean Nelson14ba6682010-02-26 05:48:29 +00001092 default:
1093 break;
1094 }
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001095
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001096 /* The even start address and even length requirements can be either
1097 * honored outside this function, or we can call spi_byte_program
1098 * for the first and/or last byte and use AAI for the rest.
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001099 * FIXME: Move this to generic code.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001100 */
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001101 /* The data sheet requires a start address with the low bit cleared. */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001102 if (start % 2) {
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001103 msg_cerr("%s: start address not even! Please report a bug at "
1104 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001105 if (spi_chip_write_1(flash, buf, start, start % 2))
1106 return SPI_GENERIC_ERROR;
1107 pos += start % 2;
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001108 cmds[1].writearr = (const unsigned char[]){
1109 JEDEC_AAI_WORD_PROGRAM,
1110 (pos >> 16) & 0xff,
1111 (pos >> 8) & 0xff,
1112 (pos & 0xff),
1113 buf[pos - start],
1114 buf[pos - start + 1]
1115 };
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001116 /* Do not return an error for now. */
1117 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001118 }
1119 /* The data sheet requires total AAI write length to be even. */
1120 if (len % 2) {
1121 msg_cerr("%s: total write length not even! Please report a "
1122 "bug at flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001123 /* Do not return an error for now. */
1124 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001125 }
1126
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001127
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001128 result = spi_send_multicommand(flash, cmds);
Stefan Reinauer87ace662014-04-26 16:12:55 +00001129 if (result != 0) {
1130 msg_cerr("%s failed during start command execution: %d\n", __func__, result);
1131 goto bailout;
Sean Nelson14ba6682010-02-26 05:48:29 +00001132 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001133 while (spi_read_status_register(flash) & SPI_SR_WIP)
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001134 programmer_delay(10);
1135
1136 /* We already wrote 2 bytes in the multicommand step. */
1137 pos += 2;
1138
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001139 /* Are there at least two more bytes to write? */
1140 while (pos < start + len - 1) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001141 cmd[1] = buf[pos++ - start];
1142 cmd[2] = buf[pos++ - start];
Stefan Reinauer87ace662014-04-26 16:12:55 +00001143 result = spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL);
1144 if (result != 0) {
1145 msg_cerr("%s failed during followup AAI command execution: %d\n", __func__, result);
1146 goto bailout;
1147 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001148 while (spi_read_status_register(flash) & SPI_SR_WIP)
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001149 programmer_delay(10);
1150 }
1151
Stefan Tauner59c4d792014-04-26 16:13:09 +00001152 /* Use WRDI to exit AAI mode. This needs to be done before issuing any other non-AAI command. */
1153 result = spi_write_disable(flash);
1154 if (result != 0) {
1155 msg_cerr("%s failed to disable AAI mode.\n", __func__);
1156 return SPI_GENERIC_ERROR;
1157 }
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001158
1159 /* Write remaining byte (if any). */
1160 if (pos < start + len) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001161 if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2))
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001162 return SPI_GENERIC_ERROR;
1163 pos += pos % 2;
1164 }
1165
Sean Nelson14ba6682010-02-26 05:48:29 +00001166 return 0;
Stefan Reinauer87ace662014-04-26 16:12:55 +00001167
1168bailout:
Stefan Tauner59c4d792014-04-26 16:13:09 +00001169 result = spi_write_disable(flash);
1170 if (result != 0)
1171 msg_cerr("%s failed to disable AAI mode.\n", __func__);
Stefan Reinauer87ace662014-04-26 16:12:55 +00001172 return SPI_GENERIC_ERROR;
Sean Nelson14ba6682010-02-26 05:48:29 +00001173}