blob: d89bef6ea45c19728cc6a9ee72d45486ae5c1a36 [file] [log] [blame]
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +00004 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
25#include <stdio.h>
26#include <pci/pci.h>
27#include <stdint.h>
28#include <string.h>
29#include "flash.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000030#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000031
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +000032
33void spi_prettyprint_status_register(struct flashchip *flash);
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000034
Peter Stugefa8c5502008-05-10 23:07:52 +000035int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +000036{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000037 switch (flashbus) {
38 case BUS_TYPE_IT87XX_SPI:
Carl-Daniel Hailfingera5b8efd2008-05-10 23:40:51 +000039 return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000040 case BUS_TYPE_ICH7_SPI:
41 case BUS_TYPE_ICH9_SPI:
42 case BUS_TYPE_VIA_SPI:
43 return ich_spi_command(writecnt, readcnt, writearr, readarr);
44 default:
45 printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
46 }
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +000047 return 1;
48}
49
Rudolf Marek48a85e42008-06-30 21:45:17 +000050static int spi_rdid(unsigned char *readarr, int bytes)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000051{
Carl-Daniel Hailfinger228231f2008-05-13 14:01:22 +000052 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID};
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000053
Rudolf Marek48a85e42008-06-30 21:45:17 +000054 if (spi_command(JEDEC_RDID_OUTSIZE, bytes, cmd, readarr))
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000055 return 1;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +000056 printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]);
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000057 return 0;
58}
59
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000060static int spi_res(unsigned char *readarr)
61{
62 const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0};
63
64 if (spi_command(JEDEC_RES_OUTSIZE, JEDEC_RES_INSIZE, cmd, readarr))
65 return 1;
66 printf_debug("RES returned %02x.\n", readarr[0]);
67 return 0;
68}
69
Peter Stugefa8c5502008-05-10 23:07:52 +000070void spi_write_enable()
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000071{
Carl-Daniel Hailfinger228231f2008-05-13 14:01:22 +000072 const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN};
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000073
74 /* Send WREN (Write Enable) */
Peter Stugefa8c5502008-05-10 23:07:52 +000075 spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000076}
77
Peter Stugefa8c5502008-05-10 23:07:52 +000078void spi_write_disable()
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000079{
Carl-Daniel Hailfinger228231f2008-05-13 14:01:22 +000080 const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI};
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000081
82 /* Send WRDI (Write Disable) */
Peter Stugefa8c5502008-05-10 23:07:52 +000083 spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +000084}
85
Rudolf Marek48a85e42008-06-30 21:45:17 +000086static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000087{
Rudolf Marek48a85e42008-06-30 21:45:17 +000088 unsigned char readarr[4];
Carl-Daniel Hailfinger1263d2a2008-02-06 22:07:58 +000089 uint32_t manuf_id;
90 uint32_t model_id;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +000091
Rudolf Marek48a85e42008-06-30 21:45:17 +000092 if (spi_rdid(readarr, bytes))
Peter Stugeda4e5f32008-06-24 01:22:03 +000093 return 0;
94
95 if (!oddparity(readarr[0]))
96 printf_debug("RDID byte 0 parity violation.\n");
97
98 /* Check if this is a continuation vendor ID */
99 if (readarr[0] == 0x7f) {
100 if (!oddparity(readarr[1]))
101 printf_debug("RDID byte 1 parity violation.\n");
102 manuf_id = (readarr[0] << 8) | readarr[1];
103 model_id = readarr[2];
Rudolf Marek48a85e42008-06-30 21:45:17 +0000104 if (bytes > 3) {
105 model_id <<= 8;
106 model_id |= readarr[3];
107 }
Peter Stugeda4e5f32008-06-24 01:22:03 +0000108 } else {
109 manuf_id = readarr[0];
110 model_id = (readarr[1] << 8) | readarr[2];
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000111 }
112
Peter Stugeda4e5f32008-06-24 01:22:03 +0000113 printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id);
114
115 if (manuf_id == flash->manufacture_id &&
116 model_id == flash->model_id) {
117 /* Print the status register to tell the
118 * user about possible write protection.
119 */
120 spi_prettyprint_status_register(flash);
121
122 return 1;
123 }
124
125 /* Test if this is a pure vendor match. */
126 if (manuf_id == flash->manufacture_id &&
127 GENERIC_DEVICE_ID == flash->model_id)
128 return 1;
129
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000130 return 0;
131}
132
Rudolf Marek48a85e42008-06-30 21:45:17 +0000133int probe_spi_rdid(struct flashchip *flash) {
134 return probe_spi_rdid_generic(flash, 3);
135}
136
137/* support 4 bytes flash ID */
138int probe_spi_rdid4(struct flashchip *flash) {
139
140 /* only some SPI chipsets support 4 bytes commands */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000141 switch (flashbus) {
142 case BUS_TYPE_ICH7_SPI:
143 case BUS_TYPE_ICH9_SPI:
144 case BUS_TYPE_VIA_SPI:
145 return probe_spi_rdid_generic(flash, 4);
146 default:
147 printf_debug("4b ID not supported on this SPI controller\n");
148 }
149
150 return 0;
Rudolf Marek48a85e42008-06-30 21:45:17 +0000151}
152
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000153int probe_spi_res(struct flashchip *flash)
154{
155 unsigned char readarr[3];
156 uint32_t model_id;
Peter Stugeda4e5f32008-06-24 01:22:03 +0000157
Rudolf Marek48a85e42008-06-30 21:45:17 +0000158 if (spi_rdid(readarr, 3))
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000159 /* We couldn't issue RDID, it's pointless to try RES. */
160 return 0;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000161
Peter Stugeda4e5f32008-06-24 01:22:03 +0000162 /* Check if RDID returns 0xff 0xff 0xff, then we use RES. */
163 if ((readarr[0] != 0xff) || (readarr[1] != 0xff) ||
164 (readarr[2] != 0xff))
165 return 0;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000166
Peter Stugeda4e5f32008-06-24 01:22:03 +0000167 if (spi_res(readarr))
168 return 0;
169
170 model_id = readarr[0];
171 printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id);
172 if (model_id != flash->model_id)
173 return 0;
174
175 /* Print the status register to tell the
176 * user about possible write protection.
177 */
178 spi_prettyprint_status_register(flash);
179 return 1;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000180}
181
Peter Stugefa8c5502008-05-10 23:07:52 +0000182uint8_t spi_read_status_register()
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000183{
Carl-Daniel Hailfinger228231f2008-05-13 14:01:22 +0000184 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR};
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000185 unsigned char readarr[1];
186
187 /* Read Status Register */
Peter Stugefa8c5502008-05-10 23:07:52 +0000188 spi_command(JEDEC_RDSR_OUTSIZE, JEDEC_RDSR_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000189 return readarr[0];
190}
191
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000192/* Prettyprint the status register. Common definitions.
193 */
194void spi_prettyprint_status_register_common(uint8_t status)
195{
196 printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
197 "%sset\n", (status & (1 << 5)) ? "" : "not ");
198 printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
199 "%sset\n", (status & (1 << 4)) ? "" : "not ");
200 printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
201 "%sset\n", (status & (1 << 3)) ? "" : "not ");
202 printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
203 "%sset\n", (status & (1 << 2)) ? "" : "not ");
204 printf_debug("Chip status register: Write Enable Latch (WEL) is "
205 "%sset\n", (status & (1 << 1)) ? "" : "not ");
206 printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
207 "%sset\n", (status & (1 << 0)) ? "" : "not ");
208}
209
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000210/* Prettyprint the status register. Works for
211 * ST M25P series
212 * MX MX25L series
213 */
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000214void spi_prettyprint_status_register_st_m25p(uint8_t status)
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000215{
216 printf_debug("Chip status register: Status Register Write Disable "
217 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
218 printf_debug("Chip status register: Bit 6 is "
219 "%sset\n", (status & (1 << 6)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000220 spi_prettyprint_status_register_common(status);
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000221}
222
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000223/* Prettyprint the status register. Works for
224 * SST 25VF016
225 */
226void spi_prettyprint_status_register_sst25vf016(uint8_t status)
227{
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000228 const char *bpt[] = {
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000229 "none",
230 "1F0000H-1FFFFFH",
231 "1E0000H-1FFFFFH",
232 "1C0000H-1FFFFFH",
233 "180000H-1FFFFFH",
234 "100000H-1FFFFFH",
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000235 "all", "all"
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000236 };
237 printf_debug("Chip status register: Block Protect Write Disable "
238 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
239 printf_debug("Chip status register: Auto Address Increment Programming "
240 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
241 spi_prettyprint_status_register_common(status);
242 printf_debug("Resulting block protection : %s\n",
243 bpt[(status & 0x1c) >> 2]);
244}
245
246void spi_prettyprint_status_register(struct flashchip *flash)
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000247{
248 uint8_t status;
249
Peter Stugefa8c5502008-05-10 23:07:52 +0000250 status = spi_read_status_register();
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000251 printf_debug("Chip status register is %02x\n", status);
252 switch (flash->manufacture_id) {
253 case ST_ID:
Carl-Daniel Hailfingerf43e6422008-05-15 22:32:08 +0000254 if (((flash->model_id & 0xff00) == 0x2000) ||
255 ((flash->model_id & 0xff00) == 0x2500))
256 spi_prettyprint_status_register_st_m25p(status);
257 break;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000258 case MX_ID:
259 if ((flash->model_id & 0xff00) == 0x2000)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000260 spi_prettyprint_status_register_st_m25p(status);
261 break;
262 case SST_ID:
263 if (flash->model_id == SST_25VF016B)
264 spi_prettyprint_status_register_sst25vf016(status);
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000265 break;
266 }
267}
268
Peter Stugefa8c5502008-05-10 23:07:52 +0000269int spi_chip_erase_c7(struct flashchip *flash)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000270{
Carl-Daniel Hailfinger228231f2008-05-13 14:01:22 +0000271 const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7};
Carl-Daniel Hailfingerf5df46f2007-12-16 21:15:27 +0000272
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000273 spi_disable_blockprotect();
Peter Stugefa8c5502008-05-10 23:07:52 +0000274 spi_write_enable();
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000275 /* Send CE (Chip Erase) */
Peter Stugefa8c5502008-05-10 23:07:52 +0000276 spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000277 /* Wait until the Write-In-Progress bit is cleared.
278 * This usually takes 1-85 s, so wait in 1 s steps.
279 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000280 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000281 sleep(1);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000282 return 0;
283}
284
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000285/* Block size is usually
286 * 64k for Macronix
287 * 32k for SST
288 * 4-32k non-uniform for EON
289 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000290int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000291{
Carl-Daniel Hailfinger228231f2008-05-13 14:01:22 +0000292 unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = {JEDEC_BE_D8};
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000293
294 cmd[1] = (addr & 0x00ff0000) >> 16;
295 cmd[2] = (addr & 0x0000ff00) >> 8;
296 cmd[3] = (addr & 0x000000ff);
Peter Stugefa8c5502008-05-10 23:07:52 +0000297 spi_write_enable();
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000298 /* Send BE (Block Erase) */
Peter Stugefa8c5502008-05-10 23:07:52 +0000299 spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000300 /* Wait until the Write-In-Progress bit is cleared.
301 * This usually takes 100-4000 ms, so wait in 100 ms steps.
302 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000303 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000304 usleep(100 * 1000);
305 return 0;
306}
307
308/* Sector size is usually 4k, though Macronix eliteflash has 64k */
Peter Stugefa8c5502008-05-10 23:07:52 +0000309int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000310{
Carl-Daniel Hailfinger228231f2008-05-13 14:01:22 +0000311 unsigned char cmd[JEDEC_SE_OUTSIZE] = {JEDEC_SE};
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000312 cmd[1] = (addr & 0x00ff0000) >> 16;
313 cmd[2] = (addr & 0x0000ff00) >> 8;
314 cmd[3] = (addr & 0x000000ff);
315
Peter Stugefa8c5502008-05-10 23:07:52 +0000316 spi_write_enable();
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000317 /* Send SE (Sector Erase) */
Peter Stugefa8c5502008-05-10 23:07:52 +0000318 spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000319 /* Wait until the Write-In-Progress bit is cleared.
320 * This usually takes 15-800 ms, so wait in 10 ms steps.
321 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000322 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000323 usleep(10 * 1000);
324 return 0;
325}
326
Peter Stugefa8c5502008-05-10 23:07:52 +0000327void spi_page_program(int block, uint8_t *buf, uint8_t *bios)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000328{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000329 switch (flashbus) {
330 case BUS_TYPE_IT87XX_SPI:
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000331 it8716f_spi_page_program(block, buf, bios);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000332 break;
333 case BUS_TYPE_ICH7_SPI:
334 case BUS_TYPE_ICH9_SPI:
335 printf_debug("%s called, but not implemented for ICH\n", __FUNCTION__);
336 break;
337 default:
338 printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000339 }
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000340}
341
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000342/*
343 * This is according the SST25VF016 datasheet, who knows it is more
344 * generic that this...
345 */
346void spi_write_status_register(int status)
347{
Carl-Daniel Hailfinger228231f2008-05-13 14:01:22 +0000348 const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status};
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000349
350 /* Send WRSR (Write Status Register) */
Peter Stugefa8c5502008-05-10 23:07:52 +0000351 spi_command(JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000352}
353
354void spi_byte_program(int address, uint8_t byte)
355{
356 const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {JEDEC_BYTE_PROGRAM,
357 (address>>16)&0xff,
358 (address>>8)&0xff,
359 (address>>0)&0xff,
360 byte
361 };
362
363 /* Send Byte-Program */
Peter Stugefa8c5502008-05-10 23:07:52 +0000364 spi_command(JEDEC_BYTE_PROGRAM_OUTSIZE, JEDEC_BYTE_PROGRAM_INSIZE, cmd, NULL);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000365}
366
367void spi_disable_blockprotect(void)
368{
369 uint8_t status;
370
Peter Stugefa8c5502008-05-10 23:07:52 +0000371 status = spi_read_status_register();
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000372 /* If there is block protection in effect, unprotect it first. */
373 if ((status & 0x3c) != 0) {
374 printf_debug("Some block protection in effect, disabling\n");
Peter Stugefa8c5502008-05-10 23:07:52 +0000375 spi_write_enable();
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000376 spi_write_status_register(status & ~0x3c);
377 }
378}
379
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000380void spi_nbyte_read(int address, uint8_t *bytes, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000381{
382 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ,
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000383 (address >> 16) & 0xff,
384 (address >> 8) & 0xff,
385 (address >> 0) & 0xff,
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000386 };
387
388 /* Send Read */
Peter Stugefa8c5502008-05-10 23:07:52 +0000389 spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000390}
391
Peter Stugefa8c5502008-05-10 23:07:52 +0000392int spi_chip_read(struct flashchip *flash, uint8_t *buf)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000393{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000394
395 switch (flashbus) {
396 case BUS_TYPE_IT87XX_SPI:
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000397 return it8716f_spi_chip_read(flash, buf);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000398 case BUS_TYPE_ICH7_SPI:
399 case BUS_TYPE_ICH9_SPI:
400 case BUS_TYPE_VIA_SPI:
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000401 return ich_spi_read(flash, buf);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000402 default:
403 printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
404 }
405
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000406 return 1;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000407}
408
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000409int spi_chip_write(struct flashchip *flash, uint8_t *buf)
410{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000411 switch (flashbus) {
412 case BUS_TYPE_IT87XX_SPI:
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000413 return it8716f_spi_chip_write(flash, buf);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000414 case BUS_TYPE_ICH7_SPI:
415 case BUS_TYPE_ICH9_SPI:
416 case BUS_TYPE_VIA_SPI:
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000417 return ich_spi_write(flash, buf);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000418 default:
419 printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
420 }
421
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000422 return 1;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000423}
424