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Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __SPI_H__
21#define __SPI_H__ 1
22
23/*
24 * Contains the generic SPI headers
25 */
26
27/* Read Electronic ID */
28#define JEDEC_RDID 0x9f
29#define JEDEC_RDID_OUTSIZE 0x01
30#define JEDEC_RDID_INSIZE 0x03
31
Carl-Daniel Hailfinger0faf03e2008-11-28 23:47:55 +000032/* AT25F512A has bit 3 as don't care bit in commands */
33#define AT25F512A_RDID 0x15
34#define AT25F512A_RDID_OUTSIZE 0x01
35#define AT25F512A_RDID_INSIZE 0x02
36
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +000037/* Read Electronic Manufacturer Signature */
38#define JEDEC_REMS 0x90
39#define JEDEC_REMS_OUTSIZE 0x04
40#define JEDEC_REMS_INSIZE 0x02
41
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000042/* Read Electronic Signature */
43#define JEDEC_RES 0xab
44#define JEDEC_RES_OUTSIZE 0x04
45#define JEDEC_RES_INSIZE 0x01
46
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000047/* Write Enable */
48#define JEDEC_WREN 0x06
49#define JEDEC_WREN_OUTSIZE 0x01
50#define JEDEC_WREN_INSIZE 0x00
51
52/* Write Disable */
53#define JEDEC_WRDI 0x04
54#define JEDEC_WRDI_OUTSIZE 0x01
55#define JEDEC_WRDI_INSIZE 0x00
56
57/* Chip Erase 0x60 is supported by Macronix/SST chips. */
58#define JEDEC_CE_60 0x60
59#define JEDEC_CE_60_OUTSIZE 0x01
60#define JEDEC_CE_60_INSIZE 0x00
61
Peter Stugef83221b2008-07-07 06:38:51 +000062/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000063#define JEDEC_CE_C7 0xc7
64#define JEDEC_CE_C7_OUTSIZE 0x01
65#define JEDEC_CE_C7_INSIZE 0x00
66
Carl-Daniel Hailfingerd54ef6e2008-11-15 13:55:43 +000067/* Block Erase 0x52 is supported by SST and old Atmel chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000068#define JEDEC_BE_52 0x52
69#define JEDEC_BE_52_OUTSIZE 0x04
70#define JEDEC_BE_52_INSIZE 0x00
71
72/* Block Erase 0xd8 is supported by EON/Macronix chips. */
73#define JEDEC_BE_D8 0xd8
74#define JEDEC_BE_D8_OUTSIZE 0x04
75#define JEDEC_BE_D8_INSIZE 0x00
76
77/* Sector Erase 0x20 is supported by Macronix/SST chips. */
78#define JEDEC_SE 0x20
79#define JEDEC_SE_OUTSIZE 0x04
80#define JEDEC_SE_INSIZE 0x00
81
82/* Read Status Register */
83#define JEDEC_RDSR 0x05
84#define JEDEC_RDSR_OUTSIZE 0x01
85#define JEDEC_RDSR_INSIZE 0x01
86#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
87
Jason Wanga3f04be2008-11-28 21:36:51 +000088/* Write Status Enable */
89#define JEDEC_EWSR 0x50
90#define JEDEC_EWSR_OUTSIZE 0x01
91#define JEDEC_EWSR_INSIZE 0x00
92
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000093/* Write Status Register */
94#define JEDEC_WRSR 0x01
95#define JEDEC_WRSR_OUTSIZE 0x02
96#define JEDEC_WRSR_INSIZE 0x00
97
98/* Read the memory */
99#define JEDEC_READ 0x03
100#define JEDEC_READ_OUTSIZE 0x04
101/* JEDEC_READ_INSIZE : any length */
102
103/* Write memory byte */
104#define JEDEC_BYTE_PROGRAM 0x02
105#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
106#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
107
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000108/* Error codes */
109#define SPI_INVALID_OPCODE -2
110#define SPI_INVALID_ADDRESS -3
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000111#define SPI_INVALID_LENGTH -4
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000112
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000113#endif /* !__SPI_H__ */