blob: 1522c9b3f0d0d50f401e46d843a7d081bb4d8e9a [file] [log] [blame]
Idwer Vollering004f4b72010-09-03 18:21:21 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Carl-Daniel Hailfinger
5 * Copyright (C) 2010 Idwer Vollering
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
Bill Paulbf8ea492014-03-17 22:07:29 +000022 * Datasheets:
Idwer Vollering004f4b72010-09-03 18:21:21 +000023 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
24 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
Bill Paulbf8ea492014-03-17 22:07:29 +000025 * http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x-family-gbe-controllers-software-dev-manual.html
26 *
27 * PCIe GbE Controllers Open Source Software Developer's Manual
28 * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe-controllers-open-source-manual.html
29 *
30 * Intel 82574 Gigabit Ethernet Controller Family Datasheet
31 * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-controller-datasheet.html
Idwer Vollering004f4b72010-09-03 18:21:21 +000032 */
33
34#include <stdlib.h>
Stefan Tauner6745d6f2012-08-26 21:50:36 +000035#include <unistd.h>
Idwer Vollering004f4b72010-09-03 18:21:21 +000036#include "flash.h"
37#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000038#include "hwaccess.h"
Idwer Vollering004f4b72010-09-03 18:21:21 +000039
40#define PCI_VENDOR_ID_INTEL 0x8086
Stefan Tauner6745d6f2012-08-26 21:50:36 +000041#define MEMMAP_SIZE getpagesize()
Idwer Vollering004f4b72010-09-03 18:21:21 +000042
Stefan Tauner8ee180d2012-02-27 19:44:16 +000043/* EEPROM/Flash Control & Data Register */
Idwer Vollering004f4b72010-09-03 18:21:21 +000044#define EECD 0x10
Stefan Tauner8ee180d2012-02-27 19:44:16 +000045/* Flash Access Register */
Idwer Vollering004f4b72010-09-03 18:21:21 +000046#define FLA 0x1c
47
48/*
49 * Register bits of EECD.
Stefan Tauner8ee180d2012-02-27 19:44:16 +000050 * Table 13-6
51 *
Idwer Vollering004f4b72010-09-03 18:21:21 +000052 * Bit 04, 05: FWE (Flash Write Enable Control)
53 * 00b = not allowed
54 * 01b = flash writes disabled
55 * 10b = flash writes enabled
56 * 11b = not allowed
57 */
58#define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
59#define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
60
Stefan Tauner8ee180d2012-02-27 19:44:16 +000061/* Flash Access register bits
62 * Table 13-9
63 */
Idwer Vollering004f4b72010-09-03 18:21:21 +000064#define FL_SCK 0
65#define FL_CS 1
66#define FL_SI 2
67#define FL_SO 3
68#define FL_REQ 4
69#define FL_GNT 5
70/* Currently unused */
71// #define FL_BUSY 30
72// #define FL_ER 31
73
74uint8_t *nicintel_spibar;
75
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000076const struct dev_entry nics_intel_spi[] = {
Idwer Volleringbdc48272010-10-05 11:16:14 +000077 {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"},
Stefan Tauner4b90e6b2011-05-18 01:31:24 +000078 {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"},
Idwer Vollering004f4b72010-09-03 18:21:21 +000079 {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},
Idwer Volleringbdc48272010-10-05 11:16:14 +000080 {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"},
Bill Paulbf8ea492014-03-17 22:07:29 +000081 {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"},
Idwer Vollering004f4b72010-09-03 18:21:21 +000082
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000083 {0},
Idwer Vollering004f4b72010-09-03 18:21:21 +000084};
85
86static void nicintel_request_spibus(void)
87{
88 uint32_t tmp;
89
90 tmp = pci_mmio_readl(nicintel_spibar + FLA);
91 tmp |= 1 << FL_REQ;
92 pci_mmio_writel(tmp, nicintel_spibar + FLA);
93
94 /* Wait until we are allowed to use the SPI bus. */
95 while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ;
96}
97
98static void nicintel_release_spibus(void)
99{
100 uint32_t tmp;
101
102 tmp = pci_mmio_readl(nicintel_spibar + FLA);
103 tmp &= ~(1 << FL_REQ);
104 pci_mmio_writel(tmp, nicintel_spibar + FLA);
105}
106
107static void nicintel_bitbang_set_cs(int val)
108{
109 uint32_t tmp;
110
Idwer Vollering004f4b72010-09-03 18:21:21 +0000111 tmp = pci_mmio_readl(nicintel_spibar + FLA);
112 tmp &= ~(1 << FL_CS);
113 tmp |= (val << FL_CS);
114 pci_mmio_writel(tmp, nicintel_spibar + FLA);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000115}
116
117static void nicintel_bitbang_set_sck(int val)
118{
119 uint32_t tmp;
120
121 tmp = pci_mmio_readl(nicintel_spibar + FLA);
122 tmp &= ~(1 << FL_SCK);
123 tmp |= (val << FL_SCK);
124 pci_mmio_writel(tmp, nicintel_spibar + FLA);
125}
126
127static void nicintel_bitbang_set_mosi(int val)
128{
129 uint32_t tmp;
130
131 tmp = pci_mmio_readl(nicintel_spibar + FLA);
132 tmp &= ~(1 << FL_SI);
133 tmp |= (val << FL_SI);
134 pci_mmio_writel(tmp, nicintel_spibar + FLA);
135}
136
137static int nicintel_bitbang_get_miso(void)
138{
139 uint32_t tmp;
140
141 tmp = pci_mmio_readl(nicintel_spibar + FLA);
142 tmp = (tmp >> FL_SO) & 0x1;
143 return tmp;
144}
145
146static const struct bitbang_spi_master bitbang_spi_master_nicintel = {
147 .type = BITBANG_SPI_MASTER_NICINTEL,
148 .set_cs = nicintel_bitbang_set_cs,
149 .set_sck = nicintel_bitbang_set_sck,
150 .set_mosi = nicintel_bitbang_set_mosi,
151 .get_miso = nicintel_bitbang_get_miso,
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000152 .request_bus = nicintel_request_spibus,
153 .release_bus = nicintel_release_spibus,
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000154 .half_period = 1,
Idwer Vollering004f4b72010-09-03 18:21:21 +0000155};
156
David Hendricks8bb20212011-06-14 01:35:36 +0000157static int nicintel_spi_shutdown(void *data)
158{
159 uint32_t tmp;
160
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000161 /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */
David Hendricks8bb20212011-06-14 01:35:36 +0000162 tmp = pci_mmio_readl(nicintel_spibar + EECD);
163 tmp &= ~FLASH_WRITES_ENABLED;
164 tmp |= FLASH_WRITES_DISABLED;
165 pci_mmio_writel(tmp, nicintel_spibar + EECD);
166
David Hendricks8bb20212011-06-14 01:35:36 +0000167 return 0;
168}
169
Idwer Vollering004f4b72010-09-03 18:21:21 +0000170int nicintel_spi_init(void)
171{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000172 struct pci_dev *dev = NULL;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000173 uint32_t tmp;
174
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000175 if (rget_io_perms())
176 return 1;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000177
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000178 dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0);
179 if (!dev)
180 return 1;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000181
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000182 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000183 if (!io_base_addr)
184 return 1;
185
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000186 nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE);
Niklas Söderlund5d307202013-09-14 09:02:27 +0000187 if (nicintel_spibar == ERROR_PTR)
188 return 1;
189
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000190 /* Automatic restore of EECD on shutdown is not possible because EECD
191 * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED,
192 * but other bits with side effects as well. Those other bits must be
193 * left untouched.
194 */
Idwer Vollering004f4b72010-09-03 18:21:21 +0000195 tmp = pci_mmio_readl(nicintel_spibar + EECD);
196 tmp &= ~FLASH_WRITES_DISABLED;
197 tmp |= FLASH_WRITES_ENABLED;
198 pci_mmio_writel(tmp, nicintel_spibar + EECD);
199
Stefan Tauner8ee180d2012-02-27 19:44:16 +0000200 /* test if FWE is really set to allow writes */
201 tmp = pci_mmio_readl(nicintel_spibar + EECD);
202 if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
203 msg_perr("Enabling flash write access failed.\n");
204 return 1;
205 }
206
David Hendricks8bb20212011-06-14 01:35:36 +0000207 if (register_shutdown(nicintel_spi_shutdown, NULL))
208 return 1;
209
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000210 if (bitbang_spi_init(&bitbang_spi_master_nicintel))
Idwer Vollering004f4b72010-09-03 18:21:21 +0000211 return 1;
212
Idwer Vollering004f4b72010-09-03 18:21:21 +0000213 return 0;
214}