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Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000025#include <string.h>
26#include "flash.h"
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000027#include "flashchips.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000028#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000029
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000030enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
31void *spibar = NULL;
32
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +000033void spi_prettyprint_status_register(struct flashchip *flash);
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000034
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000035const struct spi_programmer spi_programmer[] = {
36 { /* SPI_CONTROLLER_NONE */
37 .command = NULL,
38 .multicommand = NULL,
39 .read = NULL,
40 .write_256 = NULL,
41 },
42
43 { /* SPI_CONTROLLER_ICH7 */
44 .command = ich_spi_send_command,
45 .multicommand = ich_spi_send_multicommand,
46 .read = ich_spi_read,
47 .write_256 = ich_spi_write_256,
48 },
49
50 { /* SPI_CONTROLLER_ICH9 */
51 .command = ich_spi_send_command,
52 .multicommand = ich_spi_send_multicommand,
53 .read = ich_spi_read,
54 .write_256 = ich_spi_write_256,
55 },
56
57 { /* SPI_CONTROLLER_IT87XX */
58 .command = it8716f_spi_send_command,
59 .multicommand = default_spi_send_multicommand,
60 .read = it8716f_spi_chip_read,
61 .write_256 = it8716f_spi_chip_write_256,
62 },
63
64 { /* SPI_CONTROLLER_SB600 */
65 .command = sb600_spi_send_command,
66 .multicommand = default_spi_send_multicommand,
67 .read = sb600_spi_read,
68 .write_256 = sb600_spi_write_1,
69 },
70
71 { /* SPI_CONTROLLER_VIA */
72 .command = ich_spi_send_command,
73 .multicommand = ich_spi_send_multicommand,
74 .read = ich_spi_read,
75 .write_256 = ich_spi_write_256,
76 },
77
78 { /* SPI_CONTROLLER_WBSIO */
79 .command = wbsio_spi_send_command,
80 .multicommand = default_spi_send_multicommand,
81 .read = wbsio_spi_read,
82 .write_256 = wbsio_spi_write_1,
83 },
84
85 { /* SPI_CONTROLLER_FT2232 */
86 .command = ft2232_spi_send_command,
87 .multicommand = default_spi_send_multicommand,
88 .read = ft2232_spi_read,
89 .write_256 = ft2232_spi_write_256,
90 },
91
92 { /* SPI_CONTROLLER_DUMMY */
93 .command = dummy_spi_send_command,
94 .multicommand = default_spi_send_multicommand,
95 .read = NULL,
96 .write_256 = NULL,
97 },
98};
99
100
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000101int spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000102 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000103{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000104 if (!spi_programmer[spi_controller].command) {
105 fprintf(stderr, "%s called, but SPI is unsupported on this "
106 "hardware. Please report a bug.\n", __func__);
107 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000108 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000109
110 return spi_programmer[spi_controller].command(writecnt, readcnt,
111 writearr, readarr);
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000112}
113
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000114int spi_send_multicommand(struct spi_command *spicommands)
115{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000116 if (!spi_programmer[spi_controller].multicommand) {
117 fprintf(stderr, "%s called, but SPI is unsupported on this "
118 "hardware. Please report a bug.\n", __func__);
119 return 1;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000120 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000121
122 return spi_programmer[spi_controller].multicommand(spicommands);
123}
124
125int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
126 const unsigned char *writearr, unsigned char *readarr)
127{
128 struct spi_command cmd[] = {
129 {
130 .writecnt = writecnt,
131 .readcnt = readcnt,
132 .writearr = writearr,
133 .readarr = readarr,
134 }, {
135 .writecnt = 0,
136 .writearr = NULL,
137 .readcnt = 0,
138 .readarr = NULL,
139 }};
140
141 return spi_send_multicommand(cmd);
142}
143
144int default_spi_send_multicommand(struct spi_command *spicommands)
145{
146 int result = 0;
147 while ((spicommands->writecnt || spicommands->readcnt) && !result) {
148 result = spi_send_command(spicommands->writecnt, spicommands->readcnt,
149 spicommands->writearr, spicommands->readarr);
Carl-Daniel Hailfinger5b2f52f2009-08-03 09:35:20 +0000150 spicommands++;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000151 }
152 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000153}
154
Rudolf Marek48a85e42008-06-30 21:45:17 +0000155static int spi_rdid(unsigned char *readarr, int bytes)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000156{
Uwe Hermann394131e2008-10-18 21:14:13 +0000157 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000158 int ret;
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +0000159 int i;
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000160
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000161 ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000162 if (ret)
163 return ret;
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +0000164 printf_debug("RDID returned");
165 for (i = 0; i < bytes; i++)
166 printf_debug(" 0x%02x", readarr[i]);
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000167 printf_debug(". ");
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000168 return 0;
169}
170
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000171static int spi_rems(unsigned char *readarr)
172{
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000173 unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
174 uint32_t readaddr;
175 int ret;
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000176
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000177 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000178 if (ret == SPI_INVALID_ADDRESS) {
179 /* Find the lowest even address allowed for reads. */
180 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
181 cmd[1] = (readaddr >> 16) & 0xff,
182 cmd[2] = (readaddr >> 8) & 0xff,
183 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000184 ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000185 }
186 if (ret)
187 return ret;
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000188 printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]);
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000189 return 0;
190}
191
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000192static int spi_res(unsigned char *readarr)
193{
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000194 unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
195 uint32_t readaddr;
196 int ret;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000197
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000198 ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000199 if (ret == SPI_INVALID_ADDRESS) {
200 /* Find the lowest even address allowed for reads. */
201 readaddr = (spi_get_valid_read_addr() + 1) & ~1;
202 cmd[1] = (readaddr >> 16) & 0xff,
203 cmd[2] = (readaddr >> 8) & 0xff,
204 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000205 ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000206 }
207 if (ret)
208 return ret;
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000209 printf_debug("RES returned %02x. ", readarr[0]);
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000210 return 0;
211}
212
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000213int spi_write_enable(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000214{
Uwe Hermann394131e2008-10-18 21:14:13 +0000215 const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000216 int result;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000217
218 /* Send WREN (Write Enable) */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000219 result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000220
221 if (result)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000222 fprintf(stderr, "%s failed\n", __func__);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000223
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000224 return result;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000225}
226
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000227int spi_write_disable(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000228{
Uwe Hermann394131e2008-10-18 21:14:13 +0000229 const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000230
231 /* Send WRDI (Write Disable) */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000232 return spi_send_command(sizeof(cmd), 0, cmd, NULL);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000233}
234
Rudolf Marek48a85e42008-06-30 21:45:17 +0000235static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000236{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000237 unsigned char readarr[4];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000238 uint32_t id1;
239 uint32_t id2;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000240
Rudolf Marek48a85e42008-06-30 21:45:17 +0000241 if (spi_rdid(readarr, bytes))
Peter Stugeda4e5f32008-06-24 01:22:03 +0000242 return 0;
243
244 if (!oddparity(readarr[0]))
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000245 printf_debug("RDID byte 0 parity violation. ");
Peter Stugeda4e5f32008-06-24 01:22:03 +0000246
247 /* Check if this is a continuation vendor ID */
248 if (readarr[0] == 0x7f) {
249 if (!oddparity(readarr[1]))
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000250 printf_debug("RDID byte 1 parity violation. ");
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000251 id1 = (readarr[0] << 8) | readarr[1];
252 id2 = readarr[2];
Rudolf Marek48a85e42008-06-30 21:45:17 +0000253 if (bytes > 3) {
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000254 id2 <<= 8;
255 id2 |= readarr[3];
Rudolf Marek48a85e42008-06-30 21:45:17 +0000256 }
Peter Stugeda4e5f32008-06-24 01:22:03 +0000257 } else {
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000258 id1 = readarr[0];
259 id2 = (readarr[1] << 8) | readarr[2];
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000260 }
261
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000262 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2);
Peter Stugeda4e5f32008-06-24 01:22:03 +0000263
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000264 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
Peter Stugeda4e5f32008-06-24 01:22:03 +0000265 /* Print the status register to tell the
266 * user about possible write protection.
267 */
268 spi_prettyprint_status_register(flash);
269
270 return 1;
271 }
272
273 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000274 if (id1 == flash->manufacture_id &&
Peter Stugeda4e5f32008-06-24 01:22:03 +0000275 GENERIC_DEVICE_ID == flash->model_id)
276 return 1;
277
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +0000278 return 0;
279}
280
Uwe Hermann394131e2008-10-18 21:14:13 +0000281int probe_spi_rdid(struct flashchip *flash)
282{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000283 return probe_spi_rdid_generic(flash, 3);
284}
285
286/* support 4 bytes flash ID */
Uwe Hermann394131e2008-10-18 21:14:13 +0000287int probe_spi_rdid4(struct flashchip *flash)
288{
Rudolf Marek48a85e42008-06-30 21:45:17 +0000289 /* only some SPI chipsets support 4 bytes commands */
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000290 switch (spi_controller) {
291 case SPI_CONTROLLER_ICH7:
292 case SPI_CONTROLLER_ICH9:
293 case SPI_CONTROLLER_VIA:
294 case SPI_CONTROLLER_SB600:
295 case SPI_CONTROLLER_WBSIO:
Paul Fox05dfbe62009-06-16 21:08:06 +0000296 case SPI_CONTROLLER_FT2232:
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000297 case SPI_CONTROLLER_DUMMY:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000298 return probe_spi_rdid_generic(flash, 4);
299 default:
300 printf_debug("4b ID not supported on this SPI controller\n");
301 }
302
303 return 0;
Rudolf Marek48a85e42008-06-30 21:45:17 +0000304}
305
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000306int probe_spi_rems(struct flashchip *flash)
307{
308 unsigned char readarr[JEDEC_REMS_INSIZE];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000309 uint32_t id1, id2;
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000310
311 if (spi_rems(readarr))
312 return 0;
313
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000314 id1 = readarr[0];
315 id2 = readarr[1];
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000316
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000317 printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000318
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000319 if (id1 == flash->manufacture_id && id2 == flash->model_id) {
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000320 /* Print the status register to tell the
321 * user about possible write protection.
322 */
323 spi_prettyprint_status_register(flash);
324
325 return 1;
326 }
327
328 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000329 if (id1 == flash->manufacture_id &&
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000330 GENERIC_DEVICE_ID == flash->model_id)
331 return 1;
332
333 return 0;
334}
335
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000336int probe_spi_res(struct flashchip *flash)
337{
338 unsigned char readarr[3];
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000339 uint32_t id2;
Peter Stugeda4e5f32008-06-24 01:22:03 +0000340
Carl-Daniel Hailfinger92a54ca2008-11-27 22:48:48 +0000341 /* Check if RDID was successful and did not return 0xff 0xff 0xff.
342 * In that case, RES is pointless.
343 */
344 if (!spi_rdid(readarr, 3) && ((readarr[0] != 0xff) ||
345 (readarr[1] != 0xff) || (readarr[2] != 0xff)))
Peter Stugeda4e5f32008-06-24 01:22:03 +0000346 return 0;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000347
Peter Stugeda4e5f32008-06-24 01:22:03 +0000348 if (spi_res(readarr))
349 return 0;
350
Carl-Daniel Hailfinger2ad267d2009-05-27 11:40:08 +0000351 id2 = readarr[0];
352 printf_debug("%s: id 0x%x\n", __FUNCTION__, id2);
353 if (id2 != flash->model_id)
Peter Stugeda4e5f32008-06-24 01:22:03 +0000354 return 0;
355
356 /* Print the status register to tell the
357 * user about possible write protection.
358 */
359 spi_prettyprint_status_register(flash);
360 return 1;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000361}
362
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000363uint8_t spi_read_status_register(void)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000364{
Uwe Hermann394131e2008-10-18 21:14:13 +0000365 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000366 /* FIXME: No workarounds for driver/hardware bugs in generic code. */
Peter Stugebf196e92009-01-26 03:08:45 +0000367 unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000368 int ret;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000369
370 /* Read Status Register */
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000371 ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
372 if (ret)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000373 fprintf(stderr, "RDSR failed!\n");
Jason Wanga3f04be2008-11-28 21:36:51 +0000374
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000375 return readarr[0];
376}
377
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000378/* Prettyprint the status register. Common definitions. */
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000379void spi_prettyprint_status_register_common(uint8_t status)
380{
381 printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000382 "%sset\n", (status & (1 << 5)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000383 printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000384 "%sset\n", (status & (1 << 4)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000385 printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000386 "%sset\n", (status & (1 << 3)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000387 printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000388 "%sset\n", (status & (1 << 2)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000389 printf_debug("Chip status register: Write Enable Latch (WEL) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000390 "%sset\n", (status & (1 << 1)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000391 printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000392 "%sset\n", (status & (1 << 0)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000393}
394
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000395/* Prettyprint the status register. Works for
396 * ST M25P series
397 * MX MX25L series
398 */
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000399void spi_prettyprint_status_register_st_m25p(uint8_t status)
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000400{
401 printf_debug("Chip status register: Status Register Write Disable "
Uwe Hermann394131e2008-10-18 21:14:13 +0000402 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000403 printf_debug("Chip status register: Bit 6 is "
Uwe Hermann394131e2008-10-18 21:14:13 +0000404 "%sset\n", (status & (1 << 6)) ? "" : "not ");
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000405 spi_prettyprint_status_register_common(status);
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000406}
407
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000408void spi_prettyprint_status_register_sst25(uint8_t status)
409{
410 printf_debug("Chip status register: Block Protect Write Disable "
411 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
412 printf_debug("Chip status register: Auto Address Increment Programming "
413 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
414 spi_prettyprint_status_register_common(status);
415}
416
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000417/* Prettyprint the status register. Works for
418 * SST 25VF016
419 */
420void spi_prettyprint_status_register_sst25vf016(uint8_t status)
421{
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000422 const char *bpt[] = {
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000423 "none",
424 "1F0000H-1FFFFFH",
425 "1E0000H-1FFFFFH",
426 "1C0000H-1FFFFFH",
427 "180000H-1FFFFFH",
428 "100000H-1FFFFFH",
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000429 "all", "all"
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000430 };
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000431 spi_prettyprint_status_register_sst25(status);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000432 printf_debug("Resulting block protection : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000433 bpt[(status & 0x1c) >> 2]);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000434}
435
Peter Stuge5fecee42009-01-26 03:23:50 +0000436void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
437{
438 const char *bpt[] = {
439 "none",
440 "0x70000-0x7ffff",
441 "0x60000-0x7ffff",
442 "0x40000-0x7ffff",
443 "all blocks", "all blocks", "all blocks", "all blocks"
444 };
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000445 spi_prettyprint_status_register_sst25(status);
Peter Stuge5fecee42009-01-26 03:23:50 +0000446 printf_debug("Resulting block protection : %s\n",
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000447 bpt[(status & 0x1c) >> 2]);
Peter Stuge5fecee42009-01-26 03:23:50 +0000448}
449
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000450void spi_prettyprint_status_register(struct flashchip *flash)
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000451{
452 uint8_t status;
453
Peter Stugefa8c5502008-05-10 23:07:52 +0000454 status = spi_read_status_register();
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000455 printf_debug("Chip status register is %02x\n", status);
456 switch (flash->manufacture_id) {
457 case ST_ID:
Carl-Daniel Hailfingerf43e6422008-05-15 22:32:08 +0000458 if (((flash->model_id & 0xff00) == 0x2000) ||
459 ((flash->model_id & 0xff00) == 0x2500))
460 spi_prettyprint_status_register_st_m25p(status);
461 break;
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000462 case MX_ID:
463 if ((flash->model_id & 0xff00) == 0x2000)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000464 spi_prettyprint_status_register_st_m25p(status);
465 break;
466 case SST_ID:
Peter Stuge5fecee42009-01-26 03:23:50 +0000467 switch (flash->model_id) {
468 case 0x2541:
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000469 spi_prettyprint_status_register_sst25vf016(status);
Peter Stuge5fecee42009-01-26 03:23:50 +0000470 break;
471 case 0x8d:
472 case 0x258d:
473 spi_prettyprint_status_register_sst25vf040b(status);
474 break;
Carl-Daniel Hailfinger5100a8a2009-05-13 22:51:27 +0000475 default:
Carl-Daniel Hailfinger1bfd6c92009-05-06 13:59:44 +0000476 spi_prettyprint_status_register_sst25(status);
477 break;
Peter Stuge5fecee42009-01-26 03:23:50 +0000478 }
Carl-Daniel Hailfinger9a3ec822007-12-29 10:15:58 +0000479 break;
480 }
481}
Uwe Hermann394131e2008-10-18 21:14:13 +0000482
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000483int spi_chip_erase_60(struct flashchip *flash)
484{
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000485 int result;
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000486 struct spi_command spicommands[] = {
487 {
488 .writecnt = JEDEC_WREN_OUTSIZE,
489 .writearr = (const unsigned char[]){ JEDEC_WREN },
490 .readcnt = 0,
491 .readarr = NULL,
492 }, {
493 .writecnt = JEDEC_CE_60_OUTSIZE,
494 .writearr = (const unsigned char[]){ JEDEC_CE_60 },
495 .readcnt = 0,
496 .readarr = NULL,
497 }, {
498 .writecnt = 0,
499 .writearr = NULL,
500 .readcnt = 0,
501 .readarr = NULL,
502 }};
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000503
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000504 result = spi_disable_blockprotect();
505 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000506 fprintf(stderr, "spi_disable_blockprotect failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000507 return result;
508 }
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000509
510 result = spi_send_multicommand(spicommands);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000511 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000512 fprintf(stderr, "%s failed during command execution\n",
513 __func__);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000514 return result;
515 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000516 /* Wait until the Write-In-Progress bit is cleared.
517 * This usually takes 1-85 s, so wait in 1 s steps.
518 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000519 /* FIXME: We assume spi_read_status_register will never fail. */
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000520 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000521 programmer_delay(1000 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000522 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
523 fprintf(stderr, "ERASE FAILED!\n");
524 return -1;
525 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000526 return 0;
527}
528
Peter Stugefa8c5502008-05-10 23:07:52 +0000529int spi_chip_erase_c7(struct flashchip *flash)
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000530{
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000531 int result;
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000532 struct spi_command spicommands[] = {
533 {
534 .writecnt = JEDEC_WREN_OUTSIZE,
535 .writearr = (const unsigned char[]){ JEDEC_WREN },
536 .readcnt = 0,
537 .readarr = NULL,
538 }, {
539 .writecnt = JEDEC_CE_C7_OUTSIZE,
540 .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
541 .readcnt = 0,
542 .readarr = NULL,
543 }, {
544 .writecnt = 0,
545 .writearr = NULL,
546 .readcnt = 0,
547 .readarr = NULL,
548 }};
Uwe Hermann394131e2008-10-18 21:14:13 +0000549
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000550 result = spi_disable_blockprotect();
551 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000552 fprintf(stderr, "spi_disable_blockprotect failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000553 return result;
554 }
Carl-Daniel Hailfinger60d71182009-07-11 19:28:36 +0000555
556 result = spi_send_multicommand(spicommands);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000557 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000558 fprintf(stderr, "%s failed during command execution\n", __func__);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000559 return result;
560 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000561 /* Wait until the Write-In-Progress bit is cleared.
562 * This usually takes 1-85 s, so wait in 1 s steps.
563 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000564 /* FIXME: We assume spi_read_status_register will never fail. */
Peter Stugefa8c5502008-05-10 23:07:52 +0000565 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000566 programmer_delay(1000 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000567 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
568 fprintf(stderr, "ERASE FAILED!\n");
569 return -1;
570 }
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000571 return 0;
572}
573
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000574int spi_chip_erase_60_c7(struct flashchip *flash)
575{
576 int result;
577 result = spi_chip_erase_60(flash);
578 if (result) {
579 printf_debug("spi_chip_erase_60 failed, trying c7\n");
580 result = spi_chip_erase_c7(flash);
581 }
582 return result;
583}
584
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000585int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000586{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000587 int result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000588 struct spi_command spicommands[] = {
589 {
590 .writecnt = JEDEC_WREN_OUTSIZE,
591 .writearr = (const unsigned char[]){ JEDEC_WREN },
592 .readcnt = 0,
593 .readarr = NULL,
594 }, {
595 .writecnt = JEDEC_BE_52_OUTSIZE,
596 .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
597 .readcnt = 0,
598 .readarr = NULL,
599 }, {
600 .writecnt = 0,
601 .writearr = NULL,
602 .readcnt = 0,
603 .readarr = NULL,
604 }};
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000605
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000606 result = spi_send_multicommand(spicommands);
607 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000608 fprintf(stderr, "%s failed during command execution\n",
609 __func__);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000610 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000611 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000612 /* Wait until the Write-In-Progress bit is cleared.
613 * This usually takes 100-4000 ms, so wait in 100 ms steps.
614 */
615 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000616 programmer_delay(100 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000617 if (check_erased_range(flash, addr, blocklen)) {
618 fprintf(stderr, "ERASE FAILED!\n");
619 return -1;
620 }
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000621 return 0;
622}
623
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000624/* Block size is usually
625 * 64k for Macronix
626 * 32k for SST
627 * 4-32k non-uniform for EON
628 */
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000629int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000630{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000631 int result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000632 struct spi_command spicommands[] = {
633 {
634 .writecnt = JEDEC_WREN_OUTSIZE,
635 .writearr = (const unsigned char[]){ JEDEC_WREN },
636 .readcnt = 0,
637 .readarr = NULL,
638 }, {
639 .writecnt = JEDEC_BE_D8_OUTSIZE,
640 .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
641 .readcnt = 0,
642 .readarr = NULL,
643 }, {
644 .writecnt = 0,
645 .writearr = NULL,
646 .readcnt = 0,
647 .readarr = NULL,
648 }};
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000649
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000650 result = spi_send_multicommand(spicommands);
651 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000652 fprintf(stderr, "%s failed during command execution\n", __func__);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000653 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000654 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000655 /* Wait until the Write-In-Progress bit is cleared.
656 * This usually takes 100-4000 ms, so wait in 100 ms steps.
657 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000658 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000659 programmer_delay(100 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000660 if (check_erased_range(flash, addr, blocklen)) {
661 fprintf(stderr, "ERASE FAILED!\n");
662 return -1;
663 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000664 return 0;
665}
666
Stefan Reinauer424ed222008-10-29 22:13:20 +0000667int spi_chip_erase_d8(struct flashchip *flash)
668{
669 int i, rc = 0;
670 int total_size = flash->total_size * 1024;
671 int erase_size = 64 * 1024;
672
673 spi_disable_blockprotect();
674
675 printf("Erasing chip: \n");
676
677 for (i = 0; i < total_size / erase_size; i++) {
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000678 rc = spi_block_erase_d8(flash, i * erase_size, erase_size);
Stefan Reinauer424ed222008-10-29 22:13:20 +0000679 if (rc) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000680 fprintf(stderr, "Error erasing block at 0x%x\n", i);
Stefan Reinauer424ed222008-10-29 22:13:20 +0000681 break;
682 }
683 }
684
685 printf("\n");
686
687 return rc;
688}
689
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000690/* Sector size is usually 4k, though Macronix eliteflash has 64k */
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000691int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000692{
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000693 int result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000694 struct spi_command spicommands[] = {
695 {
696 .writecnt = JEDEC_WREN_OUTSIZE,
697 .writearr = (const unsigned char[]){ JEDEC_WREN },
698 .readcnt = 0,
699 .readarr = NULL,
700 }, {
701 .writecnt = JEDEC_SE_OUTSIZE,
702 .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
703 .readcnt = 0,
704 .readarr = NULL,
705 }, {
706 .writecnt = 0,
707 .writearr = NULL,
708 .readcnt = 0,
709 .readarr = NULL,
710 }};
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000711
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000712 result = spi_send_multicommand(spicommands);
713 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000714 fprintf(stderr, "%s failed during command execution\n",
715 __func__);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000716 return result;
Carl-Daniel Hailfinger39fa9b52009-07-11 22:26:52 +0000717 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000718 /* Wait until the Write-In-Progress bit is cleared.
719 * This usually takes 15-800 ms, so wait in 10 ms steps.
720 */
Peter Stugefa8c5502008-05-10 23:07:52 +0000721 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000722 programmer_delay(10 * 1000);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000723 if (check_erased_range(flash, addr, blocklen)) {
724 fprintf(stderr, "ERASE FAILED!\n");
725 return -1;
726 }
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000727 return 0;
728}
729
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000730int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
731{
732 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000733 fprintf(stderr, "%s called with incorrect arguments\n",
734 __func__);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000735 return -1;
736 }
737 return spi_chip_erase_60(flash);
738}
739
740int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
741{
742 if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000743 fprintf(stderr, "%s called with incorrect arguments\n",
744 __func__);
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000745 return -1;
746 }
747 return spi_chip_erase_c7(flash);
748}
749
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000750int spi_write_status_enable(void)
Jason Wanga3f04be2008-11-28 21:36:51 +0000751{
752 const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000753 int result;
Jason Wanga3f04be2008-11-28 21:36:51 +0000754
755 /* Send EWSR (Enable Write Status Register). */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000756 result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000757
758 if (result)
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000759 fprintf(stderr, "%s failed\n", __func__);
Carl-Daniel Hailfinger1e637842009-05-15 00:56:22 +0000760
761 return result;
Jason Wanga3f04be2008-11-28 21:36:51 +0000762}
763
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000764/*
765 * This is according the SST25VF016 datasheet, who knows it is more
766 * generic that this...
767 */
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000768int spi_write_status_register(int status)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000769{
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000770 int result;
771 struct spi_command spicommands[] = {
772 {
773 .writecnt = JEDEC_EWSR_OUTSIZE,
774 .writearr = (const unsigned char[]){ JEDEC_EWSR },
775 .readcnt = 0,
776 .readarr = NULL,
777 }, {
778 .writecnt = JEDEC_WRSR_OUTSIZE,
779 .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
780 .readcnt = 0,
781 .readarr = NULL,
782 }, {
783 .writecnt = 0,
784 .writearr = NULL,
785 .readcnt = 0,
786 .readarr = NULL,
787 }};
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000788
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000789 result = spi_send_multicommand(spicommands);
790 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000791 fprintf(stderr, "%s failed during command execution\n",
792 __func__);
Carl-Daniel Hailfingerfcbdbbc2009-07-22 20:09:28 +0000793 }
794 return result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000795}
796
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000797int spi_byte_program(int addr, uint8_t byte)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000798{
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000799 int result;
800 struct spi_command spicommands[] = {
801 {
802 .writecnt = JEDEC_WREN_OUTSIZE,
803 .writearr = (const unsigned char[]){ JEDEC_WREN },
804 .readcnt = 0,
805 .readarr = NULL,
806 }, {
807 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
808 .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte },
809 .readcnt = 0,
810 .readarr = NULL,
811 }, {
812 .writecnt = 0,
813 .writearr = NULL,
814 .readcnt = 0,
815 .readarr = NULL,
816 }};
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000817
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000818 result = spi_send_multicommand(spicommands);
819 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000820 fprintf(stderr, "%s failed during command execution\n",
821 __func__);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000822 }
823 return result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000824}
825
Paul Foxeb3acef2009-06-12 08:10:33 +0000826int spi_nbyte_program(int address, uint8_t *bytes, int len)
827{
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000828 int result;
829 /* FIXME: Switch to malloc based on len unless that kills speed. */
Paul Foxeb3acef2009-06-12 08:10:33 +0000830 unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
831 JEDEC_BYTE_PROGRAM,
832 (address >> 16) & 0xff,
833 (address >> 8) & 0xff,
834 (address >> 0) & 0xff,
835 };
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000836 struct spi_command spicommands[] = {
837 {
838 .writecnt = JEDEC_WREN_OUTSIZE,
839 .writearr = (const unsigned char[]){ JEDEC_WREN },
840 .readcnt = 0,
841 .readarr = NULL,
842 }, {
843 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
844 .writearr = cmd,
845 .readcnt = 0,
846 .readarr = NULL,
847 }, {
848 .writecnt = 0,
849 .writearr = NULL,
850 .readcnt = 0,
851 .readarr = NULL,
852 }};
Paul Foxeb3acef2009-06-12 08:10:33 +0000853
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000854 if (!len) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000855 fprintf(stderr, "%s called for zero-length write\n", __func__);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000856 return 1;
857 }
Paul Foxeb3acef2009-06-12 08:10:33 +0000858 if (len > 256) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000859 fprintf(stderr, "%s called for too long a write\n", __func__);
Paul Foxeb3acef2009-06-12 08:10:33 +0000860 return 1;
861 }
862
863 memcpy(&cmd[4], bytes, len);
864
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000865 result = spi_send_multicommand(spicommands);
866 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000867 fprintf(stderr, "%s failed during command execution\n",
868 __func__);
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000869 }
870 return result;
Paul Foxeb3acef2009-06-12 08:10:33 +0000871}
872
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000873int spi_disable_blockprotect(void)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000874{
875 uint8_t status;
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000876 int result;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000877
Peter Stugefa8c5502008-05-10 23:07:52 +0000878 status = spi_read_status_register();
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000879 /* If there is block protection in effect, unprotect it first. */
880 if ((status & 0x3c) != 0) {
881 printf_debug("Some block protection in effect, disabling\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000882 result = spi_write_status_register(status & ~0x3c);
883 if (result) {
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000884 fprintf(stderr, "spi_write_status_register failed\n");
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000885 return result;
886 }
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000887 }
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000888 return 0;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000889}
890
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000891int spi_nbyte_read(int address, uint8_t *bytes, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000892{
Uwe Hermann394131e2008-10-18 21:14:13 +0000893 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
894 JEDEC_READ,
Carl-Daniel Hailfingerd3568ad2008-01-22 14:37:31 +0000895 (address >> 16) & 0xff,
896 (address >> 8) & 0xff,
897 (address >> 0) & 0xff,
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000898 };
899
900 /* Send Read */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000901 return spi_send_command(sizeof(cmd), len, cmd, bytes);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000902}
903
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000904/*
905 * Read a complete flash chip.
906 * Each page is read separately in chunks with a maximum size of chunksize.
907 */
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000908int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000909{
910 int rc = 0;
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000911 int i, j, starthere, lenhere;
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000912 int page_size = flash->page_size;
913 int toread;
914
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000915 /* Warning: This loop has a very unusual condition and body.
916 * The loop needs to go through each page with at least one affected
917 * byte. The lowest page number is (start / page_size) since that
918 * division rounds down. The highest page number we want is the page
919 * where the last byte of the range lives. That last byte has the
920 * address (start + len - 1), thus the highest page number is
921 * (start + len - 1) / page_size. Since we want to include that last
922 * page as well, the loop condition uses <=.
923 */
924 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
925 /* Byte position of the first byte in the range in this page. */
926 /* starthere is an offset to the base address of the chip. */
927 starthere = max(start, i * page_size);
928 /* Length of bytes in the range in this page. */
929 lenhere = min(start + len, (i + 1) * page_size) - starthere;
930 for (j = 0; j < lenhere; j += chunksize) {
931 toread = min(chunksize, lenhere - j);
932 rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000933 if (rc)
934 break;
935 }
936 if (rc)
937 break;
938 }
939
940 return rc;
941}
942
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000943int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000944{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000945 if (!spi_programmer[spi_controller].read) {
946 fprintf(stderr, "%s called, but SPI read is unsupported on this"
947 " hardware. Please report a bug.\n", __func__);
948 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000949 }
950
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000951 return spi_programmer[spi_controller].read(flash, buf, start, len);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000952}
953
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000954/*
955 * Program chip using byte programming. (SLOW!)
956 * This is for chips which can only handle one byte writes
957 * and for chips where memory mapped programming is impossible
958 * (e.g. due to size constraints in IT87* for over 512 kB)
959 */
960int spi_chip_write_1(struct flashchip *flash, uint8_t *buf)
961{
962 int total_size = 1024 * flash->total_size;
963 int i;
964
965 spi_disable_blockprotect();
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +0000966 /* Erase first */
967 printf("Erasing flash before programming... ");
968 if (flash->erase(flash)) {
969 fprintf(stderr, "ERASE FAILED!\n");
970 return -1;
971 }
972 printf("done.\n");
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000973 for (i = 0; i < total_size; i++) {
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000974 spi_byte_program(i, buf[i]);
975 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000976 programmer_delay(10);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000977 }
978
979 return 0;
980}
981
982/*
983 * Program chip using page (256 bytes) programming.
984 * Some SPI masters can't do this, they use single byte programming instead.
985 */
Carl-Daniel Hailfinger8d497012009-05-09 02:34:18 +0000986int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000987{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000988 if (!spi_programmer[spi_controller].write_256) {
989 fprintf(stderr, "%s called, but SPI page write is unsupported "
990 " on this hardware. Please report a bug.\n", __func__);
991 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000992 }
993
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000994 return spi_programmer[spi_controller].write_256(flash, buf);
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000995}
Peter Stugefd9217d2009-01-26 03:37:40 +0000996
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000997uint32_t spi_get_valid_read_addr(void)
998{
999 /* Need to return BBAR for ICH chipsets. */
1000 return 0;
1001}
1002
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001003int spi_aai_write(struct flashchip *flash, uint8_t *buf)
1004{
Peter Stugefd9217d2009-01-26 03:37:40 +00001005 uint32_t pos = 2, size = flash->total_size * 1024;
1006 unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +00001007 int result;
1008
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +00001009 switch (spi_controller) {
1010 case SPI_CONTROLLER_WBSIO:
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001011 fprintf(stderr, "%s: impossible with Winbond SPI masters,"
1012 " degrading to byte program\n", __func__);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +00001013 return spi_chip_write_1(flash, buf);
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001014 default:
1015 break;
Peter Stugefd9217d2009-01-26 03:37:40 +00001016 }
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00001017 if (flash->erase(flash)) {
1018 fprintf(stderr, "ERASE FAILED!\n");
1019 return -1;
1020 }
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +00001021 result = spi_write_enable();
1022 if (result)
1023 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +00001024 spi_send_command(6, 0, w, NULL);
Peter Stugefd9217d2009-01-26 03:37:40 +00001025 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001026 programmer_delay(5); /* SST25VF040B Tbp is max 10us */
Peter Stugefd9217d2009-01-26 03:37:40 +00001027 while (pos < size) {
1028 w[1] = buf[pos++];
1029 w[2] = buf[pos++];
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +00001030 spi_send_command(3, 0, w, NULL);
Peter Stugefd9217d2009-01-26 03:37:40 +00001031 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001032 programmer_delay(5); /* SST25VF040B Tbp is max 10us */
Peter Stugefd9217d2009-01-26 03:37:40 +00001033 }
1034 spi_write_disable();
1035 return 0;
1036}