blob: 26da13d8e7b688fd6caea8908322c44de0ced88c [file] [log] [blame]
Sean Nelson14ba6682010-02-26 05:48:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00004 * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
Sean Nelson14ba6682010-02-26 05:48:29 +00005 * Copyright (C) 2008 coresystems GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the common SPI chip driver functions
23 */
24
25#include <string.h>
26#include "flash.h"
27#include "flashchips.h"
28#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000030#include "spi.h"
31
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000032static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000033{
Mathias Krausea60faab2011-01-17 07:50:42 +000034 static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
Sean Nelson14ba6682010-02-26 05:48:29 +000035 int ret;
36 int i;
37
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000038 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000039 if (ret)
40 return ret;
Sean Nelsoned479d22010-03-24 23:14:32 +000041 msg_cspew("RDID returned");
Sean Nelson14ba6682010-02-26 05:48:29 +000042 for (i = 0; i < bytes; i++)
Sean Nelsoned479d22010-03-24 23:14:32 +000043 msg_cspew(" 0x%02x", readarr[i]);
44 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000045 return 0;
46}
47
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000048static int spi_rems(struct flashctx *flash, unsigned char *readarr)
Sean Nelson14ba6682010-02-26 05:48:29 +000049{
50 unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
51 uint32_t readaddr;
52 int ret;
53
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000054 ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd,
55 readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000056 if (ret == SPI_INVALID_ADDRESS) {
57 /* Find the lowest even address allowed for reads. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000058 readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1;
Sean Nelson14ba6682010-02-26 05:48:29 +000059 cmd[1] = (readaddr >> 16) & 0xff,
60 cmd[2] = (readaddr >> 8) & 0xff,
61 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000062 ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE,
63 cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000064 }
65 if (ret)
66 return ret;
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +000067 msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]);
Sean Nelson14ba6682010-02-26 05:48:29 +000068 return 0;
69}
70
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000071static int spi_res(struct flashctx *flash, unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000072{
73 unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
74 uint32_t readaddr;
75 int ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000076 int i;
Sean Nelson14ba6682010-02-26 05:48:29 +000077
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000078 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000079 if (ret == SPI_INVALID_ADDRESS) {
80 /* Find the lowest even address allowed for reads. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000081 readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1;
Sean Nelson14ba6682010-02-26 05:48:29 +000082 cmd[1] = (readaddr >> 16) & 0xff,
83 cmd[2] = (readaddr >> 8) & 0xff,
84 cmd[3] = (readaddr >> 0) & 0xff,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000085 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000086 }
87 if (ret)
88 return ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000089 msg_cspew("RES returned");
90 for (i = 0; i < bytes; i++)
91 msg_cspew(" 0x%02x", readarr[i]);
92 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000093 return 0;
94}
95
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000096int spi_write_enable(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +000097{
Mathias Krausea60faab2011-01-17 07:50:42 +000098 static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
Sean Nelson14ba6682010-02-26 05:48:29 +000099 int result;
100
101 /* Send WREN (Write Enable) */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000102 result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
Sean Nelson14ba6682010-02-26 05:48:29 +0000103
104 if (result)
Sean Nelsoned479d22010-03-24 23:14:32 +0000105 msg_cerr("%s failed\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000106
107 return result;
108}
109
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000110int spi_write_disable(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000111{
Mathias Krausea60faab2011-01-17 07:50:42 +0000112 static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
Sean Nelson14ba6682010-02-26 05:48:29 +0000113
114 /* Send WRDI (Write Disable) */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000115 return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
Sean Nelson14ba6682010-02-26 05:48:29 +0000116}
117
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000118static int probe_spi_rdid_generic(struct flashctx *flash, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +0000119{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000120 const struct flashchip *chip = flash->chip;
Sean Nelson14ba6682010-02-26 05:48:29 +0000121 unsigned char readarr[4];
122 uint32_t id1;
123 uint32_t id2;
124
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000125 if (spi_rdid(flash, readarr, bytes)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000126 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000127 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000128
129 if (!oddparity(readarr[0]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000130 msg_cdbg("RDID byte 0 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000131
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000132 /* Check if this is a continuation vendor ID.
133 * FIXME: Handle continuation device IDs.
134 */
Sean Nelson14ba6682010-02-26 05:48:29 +0000135 if (readarr[0] == 0x7f) {
136 if (!oddparity(readarr[1]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000137 msg_cdbg("RDID byte 1 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000138 id1 = (readarr[0] << 8) | readarr[1];
139 id2 = readarr[2];
140 if (bytes > 3) {
141 id2 <<= 8;
142 id2 |= readarr[3];
143 }
144 } else {
145 id1 = readarr[0];
146 id2 = (readarr[1] << 8) | readarr[2];
147 }
148
Sean Nelsoned479d22010-03-24 23:14:32 +0000149 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000150
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000151 if (id1 == chip->manufacture_id && id2 == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000152 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000153
154 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000155 if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000156 return 1;
157
158 /* Test if there is any vendor ID. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000159 if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff)
Sean Nelson14ba6682010-02-26 05:48:29 +0000160 return 1;
161
162 return 0;
163}
164
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000165int probe_spi_rdid(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000166{
167 return probe_spi_rdid_generic(flash, 3);
168}
169
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000170int probe_spi_rdid4(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000171{
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000172 /* Some SPI controllers do not support commands with writecnt=1 and
173 * readcnt=4.
174 */
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000175 switch (flash->pgm->spi.type) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000176#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000177#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000178 case SPI_CONTROLLER_IT87XX:
Sean Nelson14ba6682010-02-26 05:48:29 +0000179 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000180 msg_cinfo("4 byte RDID not supported on this SPI controller\n");
181 return 0;
182 break;
Sean Nelson14ba6682010-02-26 05:48:29 +0000183#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000184#endif
Sean Nelson14ba6682010-02-26 05:48:29 +0000185 default:
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000186 return probe_spi_rdid_generic(flash, 4);
Sean Nelson14ba6682010-02-26 05:48:29 +0000187 }
188
189 return 0;
190}
191
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000192int probe_spi_rems(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000193{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000194 const struct flashchip *chip = flash->chip;
Sean Nelson14ba6682010-02-26 05:48:29 +0000195 unsigned char readarr[JEDEC_REMS_INSIZE];
196 uint32_t id1, id2;
197
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000198 if (spi_rems(flash, readarr)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000199 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000200 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000201
202 id1 = readarr[0];
203 id2 = readarr[1];
204
Sean Nelsoned479d22010-03-24 23:14:32 +0000205 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000206
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000207 if (id1 == chip->manufacture_id && id2 == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000208 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000209
210 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000211 if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000212 return 1;
213
214 /* Test if there is any vendor ID. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000215 if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff)
Sean Nelson14ba6682010-02-26 05:48:29 +0000216 return 1;
217
218 return 0;
219}
220
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000221int probe_spi_res1(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000222{
Mathias Krausea60faab2011-01-17 07:50:42 +0000223 static const unsigned char allff[] = {0xff, 0xff, 0xff};
224 static const unsigned char all00[] = {0x00, 0x00, 0x00};
Sean Nelson14ba6682010-02-26 05:48:29 +0000225 unsigned char readarr[3];
226 uint32_t id2;
Sean Nelson14ba6682010-02-26 05:48:29 +0000227
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000228 /* We only want one-byte RES if RDID and REMS are unusable. */
229
Sean Nelson14ba6682010-02-26 05:48:29 +0000230 /* Check if RDID is usable and does not return 0xff 0xff 0xff or
231 * 0x00 0x00 0x00. In that case, RES is pointless.
232 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000233 if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) &&
Sean Nelson14ba6682010-02-26 05:48:29 +0000234 memcmp(readarr, all00, 3)) {
235 msg_cdbg("Ignoring RES in favour of RDID.\n");
236 return 0;
237 }
238 /* Check if REMS is usable and does not return 0xff 0xff or
239 * 0x00 0x00. In that case, RES is pointless.
240 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000241 if (!spi_rems(flash, readarr) &&
242 memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
Sean Nelson14ba6682010-02-26 05:48:29 +0000243 memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
244 msg_cdbg("Ignoring RES in favour of REMS.\n");
245 return 0;
246 }
247
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000248 if (spi_res(flash, readarr, 1)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000249 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000250 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000251
Sean Nelson14ba6682010-02-26 05:48:29 +0000252 id2 = readarr[0];
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000253
Sean Nelsoned479d22010-03-24 23:14:32 +0000254 msg_cdbg("%s: id 0x%x\n", __func__, id2);
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000255
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000256 if (id2 != flash->chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000257 return 0;
258
Sean Nelson14ba6682010-02-26 05:48:29 +0000259 return 1;
260}
261
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000262int probe_spi_res2(struct flashctx *flash)
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000263{
264 unsigned char readarr[2];
265 uint32_t id1, id2;
266
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000267 if (spi_res(flash, readarr, 2)) {
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000268 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000269 }
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000270
271 id1 = readarr[0];
272 id2 = readarr[1];
273
274 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
275
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000276 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000277 return 0;
278
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000279 return 1;
280}
281
Stefan Tauner3f5e35d2013-04-19 01:58:33 +0000282int probe_spi_res3(struct flashctx *flash)
283{
284 unsigned char readarr[3];
285 uint32_t id1, id2;
286
287 if (spi_res(flash, readarr, 3)) {
288 return 0;
289 }
290
291 id1 = (readarr[0] << 8) | readarr[1];
292 id2 = readarr[2];
293
294 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
295
296 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
297 return 0;
298
299 return 1;
300}
301
Stefan Tauner57794ac2012-12-29 15:04:20 +0000302/* Only used for some Atmel chips. */
303int probe_spi_at25f(struct flashctx *flash)
304{
305 static const unsigned char cmd[AT25F_RDID_OUTSIZE] = { AT25F_RDID };
306 unsigned char readarr[AT25F_RDID_INSIZE];
307 uint32_t id1;
308 uint32_t id2;
309
310 if (spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr))
311 return 0;
312
313 id1 = readarr[0];
314 id2 = readarr[1];
315
316 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
317
318 if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id)
319 return 1;
320
321 return 0;
322}
323
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000324int spi_chip_erase_60(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000325{
326 int result;
327 struct spi_command cmds[] = {
328 {
329 .writecnt = JEDEC_WREN_OUTSIZE,
330 .writearr = (const unsigned char[]){ JEDEC_WREN },
331 .readcnt = 0,
332 .readarr = NULL,
333 }, {
334 .writecnt = JEDEC_CE_60_OUTSIZE,
335 .writearr = (const unsigned char[]){ JEDEC_CE_60 },
336 .readcnt = 0,
337 .readarr = NULL,
338 }, {
339 .writecnt = 0,
340 .writearr = NULL,
341 .readcnt = 0,
342 .readarr = NULL,
343 }};
344
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000345 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000346 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000347 msg_cerr("%s failed during command execution\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000348 __func__);
349 return result;
350 }
351 /* Wait until the Write-In-Progress bit is cleared.
352 * This usually takes 1-85 s, so wait in 1 s steps.
353 */
354 /* FIXME: We assume spi_read_status_register will never fail. */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000355 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000356 programmer_delay(1000 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000357 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000358 return 0;
359}
360
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000361int spi_chip_erase_62(struct flashctx *flash)
362{
363 int result;
364 struct spi_command cmds[] = {
365 {
366 .writecnt = JEDEC_WREN_OUTSIZE,
367 .writearr = (const unsigned char[]){ JEDEC_WREN },
368 .readcnt = 0,
369 .readarr = NULL,
370 }, {
371 .writecnt = JEDEC_CE_62_OUTSIZE,
372 .writearr = (const unsigned char[]){ JEDEC_CE_62 },
373 .readcnt = 0,
374 .readarr = NULL,
375 }, {
376 .writecnt = 0,
377 .writearr = NULL,
378 .readcnt = 0,
379 .readarr = NULL,
380 }};
381
382 result = spi_send_multicommand(flash, cmds);
383 if (result) {
384 msg_cerr("%s failed during command execution\n",
385 __func__);
386 return result;
387 }
388 /* Wait until the Write-In-Progress bit is cleared.
389 * This usually takes 2-5 s, so wait in 100 ms steps.
390 */
391 /* FIXME: We assume spi_read_status_register will never fail. */
392 while (spi_read_status_register(flash) & SPI_SR_WIP)
393 programmer_delay(100 * 1000);
394 /* FIXME: Check the status register for errors. */
395 return 0;
396}
397
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000398int spi_chip_erase_c7(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000399{
400 int result;
401 struct spi_command cmds[] = {
402 {
403 .writecnt = JEDEC_WREN_OUTSIZE,
404 .writearr = (const unsigned char[]){ JEDEC_WREN },
405 .readcnt = 0,
406 .readarr = NULL,
407 }, {
408 .writecnt = JEDEC_CE_C7_OUTSIZE,
409 .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
410 .readcnt = 0,
411 .readarr = NULL,
412 }, {
413 .writecnt = 0,
414 .writearr = NULL,
415 .readcnt = 0,
416 .readarr = NULL,
417 }};
418
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000419 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000420 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000421 msg_cerr("%s failed during command execution\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000422 return result;
423 }
424 /* Wait until the Write-In-Progress bit is cleared.
425 * This usually takes 1-85 s, so wait in 1 s steps.
426 */
427 /* FIXME: We assume spi_read_status_register will never fail. */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000428 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000429 programmer_delay(1000 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000430 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000431 return 0;
432}
433
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000434int spi_block_erase_52(struct flashctx *flash, unsigned int addr,
435 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000436{
437 int result;
438 struct spi_command cmds[] = {
439 {
440 .writecnt = JEDEC_WREN_OUTSIZE,
441 .writearr = (const unsigned char[]){ JEDEC_WREN },
442 .readcnt = 0,
443 .readarr = NULL,
444 }, {
445 .writecnt = JEDEC_BE_52_OUTSIZE,
446 .writearr = (const unsigned char[]){
447 JEDEC_BE_52,
448 (addr >> 16) & 0xff,
449 (addr >> 8) & 0xff,
450 (addr & 0xff)
451 },
452 .readcnt = 0,
453 .readarr = NULL,
454 }, {
455 .writecnt = 0,
456 .writearr = NULL,
457 .readcnt = 0,
458 .readarr = NULL,
459 }};
460
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000461 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000462 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000463 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000464 __func__, addr);
465 return result;
466 }
467 /* Wait until the Write-In-Progress bit is cleared.
468 * This usually takes 100-4000 ms, so wait in 100 ms steps.
469 */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000470 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000471 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000472 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000473 return 0;
474}
475
476/* Block size is usually
477 * 64k for Macronix
478 * 32k for SST
479 * 4-32k non-uniform for EON
480 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000481int spi_block_erase_d8(struct flashctx *flash, unsigned int addr,
482 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000483{
484 int result;
485 struct spi_command cmds[] = {
486 {
487 .writecnt = JEDEC_WREN_OUTSIZE,
488 .writearr = (const unsigned char[]){ JEDEC_WREN },
489 .readcnt = 0,
490 .readarr = NULL,
491 }, {
492 .writecnt = JEDEC_BE_D8_OUTSIZE,
493 .writearr = (const unsigned char[]){
494 JEDEC_BE_D8,
495 (addr >> 16) & 0xff,
496 (addr >> 8) & 0xff,
497 (addr & 0xff)
498 },
499 .readcnt = 0,
500 .readarr = NULL,
501 }, {
502 .writecnt = 0,
503 .writearr = NULL,
504 .readcnt = 0,
505 .readarr = NULL,
506 }};
507
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000508 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000509 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000510 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000511 __func__, addr);
512 return result;
513 }
514 /* Wait until the Write-In-Progress bit is cleared.
515 * This usually takes 100-4000 ms, so wait in 100 ms steps.
516 */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000517 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000518 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000519 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000520 return 0;
521}
522
523/* Block size is usually
524 * 4k for PMC
525 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000526int spi_block_erase_d7(struct flashctx *flash, unsigned int addr,
527 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000528{
529 int result;
530 struct spi_command cmds[] = {
531 {
532 .writecnt = JEDEC_WREN_OUTSIZE,
533 .writearr = (const unsigned char[]){ JEDEC_WREN },
534 .readcnt = 0,
535 .readarr = NULL,
536 }, {
537 .writecnt = JEDEC_BE_D7_OUTSIZE,
538 .writearr = (const unsigned char[]){
539 JEDEC_BE_D7,
540 (addr >> 16) & 0xff,
541 (addr >> 8) & 0xff,
542 (addr & 0xff)
543 },
544 .readcnt = 0,
545 .readarr = NULL,
546 }, {
547 .writecnt = 0,
548 .writearr = NULL,
549 .readcnt = 0,
550 .readarr = NULL,
551 }};
552
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000553 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000554 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000555 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000556 __func__, addr);
557 return result;
558 }
559 /* Wait until the Write-In-Progress bit is cleared.
560 * This usually takes 100-4000 ms, so wait in 100 ms steps.
561 */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000562 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000563 programmer_delay(100 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000564 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000565 return 0;
566}
567
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000568/* Page erase (usually 256B blocks) */
569int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
570{
571 int result;
572 struct spi_command cmds[] = {
573 {
574 .writecnt = JEDEC_WREN_OUTSIZE,
575 .writearr = (const unsigned char[]){ JEDEC_WREN },
576 .readcnt = 0,
577 .readarr = NULL,
578 }, {
579 .writecnt = JEDEC_PE_OUTSIZE,
580 .writearr = (const unsigned char[]){
581 JEDEC_PE,
582 (addr >> 16) & 0xff,
583 (addr >> 8) & 0xff,
584 (addr & 0xff)
585 },
586 .readcnt = 0,
587 .readarr = NULL,
588 }, {
589 .writecnt = 0,
590 .writearr = NULL,
591 .readcnt = 0,
592 .readarr = NULL,
593 } };
594
595 result = spi_send_multicommand(flash, cmds);
596 if (result) {
597 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
598 return result;
599 }
600
601 /* Wait until the Write-In-Progress bit is cleared.
602 * This takes up to 20 ms usually (on worn out devices up to the 0.5s range), so wait in 1 ms steps. */
603 while (spi_read_status_register(flash) & SPI_SR_WIP)
604 programmer_delay(1 * 1000);
605 /* FIXME: Check the status register for errors. */
606 return 0;
607}
608
Sean Nelson14ba6682010-02-26 05:48:29 +0000609/* Sector size is usually 4k, though Macronix eliteflash has 64k */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000610int spi_block_erase_20(struct flashctx *flash, unsigned int addr,
611 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000612{
613 int result;
614 struct spi_command cmds[] = {
615 {
616 .writecnt = JEDEC_WREN_OUTSIZE,
617 .writearr = (const unsigned char[]){ JEDEC_WREN },
618 .readcnt = 0,
619 .readarr = NULL,
620 }, {
621 .writecnt = JEDEC_SE_OUTSIZE,
622 .writearr = (const unsigned char[]){
623 JEDEC_SE,
624 (addr >> 16) & 0xff,
625 (addr >> 8) & 0xff,
626 (addr & 0xff)
627 },
628 .readcnt = 0,
629 .readarr = NULL,
630 }, {
631 .writecnt = 0,
632 .writearr = NULL,
633 .readcnt = 0,
634 .readarr = NULL,
635 }};
636
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000637 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000638 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000639 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000640 __func__, addr);
641 return result;
642 }
643 /* Wait until the Write-In-Progress bit is cleared.
644 * This usually takes 15-800 ms, so wait in 10 ms steps.
645 */
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000646 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +0000647 programmer_delay(10 * 1000);
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000648 /* FIXME: Check the status register for errors. */
Sean Nelson14ba6682010-02-26 05:48:29 +0000649 return 0;
650}
651
Stefan Tauner94b39b42012-10-27 00:06:02 +0000652int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
653{
654 int result;
655 struct spi_command cmds[] = {
656 {
657/* .writecnt = JEDEC_WREN_OUTSIZE,
658 .writearr = (const unsigned char[]){ JEDEC_WREN },
659 .readcnt = 0,
660 .readarr = NULL,
661 }, { */
662 .writecnt = JEDEC_BE_50_OUTSIZE,
663 .writearr = (const unsigned char[]){
664 JEDEC_BE_50,
665 (addr >> 16) & 0xff,
666 (addr >> 8) & 0xff,
667 (addr & 0xff)
668 },
669 .readcnt = 0,
670 .readarr = NULL,
671 }, {
672 .writecnt = 0,
673 .writearr = NULL,
674 .readcnt = 0,
675 .readarr = NULL,
676 }};
677
678 result = spi_send_multicommand(flash, cmds);
679 if (result) {
680 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
681 return result;
682 }
683 /* Wait until the Write-In-Progress bit is cleared.
684 * This usually takes 10 ms, so wait in 1 ms steps.
685 */
686 while (spi_read_status_register(flash) & SPI_SR_WIP)
687 programmer_delay(1 * 1000);
688 /* FIXME: Check the status register for errors. */
689 return 0;
690}
691
692int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
693{
694 int result;
695 struct spi_command cmds[] = {
696 {
697/* .writecnt = JEDEC_WREN_OUTSIZE,
698 .writearr = (const unsigned char[]){ JEDEC_WREN },
699 .readcnt = 0,
700 .readarr = NULL,
701 }, { */
702 .writecnt = JEDEC_BE_81_OUTSIZE,
703 .writearr = (const unsigned char[]){
704 JEDEC_BE_81,
705 (addr >> 16) & 0xff,
706 (addr >> 8) & 0xff,
707 (addr & 0xff)
708 },
709 .readcnt = 0,
710 .readarr = NULL,
711 }, {
712 .writecnt = 0,
713 .writearr = NULL,
714 .readcnt = 0,
715 .readarr = NULL,
716 }};
717
718 result = spi_send_multicommand(flash, cmds);
719 if (result) {
720 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
721 return result;
722 }
723 /* Wait until the Write-In-Progress bit is cleared.
724 * This usually takes 8 ms, so wait in 1 ms steps.
725 */
726 while (spi_read_status_register(flash) & SPI_SR_WIP)
727 programmer_delay(1 * 1000);
728 /* FIXME: Check the status register for errors. */
729 return 0;
730}
731
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000732int spi_block_erase_60(struct flashctx *flash, unsigned int addr,
733 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000734{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000735 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000736 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000737 __func__);
738 return -1;
739 }
740 return spi_chip_erase_60(flash);
741}
742
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000743int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
744{
745 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
746 msg_cerr("%s called with incorrect arguments\n",
747 __func__);
748 return -1;
749 }
750 return spi_chip_erase_62(flash);
751}
752
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000753int spi_block_erase_c7(struct flashctx *flash, unsigned int addr,
754 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000755{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000756 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000757 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000758 __func__);
759 return -1;
760 }
761 return spi_chip_erase_c7(flash);
762}
763
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000764erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode)
765{
766 switch(opcode){
767 case 0xff:
768 case 0x00:
769 /* Not specified, assuming "not supported". */
770 return NULL;
771 case 0x20:
772 return &spi_block_erase_20;
Stefan Tauner730e7e72013-05-01 14:04:19 +0000773 case 0x50:
774 return &spi_block_erase_50;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000775 case 0x52:
776 return &spi_block_erase_52;
777 case 0x60:
778 return &spi_block_erase_60;
Stefan Tauner730e7e72013-05-01 14:04:19 +0000779 case 0x62:
780 return &spi_block_erase_62;
781 case 0x81:
782 return &spi_block_erase_81;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000783 case 0xc7:
784 return &spi_block_erase_c7;
785 case 0xd7:
786 return &spi_block_erase_d7;
787 case 0xd8:
788 return &spi_block_erase_d8;
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000789 case 0xdb:
790 return &spi_block_erase_db;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000791 default:
792 msg_cinfo("%s: unknown erase opcode (0x%02x). Please report "
793 "this at flashrom@flashrom.org\n", __func__, opcode);
794 return NULL;
795 }
796}
797
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000798int spi_byte_program(struct flashctx *flash, unsigned int addr,
799 uint8_t databyte)
Sean Nelson14ba6682010-02-26 05:48:29 +0000800{
801 int result;
802 struct spi_command cmds[] = {
803 {
804 .writecnt = JEDEC_WREN_OUTSIZE,
805 .writearr = (const unsigned char[]){ JEDEC_WREN },
806 .readcnt = 0,
807 .readarr = NULL,
808 }, {
809 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
810 .writearr = (const unsigned char[]){
811 JEDEC_BYTE_PROGRAM,
812 (addr >> 16) & 0xff,
813 (addr >> 8) & 0xff,
814 (addr & 0xff),
815 databyte
816 },
817 .readcnt = 0,
818 .readarr = NULL,
819 }, {
820 .writecnt = 0,
821 .writearr = NULL,
822 .readcnt = 0,
823 .readarr = NULL,
824 }};
825
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000826 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000827 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000828 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000829 __func__, addr);
830 }
831 return result;
832}
833
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000834int spi_nbyte_program(struct flashctx *flash, unsigned int addr, uint8_t *bytes,
835 unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000836{
837 int result;
838 /* FIXME: Switch to malloc based on len unless that kills speed. */
839 unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
840 JEDEC_BYTE_PROGRAM,
841 (addr >> 16) & 0xff,
842 (addr >> 8) & 0xff,
843 (addr >> 0) & 0xff,
844 };
845 struct spi_command cmds[] = {
846 {
847 .writecnt = JEDEC_WREN_OUTSIZE,
848 .writearr = (const unsigned char[]){ JEDEC_WREN },
849 .readcnt = 0,
850 .readarr = NULL,
851 }, {
852 .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
853 .writearr = cmd,
854 .readcnt = 0,
855 .readarr = NULL,
856 }, {
857 .writecnt = 0,
858 .writearr = NULL,
859 .readcnt = 0,
860 .readarr = NULL,
861 }};
862
863 if (!len) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000864 msg_cerr("%s called for zero-length write\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000865 return 1;
866 }
867 if (len > 256) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000868 msg_cerr("%s called for too long a write\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000869 return 1;
870 }
871
872 memcpy(&cmd[4], bytes, len);
873
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000874 result = spi_send_multicommand(flash, cmds);
Sean Nelson14ba6682010-02-26 05:48:29 +0000875 if (result) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000876 msg_cerr("%s failed during command execution at address 0x%x\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000877 __func__, addr);
878 }
879 return result;
880}
881
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000882int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes,
883 unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000884{
885 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
886 JEDEC_READ,
887 (address >> 16) & 0xff,
888 (address >> 8) & 0xff,
889 (address >> 0) & 0xff,
890 };
891
892 /* Send Read */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000893 return spi_send_command(flash, sizeof(cmd), len, cmd, bytes);
Sean Nelson14ba6682010-02-26 05:48:29 +0000894}
895
896/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000897 * Read a part of the flash chip.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000898 * FIXME: Use the chunk code from Michael Karcher instead.
Sean Nelson14ba6682010-02-26 05:48:29 +0000899 * Each page is read separately in chunks with a maximum size of chunksize.
900 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000901int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,
902 unsigned int len, unsigned int chunksize)
Sean Nelson14ba6682010-02-26 05:48:29 +0000903{
904 int rc = 0;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000905 unsigned int i, j, starthere, lenhere, toread;
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000906 unsigned int page_size = flash->chip->page_size;
Sean Nelson14ba6682010-02-26 05:48:29 +0000907
908 /* Warning: This loop has a very unusual condition and body.
909 * The loop needs to go through each page with at least one affected
910 * byte. The lowest page number is (start / page_size) since that
911 * division rounds down. The highest page number we want is the page
912 * where the last byte of the range lives. That last byte has the
913 * address (start + len - 1), thus the highest page number is
914 * (start + len - 1) / page_size. Since we want to include that last
915 * page as well, the loop condition uses <=.
916 */
917 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
918 /* Byte position of the first byte in the range in this page. */
919 /* starthere is an offset to the base address of the chip. */
920 starthere = max(start, i * page_size);
921 /* Length of bytes in the range in this page. */
922 lenhere = min(start + len, (i + 1) * page_size) - starthere;
923 for (j = 0; j < lenhere; j += chunksize) {
924 toread = min(chunksize, lenhere - j);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000925 rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread);
Sean Nelson14ba6682010-02-26 05:48:29 +0000926 if (rc)
927 break;
928 }
929 if (rc)
930 break;
931 }
932
933 return rc;
934}
935
936/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000937 * Write a part of the flash chip.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000938 * FIXME: Use the chunk code from Michael Karcher instead.
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000939 * Each page is written separately in chunks with a maximum size of chunksize.
940 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000941int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,
942 unsigned int len, unsigned int chunksize)
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000943{
944 int rc = 0;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000945 unsigned int i, j, starthere, lenhere, towrite;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000946 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000947 * in struct flashctx to do this properly. All chips using
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000948 * spi_chip_write_256 have page_size set to max_writechunk_size, so
949 * we're OK for now.
950 */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000951 unsigned int page_size = flash->chip->page_size;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000952
953 /* Warning: This loop has a very unusual condition and body.
954 * The loop needs to go through each page with at least one affected
955 * byte. The lowest page number is (start / page_size) since that
956 * division rounds down. The highest page number we want is the page
957 * where the last byte of the range lives. That last byte has the
958 * address (start + len - 1), thus the highest page number is
959 * (start + len - 1) / page_size. Since we want to include that last
960 * page as well, the loop condition uses <=.
961 */
962 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
963 /* Byte position of the first byte in the range in this page. */
964 /* starthere is an offset to the base address of the chip. */
965 starthere = max(start, i * page_size);
966 /* Length of bytes in the range in this page. */
967 lenhere = min(start + len, (i + 1) * page_size) - starthere;
968 for (j = 0; j < lenhere; j += chunksize) {
969 towrite = min(chunksize, lenhere - j);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000970 rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000971 if (rc)
972 break;
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000973 while (spi_read_status_register(flash) & SPI_SR_WIP)
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000974 programmer_delay(10);
975 }
976 if (rc)
977 break;
978 }
979
980 return rc;
981}
982
983/*
Sean Nelson14ba6682010-02-26 05:48:29 +0000984 * Program chip using byte programming. (SLOW!)
985 * This is for chips which can only handle one byte writes
986 * and for chips where memory mapped programming is impossible
987 * (e.g. due to size constraints in IT87* for over 512 kB)
988 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000989/* real chunksize is 1, logical chunksize is 1 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000990int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start,
991 unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000992{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000993 unsigned int i;
994 int result = 0;
Sean Nelson14ba6682010-02-26 05:48:29 +0000995
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000996 for (i = start; i < start + len; i++) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000997 result = spi_byte_program(flash, i, buf[i - start]);
Sean Nelson14ba6682010-02-26 05:48:29 +0000998 if (result)
999 return 1;
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001000 while (spi_read_status_register(flash) & SPI_SR_WIP)
Sean Nelson14ba6682010-02-26 05:48:29 +00001001 programmer_delay(10);
1002 }
1003
1004 return 0;
1005}
1006
Nico Huber7bca1262012-06-15 22:28:12 +00001007int default_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len)
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001008{
1009 uint32_t pos = start;
Sean Nelson14ba6682010-02-26 05:48:29 +00001010 int result;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001011 unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = {
1012 JEDEC_AAI_WORD_PROGRAM,
1013 };
1014 struct spi_command cmds[] = {
1015 {
1016 .writecnt = JEDEC_WREN_OUTSIZE,
1017 .writearr = (const unsigned char[]){ JEDEC_WREN },
1018 .readcnt = 0,
1019 .readarr = NULL,
1020 }, {
1021 .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE,
1022 .writearr = (const unsigned char[]){
1023 JEDEC_AAI_WORD_PROGRAM,
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001024 (start >> 16) & 0xff,
1025 (start >> 8) & 0xff,
1026 (start & 0xff),
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001027 buf[0],
1028 buf[1]
1029 },
1030 .readcnt = 0,
1031 .readarr = NULL,
1032 }, {
1033 .writecnt = 0,
1034 .writearr = NULL,
1035 .readcnt = 0,
1036 .readarr = NULL,
1037 }};
Sean Nelson14ba6682010-02-26 05:48:29 +00001038
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001039 switch (flash->pgm->spi.type) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +00001040#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001041#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001042 case SPI_CONTROLLER_IT87XX:
Sean Nelson14ba6682010-02-26 05:48:29 +00001043 case SPI_CONTROLLER_WBSIO:
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001044 msg_perr("%s: impossible with this SPI controller,"
Sean Nelson14ba6682010-02-26 05:48:29 +00001045 " degrading to byte program\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001046 return spi_chip_write_1(flash, buf, start, len);
Sean Nelson14ba6682010-02-26 05:48:29 +00001047#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001048#endif
Sean Nelson14ba6682010-02-26 05:48:29 +00001049 default:
1050 break;
1051 }
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001052
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001053 /* The even start address and even length requirements can be either
1054 * honored outside this function, or we can call spi_byte_program
1055 * for the first and/or last byte and use AAI for the rest.
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001056 * FIXME: Move this to generic code.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001057 */
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001058 /* The data sheet requires a start address with the low bit cleared. */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001059 if (start % 2) {
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001060 msg_cerr("%s: start address not even! Please report a bug at "
1061 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001062 if (spi_chip_write_1(flash, buf, start, start % 2))
1063 return SPI_GENERIC_ERROR;
1064 pos += start % 2;
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001065 cmds[1].writearr = (const unsigned char[]){
1066 JEDEC_AAI_WORD_PROGRAM,
1067 (pos >> 16) & 0xff,
1068 (pos >> 8) & 0xff,
1069 (pos & 0xff),
1070 buf[pos - start],
1071 buf[pos - start + 1]
1072 };
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001073 /* Do not return an error for now. */
1074 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001075 }
1076 /* The data sheet requires total AAI write length to be even. */
1077 if (len % 2) {
1078 msg_cerr("%s: total write length not even! Please report a "
1079 "bug at flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001080 /* Do not return an error for now. */
1081 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001082 }
1083
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001084
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001085 result = spi_send_multicommand(flash, cmds);
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001086 if (result) {
1087 msg_cerr("%s failed during start command execution\n",
1088 __func__);
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +00001089 /* FIXME: Should we send WRDI here as well to make sure the chip
1090 * is not in AAI mode?
1091 */
Sean Nelson14ba6682010-02-26 05:48:29 +00001092 return result;
Sean Nelson14ba6682010-02-26 05:48:29 +00001093 }
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001094 while (spi_read_status_register(flash) & SPI_SR_WIP)
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001095 programmer_delay(10);
1096
1097 /* We already wrote 2 bytes in the multicommand step. */
1098 pos += 2;
1099
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001100 /* Are there at least two more bytes to write? */
1101 while (pos < start + len - 1) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001102 cmd[1] = buf[pos++ - start];
1103 cmd[2] = buf[pos++ - start];
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001104 spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0,
1105 cmd, NULL);
Stefan Tauner5e695ab2012-05-06 17:03:40 +00001106 while (spi_read_status_register(flash) & SPI_SR_WIP)
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +00001107 programmer_delay(10);
1108 }
1109
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001110 /* Use WRDI to exit AAI mode. This needs to be done before issuing any
1111 * other non-AAI command.
1112 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001113 spi_write_disable(flash);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001114
1115 /* Write remaining byte (if any). */
1116 if (pos < start + len) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +00001117 if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2))
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +00001118 return SPI_GENERIC_ERROR;
1119 pos += pos % 2;
1120 }
1121
Sean Nelson14ba6682010-02-26 05:48:29 +00001122 return 0;
1123}