blob: e1147f1102be411822232438748227ca71f73727 [file] [log] [blame]
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef __PROGRAMMER_H__
25#define __PROGRAMMER_H__ 1
26
27enum programmer {
28#if CONFIG_INTERNAL == 1
29 PROGRAMMER_INTERNAL,
30#endif
31#if CONFIG_DUMMY == 1
32 PROGRAMMER_DUMMY,
33#endif
34#if CONFIG_NIC3COM == 1
35 PROGRAMMER_NIC3COM,
36#endif
37#if CONFIG_NICREALTEK == 1
38 PROGRAMMER_NICREALTEK,
Idwer Vollering004f4b72010-09-03 18:21:21 +000039#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000040#if CONFIG_NICNATSEMI == 1
41 PROGRAMMER_NICNATSEMI,
Idwer Vollering004f4b72010-09-03 18:21:21 +000042#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000043#if CONFIG_GFXNVIDIA == 1
44 PROGRAMMER_GFXNVIDIA,
45#endif
46#if CONFIG_DRKAISER == 1
47 PROGRAMMER_DRKAISER,
48#endif
49#if CONFIG_SATASII == 1
50 PROGRAMMER_SATASII,
51#endif
52#if CONFIG_ATAHPT == 1
53 PROGRAMMER_ATAHPT,
54#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000055#if CONFIG_FT2232_SPI == 1
56 PROGRAMMER_FT2232_SPI,
57#endif
58#if CONFIG_SERPROG == 1
59 PROGRAMMER_SERPROG,
60#endif
61#if CONFIG_BUSPIRATE_SPI == 1
62 PROGRAMMER_BUSPIRATE_SPI,
63#endif
64#if CONFIG_DEDIPROG == 1
65 PROGRAMMER_DEDIPROG,
66#endif
67#if CONFIG_RAYER_SPI == 1
68 PROGRAMMER_RAYER_SPI,
69#endif
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000070#if CONFIG_NICINTEL == 1
71 PROGRAMMER_NICINTEL,
72#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +000073#if CONFIG_NICINTEL_SPI == 1
74 PROGRAMMER_NICINTEL_SPI,
75#endif
Mark Marshall90021f22010-12-03 14:48:11 +000076#if CONFIG_OGP_SPI == 1
77 PROGRAMMER_OGP_SPI,
78#endif
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000079#if CONFIG_SATAMV == 1
80 PROGRAMMER_SATAMV,
81#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000082 PROGRAMMER_INVALID /* This must always be the last entry. */
83};
84
85extern enum programmer programmer;
86
87struct programmer_entry {
88 const char *vendor;
89 const char *name;
90
91 int (*init) (void);
92 int (*shutdown) (void);
93
94 void * (*map_flash_region) (const char *descr, unsigned long phys_addr,
95 size_t len);
96 void (*unmap_flash_region) (void *virt_addr, size_t len);
97
98 void (*chip_writeb) (uint8_t val, chipaddr addr);
99 void (*chip_writew) (uint16_t val, chipaddr addr);
100 void (*chip_writel) (uint32_t val, chipaddr addr);
101 void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
102 uint8_t (*chip_readb) (const chipaddr addr);
103 uint16_t (*chip_readw) (const chipaddr addr);
104 uint32_t (*chip_readl) (const chipaddr addr);
105 void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
106 void (*delay) (int usecs);
107};
108
109extern const struct programmer_entry programmer_table[];
110
111int programmer_init(char *param);
112int programmer_shutdown(void);
113
114enum bitbang_spi_master_type {
115 BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */
116#if CONFIG_RAYER_SPI == 1
117 BITBANG_SPI_MASTER_RAYER,
118#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +0000119#if CONFIG_NICINTEL_SPI == 1
120 BITBANG_SPI_MASTER_NICINTEL,
121#endif
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000122#if CONFIG_INTERNAL == 1
123#if defined(__i386__) || defined(__x86_64__)
124 BITBANG_SPI_MASTER_MCP,
125#endif
126#endif
Mark Marshall90021f22010-12-03 14:48:11 +0000127#if CONFIG_OGP_SPI == 1
128 BITBANG_SPI_MASTER_OGP,
129#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000130};
131
132struct bitbang_spi_master {
133 enum bitbang_spi_master_type type;
134
135 /* Note that CS# is active low, so val=0 means the chip is active. */
136 void (*set_cs) (int val);
137 void (*set_sck) (int val);
138 void (*set_mosi) (int val);
139 int (*get_miso) (void);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000140 void (*request_bus) (void);
141 void (*release_bus) (void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000142};
143
144#if CONFIG_INTERNAL == 1
145struct penable {
146 uint16_t vendor_id;
147 uint16_t device_id;
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000148 int status; /* OK=0 and NT=1 are defines only. Beware! */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000149 const char *vendor_name;
150 const char *device_name;
151 int (*doit) (struct pci_dev *dev, const char *name);
152};
153
154extern const struct penable chipset_enables[];
155
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000156enum board_match_phase {
157 P1,
158 P2,
159 P3
160};
161
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000162struct board_pciid_enable {
163 /* Any device, but make it sensible, like the ISA bridge. */
164 uint16_t first_vendor;
165 uint16_t first_device;
166 uint16_t first_card_vendor;
167 uint16_t first_card_device;
168
169 /* Any device, but make it sensible, like
170 * the host bridge. May be NULL.
171 */
172 uint16_t second_vendor;
173 uint16_t second_device;
174 uint16_t second_card_vendor;
175 uint16_t second_card_device;
176
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000177 /* Pattern to match DMI entries. May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000178 const char *dmi_pattern;
179
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000180 /* The vendor / part name from the coreboot table. May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000181 const char *lb_vendor;
182 const char *lb_part;
183
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000184 enum board_match_phase phase;
185
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000186 const char *vendor_name;
187 const char *board_name;
188
189 int max_rom_decode_parallel;
190 int status;
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000191 int (*enable) (void); /* May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000192};
193
194extern const struct board_pciid_enable board_pciid_enables[];
195
196struct board_info {
197 const char *vendor;
198 const char *name;
199 const int working;
200#ifdef CONFIG_PRINT_WIKI
201 const char *url;
202 const char *note;
203#endif
204};
205
206extern const struct board_info boards_known[];
207extern const struct board_info laptops_known[];
208#endif
209
210/* udelay.c */
211void myusec_delay(int usecs);
212void myusec_calibrate_delay(void);
213void internal_delay(int usecs);
214
215#if NEED_PCI == 1
216/* pcidev.c */
217extern uint32_t io_base_addr;
218extern struct pci_access *pacc;
219extern struct pci_dev *pcidev_dev;
220struct pcidev_status {
221 uint16_t vendor_id;
222 uint16_t device_id;
223 int status;
224 const char *vendor_name;
225 const char *device_name;
226};
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +0000227uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs);
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +0000228uintptr_t pcidev_init(int bar, const struct pcidev_status *devs);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000229/* rpci_write_* are reversible writes. The original PCI config space register
230 * contents will be restored on shutdown.
231 */
Idwer Vollering1a6162e2010-12-26 23:55:19 +0000232int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
233int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
234int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000235#endif
236
237/* print.c */
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000238#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000239void print_supported_pcidevs(const struct pcidev_status *devs);
240#endif
241
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000242#if CONFIG_INTERNAL
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000243/* board_enable.c */
244void w836xx_ext_enter(uint16_t port);
245void w836xx_ext_leave(uint16_t port);
246int it8705f_write_enable(uint8_t port);
247uint8_t sio_read(uint16_t port, uint8_t reg);
248void sio_write(uint16_t port, uint8_t reg, uint8_t data);
249void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000250void board_handle_before_superio(void);
251void board_handle_before_laptop(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000252int board_flash_enable(const char *vendor, const char *part);
253
254/* chipset_enable.c */
255int chipset_flash_enable(void);
256
257/* processor_enable.c */
258int processor_flash_enable(void);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000259#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000260
261/* physmap.c */
262void *physmap(const char *descr, unsigned long phys_addr, size_t len);
263void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len);
264void physunmap(void *virt_addr, size_t len);
265int setup_cpu_msr(int cpu);
266void cleanup_cpu_msr(void);
267
268/* cbtable.c */
269void lb_vendor_dev_from_string(char *boardstring);
270int coreboot_init(void);
271extern char *lb_part, *lb_vendor;
272extern int partvendor_from_cbtable;
273
274/* dmi.c */
275extern int has_dmi_support;
276void dmi_init(void);
277int dmi_match(const char *pattern);
278
279/* internal.c */
280#if NEED_PCI == 1
281struct superio {
282 uint16_t vendor;
283 uint16_t port;
284 uint16_t model;
285};
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000286extern struct superio superios[];
287extern int superio_count;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000288#define SUPERIO_VENDOR_NONE 0x0
289#define SUPERIO_VENDOR_ITE 0x1
290struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
291struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class);
292struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
293struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
294 uint16_t card_vendor, uint16_t card_device);
295#endif
296void get_io_perms(void);
297void release_io_perms(void);
298#if CONFIG_INTERNAL == 1
299extern int is_laptop;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000300extern int laptop_ok;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000301extern int force_boardenable;
302extern int force_boardmismatch;
303void probe_superio(void);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000304int register_superio(struct superio s);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000305int internal_init(void);
306int internal_shutdown(void);
307void internal_chip_writeb(uint8_t val, chipaddr addr);
308void internal_chip_writew(uint16_t val, chipaddr addr);
309void internal_chip_writel(uint32_t val, chipaddr addr);
310uint8_t internal_chip_readb(const chipaddr addr);
311uint16_t internal_chip_readw(const chipaddr addr);
312uint32_t internal_chip_readl(const chipaddr addr);
313void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
314#endif
315
316/* hwaccess.c */
317void mmio_writeb(uint8_t val, void *addr);
318void mmio_writew(uint16_t val, void *addr);
319void mmio_writel(uint32_t val, void *addr);
320uint8_t mmio_readb(void *addr);
321uint16_t mmio_readw(void *addr);
322uint32_t mmio_readl(void *addr);
323void mmio_le_writeb(uint8_t val, void *addr);
324void mmio_le_writew(uint16_t val, void *addr);
325void mmio_le_writel(uint32_t val, void *addr);
326uint8_t mmio_le_readb(void *addr);
327uint16_t mmio_le_readw(void *addr);
328uint32_t mmio_le_readl(void *addr);
329#define pci_mmio_writeb mmio_le_writeb
330#define pci_mmio_writew mmio_le_writew
331#define pci_mmio_writel mmio_le_writel
332#define pci_mmio_readb mmio_le_readb
333#define pci_mmio_readw mmio_le_readw
334#define pci_mmio_readl mmio_le_readl
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000335void rmmio_writeb(uint8_t val, void *addr);
336void rmmio_writew(uint16_t val, void *addr);
337void rmmio_writel(uint32_t val, void *addr);
338void rmmio_le_writeb(uint8_t val, void *addr);
339void rmmio_le_writew(uint16_t val, void *addr);
340void rmmio_le_writel(uint32_t val, void *addr);
341#define pci_rmmio_writeb rmmio_le_writeb
342#define pci_rmmio_writew rmmio_le_writew
343#define pci_rmmio_writel rmmio_le_writel
344void rmmio_valb(void *addr);
345void rmmio_valw(void *addr);
346void rmmio_vall(void *addr);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000347
348/* programmer.c */
349int noop_shutdown(void);
350void *fallback_map(const char *descr, unsigned long phys_addr, size_t len);
351void fallback_unmap(void *virt_addr, size_t len);
352uint8_t noop_chip_readb(const chipaddr addr);
353void noop_chip_writeb(uint8_t val, chipaddr addr);
354void fallback_chip_writew(uint16_t val, chipaddr addr);
355void fallback_chip_writel(uint32_t val, chipaddr addr);
356void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
357uint16_t fallback_chip_readw(const chipaddr addr);
358uint32_t fallback_chip_readl(const chipaddr addr);
359void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
360
361/* dummyflasher.c */
362#if CONFIG_DUMMY == 1
363int dummy_init(void);
364int dummy_shutdown(void);
365void *dummy_map(const char *descr, unsigned long phys_addr, size_t len);
366void dummy_unmap(void *virt_addr, size_t len);
367void dummy_chip_writeb(uint8_t val, chipaddr addr);
368void dummy_chip_writew(uint16_t val, chipaddr addr);
369void dummy_chip_writel(uint32_t val, chipaddr addr);
370void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
371uint8_t dummy_chip_readb(const chipaddr addr);
372uint16_t dummy_chip_readw(const chipaddr addr);
373uint32_t dummy_chip_readl(const chipaddr addr);
374void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000375#endif
376
377/* nic3com.c */
378#if CONFIG_NIC3COM == 1
379int nic3com_init(void);
380int nic3com_shutdown(void);
381void nic3com_chip_writeb(uint8_t val, chipaddr addr);
382uint8_t nic3com_chip_readb(const chipaddr addr);
383extern const struct pcidev_status nics_3com[];
384#endif
385
386/* gfxnvidia.c */
387#if CONFIG_GFXNVIDIA == 1
388int gfxnvidia_init(void);
389int gfxnvidia_shutdown(void);
390void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr);
391uint8_t gfxnvidia_chip_readb(const chipaddr addr);
392extern const struct pcidev_status gfx_nvidia[];
393#endif
394
395/* drkaiser.c */
396#if CONFIG_DRKAISER == 1
397int drkaiser_init(void);
398int drkaiser_shutdown(void);
399void drkaiser_chip_writeb(uint8_t val, chipaddr addr);
400uint8_t drkaiser_chip_readb(const chipaddr addr);
401extern const struct pcidev_status drkaiser_pcidev[];
402#endif
403
404/* nicrealtek.c */
405#if CONFIG_NICREALTEK == 1
406int nicrealtek_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000407int nicrealtek_shutdown(void);
408void nicrealtek_chip_writeb(uint8_t val, chipaddr addr);
409uint8_t nicrealtek_chip_readb(const chipaddr addr);
410extern const struct pcidev_status nics_realtek[];
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000411#endif
412
413/* nicnatsemi.c */
414#if CONFIG_NICNATSEMI == 1
415int nicnatsemi_init(void);
416int nicnatsemi_shutdown(void);
417void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr);
418uint8_t nicnatsemi_chip_readb(const chipaddr addr);
419extern const struct pcidev_status nics_natsemi[];
420#endif
421
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000422/* nicintel.c */
423#if CONFIG_NICINTEL == 1
424int nicintel_init(void);
425int nicintel_shutdown(void);
426void nicintel_chip_writeb(uint8_t val, chipaddr addr);
427uint8_t nicintel_chip_readb(const chipaddr addr);
428extern const struct pcidev_status nics_intel[];
429#endif
430
Idwer Vollering004f4b72010-09-03 18:21:21 +0000431/* nicintel_spi.c */
432#if CONFIG_NICINTEL_SPI == 1
433int nicintel_spi_init(void);
434int nicintel_spi_shutdown(void);
435int nicintel_spi_send_command(unsigned int writecnt, unsigned int readcnt,
436 const unsigned char *writearr, unsigned char *readarr);
437void nicintel_spi_chip_writeb(uint8_t val, chipaddr addr);
438extern const struct pcidev_status nics_intel_spi[];
439#endif
440
Mark Marshall90021f22010-12-03 14:48:11 +0000441/* ogp_spi.c */
442#if CONFIG_OGP_SPI == 1
443int ogp_spi_init(void);
444int ogp_spi_shutdown(void);
445extern const struct pcidev_status ogp_spi[];
446#endif
447
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000448/* satamv.c */
449#if CONFIG_SATAMV == 1
450int satamv_init(void);
451int satamv_shutdown(void);
452void satamv_chip_writeb(uint8_t val, chipaddr addr);
453uint8_t satamv_chip_readb(const chipaddr addr);
454extern const struct pcidev_status satas_mv[];
455#endif
456
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000457/* satasii.c */
458#if CONFIG_SATASII == 1
459int satasii_init(void);
460int satasii_shutdown(void);
461void satasii_chip_writeb(uint8_t val, chipaddr addr);
462uint8_t satasii_chip_readb(const chipaddr addr);
463extern const struct pcidev_status satas_sii[];
464#endif
465
466/* atahpt.c */
467#if CONFIG_ATAHPT == 1
468int atahpt_init(void);
469int atahpt_shutdown(void);
470void atahpt_chip_writeb(uint8_t val, chipaddr addr);
471uint8_t atahpt_chip_readb(const chipaddr addr);
472extern const struct pcidev_status ata_hpt[];
473#endif
474
475/* ft2232_spi.c */
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000476#if CONFIG_FT2232_SPI == 1
477struct usbdev_status {
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000478 uint16_t vendor_id;
479 uint16_t device_id;
480 int status;
481 const char *vendor_name;
482 const char *device_name;
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000483};
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000484int ft2232_spi_init(void);
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000485extern const struct usbdev_status devs_ft2232spi[];
486void print_supported_usbdevs(const struct usbdev_status *devs);
487#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000488
489/* rayer_spi.c */
490#if CONFIG_RAYER_SPI == 1
491int rayer_spi_init(void);
492#endif
493
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000494/* mcp6x_spi.c */
495#if CONFIG_INTERNAL == 1
496#if defined(__i386__) || defined(__x86_64__)
497int mcp6x_spi_init(int want_spi);
498#endif
499#endif
500
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000501/* bitbang_spi.c */
502int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000503int bitbang_spi_shutdown(const struct bitbang_spi_master *master);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000504
505/* buspirate_spi.c */
506struct buspirate_spispeeds {
507 const char *name;
508 const int speed;
509};
510int buspirate_spi_init(void);
511int buspirate_spi_shutdown(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000512
513/* dediprog.c */
514int dediprog_init(void);
515int dediprog_shutdown(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000516
517/* flashrom.c */
518struct decode_sizes {
519 uint32_t parallel;
520 uint32_t lpc;
521 uint32_t fwh;
522 uint32_t spi;
523};
524extern struct decode_sizes max_rom_decode;
525extern int programmer_may_write;
526extern unsigned long flashbase;
Carl-Daniel Hailfinger4c823182011-05-04 00:39:50 +0000527void check_chip_supported(const struct flashchip *flash);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000528int check_max_decode(enum chipbustype buses, uint32_t size);
529char *extract_programmer_param(char *param_name);
530
531/* layout.c */
532int show_id(uint8_t *bios, int size, int force);
533
534/* spi.c */
535enum spi_controller {
536 SPI_CONTROLLER_NONE,
537#if CONFIG_INTERNAL == 1
538#if defined(__i386__) || defined(__x86_64__)
539 SPI_CONTROLLER_ICH7,
540 SPI_CONTROLLER_ICH9,
David Hendricks4e748392011-02-28 23:58:15 +0000541 SPI_CONTROLLER_IT85XX,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000542 SPI_CONTROLLER_IT87XX,
543 SPI_CONTROLLER_SB600,
544 SPI_CONTROLLER_VIA,
545 SPI_CONTROLLER_WBSIO,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000546#endif
547#endif
548#if CONFIG_FT2232_SPI == 1
549 SPI_CONTROLLER_FT2232,
550#endif
551#if CONFIG_DUMMY == 1
552 SPI_CONTROLLER_DUMMY,
553#endif
554#if CONFIG_BUSPIRATE_SPI == 1
555 SPI_CONTROLLER_BUSPIRATE,
556#endif
557#if CONFIG_DEDIPROG == 1
558 SPI_CONTROLLER_DEDIPROG,
559#endif
Michael Karcherb9dbe482011-05-11 17:07:07 +0000560#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__)))
561 SPI_CONTROLLER_BITBANG,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000562#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000563};
564extern const int spi_programmer_count;
Michael Karcher62797512011-05-11 17:07:02 +0000565
566#define MAX_DATA_UNSPECIFIED 0
567#define MAX_DATA_READ_UNLIMITED 64 * 1024
568#define MAX_DATA_WRITE_UNLIMITED 256
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000569struct spi_programmer {
Michael Karcherb9dbe482011-05-11 17:07:07 +0000570 enum spi_controller type;
Michael Karcher62797512011-05-11 17:07:02 +0000571 int max_data_read;
572 int max_data_write;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000573 int (*command)(unsigned int writecnt, unsigned int readcnt,
574 const unsigned char *writearr, unsigned char *readarr);
575 int (*multicommand)(struct spi_command *cmds);
576
577 /* Optimized functions for this programmer */
578 int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len);
579 int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len);
580};
581
Michael Karcherb9dbe482011-05-11 17:07:07 +0000582extern const struct spi_programmer *spi_programmer;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000583int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
584 const unsigned char *writearr, unsigned char *readarr);
585int default_spi_send_multicommand(struct spi_command *cmds);
Michael Karcher62797512011-05-11 17:07:02 +0000586int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
587int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000588void register_spi_programmer(const struct spi_programmer *programmer);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000589
590/* ichspi.c */
591#if CONFIG_INTERNAL == 1
592extern uint32_t ichspi_bbar;
593int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
594 int ich_generation);
595int via_init_spi(struct pci_dev *dev);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000596#endif
597
David Hendricks4e748392011-02-28 23:58:15 +0000598/* it85spi.c */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000599int it85xx_spi_init(struct superio s);
David Hendricks4e748392011-02-28 23:58:15 +0000600int it85xx_shutdown(void);
David Hendricks4e748392011-02-28 23:58:15 +0000601
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000602/* it87spi.c */
603void enter_conf_mode_ite(uint16_t port);
604void exit_conf_mode_ite(uint16_t port);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000605void probe_superio_ite(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000606int init_superio_ite(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000607
608/* sb600spi.c */
609#if CONFIG_INTERNAL == 1
610int sb600_probe_spi(struct pci_dev *dev);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000611#endif
612
613/* wbsio_spi.c */
614#if CONFIG_INTERNAL == 1
615int wbsio_check_for_spi(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000616#endif
617
618/* serprog.c */
619int serprog_init(void);
620int serprog_shutdown(void);
621void serprog_chip_writeb(uint8_t val, chipaddr addr);
622uint8_t serprog_chip_readb(const chipaddr addr);
623void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
624void serprog_delay(int delay);
625
626/* serial.c */
627#if _WIN32
628typedef HANDLE fdtype;
629#else
630typedef int fdtype;
631#endif
632
633void sp_flush_incoming(void);
634fdtype sp_openserport(char *dev, unsigned int baud);
635void __attribute__((noreturn)) sp_die(char *msg);
636extern fdtype sp_fd;
637int serialport_shutdown(void);
638int serialport_write(unsigned char *buf, unsigned int writecnt);
639int serialport_read(unsigned char *buf, unsigned int readcnt);
640
641#endif /* !__PROGRAMMER_H__ */