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Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __SPI_H__
21#define __SPI_H__ 1
22
23/*
24 * Contains the generic SPI headers
25 */
26
27/* Read Electronic ID */
28#define JEDEC_RDID 0x9f
29#define JEDEC_RDID_OUTSIZE 0x01
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000030/* INSIZE may be 0x04 for some chips*/
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000031#define JEDEC_RDID_INSIZE 0x03
32
Carl-Daniel Hailfinger0faf03e2008-11-28 23:47:55 +000033/* AT25F512A has bit 3 as don't care bit in commands */
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +000034#define AT25F512A_RDID 0x15 /* 0x15 or 0x1d */
Carl-Daniel Hailfinger0faf03e2008-11-28 23:47:55 +000035#define AT25F512A_RDID_OUTSIZE 0x01
36#define AT25F512A_RDID_INSIZE 0x02
37
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +000038/* Read Electronic Manufacturer Signature */
39#define JEDEC_REMS 0x90
40#define JEDEC_REMS_OUTSIZE 0x04
41#define JEDEC_REMS_INSIZE 0x02
42
Stefan Taunerac1b4c82012-02-17 14:51:04 +000043/* Read Serial Flash Discoverable Parameters (SFDP) */
44#define JEDEC_SFDP 0x5a
45#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */
46/* JEDEC_SFDP_INSIZE : any length */
47
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000048/* Read Electronic Signature */
49#define JEDEC_RES 0xab
50#define JEDEC_RES_OUTSIZE 0x04
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000051/* INSIZE may be 0x02 for some chips*/
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000052#define JEDEC_RES_INSIZE 0x01
53
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000054/* Write Enable */
55#define JEDEC_WREN 0x06
56#define JEDEC_WREN_OUTSIZE 0x01
57#define JEDEC_WREN_INSIZE 0x00
58
59/* Write Disable */
60#define JEDEC_WRDI 0x04
61#define JEDEC_WRDI_OUTSIZE 0x01
62#define JEDEC_WRDI_INSIZE 0x00
63
64/* Chip Erase 0x60 is supported by Macronix/SST chips. */
65#define JEDEC_CE_60 0x60
66#define JEDEC_CE_60_OUTSIZE 0x01
67#define JEDEC_CE_60_INSIZE 0x00
68
Peter Stugef83221b2008-07-07 06:38:51 +000069/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000070#define JEDEC_CE_C7 0xc7
71#define JEDEC_CE_C7_OUTSIZE 0x01
72#define JEDEC_CE_C7_INSIZE 0x00
73
Carl-Daniel Hailfingerd54ef6e2008-11-15 13:55:43 +000074/* Block Erase 0x52 is supported by SST and old Atmel chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000075#define JEDEC_BE_52 0x52
76#define JEDEC_BE_52_OUTSIZE 0x04
77#define JEDEC_BE_52_INSIZE 0x00
78
79/* Block Erase 0xd8 is supported by EON/Macronix chips. */
80#define JEDEC_BE_D8 0xd8
81#define JEDEC_BE_D8_OUTSIZE 0x04
82#define JEDEC_BE_D8_INSIZE 0x00
83
Sean Nelson5643c072010-01-19 03:23:07 +000084/* Block Erase 0xd7 is supported by PMC chips. */
85#define JEDEC_BE_D7 0xd7
86#define JEDEC_BE_D7_OUTSIZE 0x04
87#define JEDEC_BE_D7_INSIZE 0x00
88
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000089/* Sector Erase 0x20 is supported by Macronix/SST chips. */
90#define JEDEC_SE 0x20
91#define JEDEC_SE_OUTSIZE 0x04
92#define JEDEC_SE_INSIZE 0x00
93
94/* Read Status Register */
95#define JEDEC_RDSR 0x05
96#define JEDEC_RDSR_OUTSIZE 0x01
97#define JEDEC_RDSR_INSIZE 0x01
Stefan Tauner5e695ab2012-05-06 17:03:40 +000098
99/* Status Register Bits */
100#define SPI_SR_WIP (0x01 << 0)
101#define SPI_SR_WEL (0x01 << 1)
102#define SPI_SR_AAI (0x01 << 6)
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000103
Jason Wanga3f04be2008-11-28 21:36:51 +0000104/* Write Status Enable */
105#define JEDEC_EWSR 0x50
106#define JEDEC_EWSR_OUTSIZE 0x01
107#define JEDEC_EWSR_INSIZE 0x00
108
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000109/* Write Status Register */
110#define JEDEC_WRSR 0x01
111#define JEDEC_WRSR_OUTSIZE 0x02
112#define JEDEC_WRSR_INSIZE 0x00
113
114/* Read the memory */
115#define JEDEC_READ 0x03
116#define JEDEC_READ_OUTSIZE 0x04
117/* JEDEC_READ_INSIZE : any length */
118
119/* Write memory byte */
Carl-Daniel Hailfingerd99b8d32010-07-29 16:32:24 +0000120#define JEDEC_BYTE_PROGRAM 0x02
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000121#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
122#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
123
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000124/* Write AAI word (SST25VF080B) */
Carl-Daniel Hailfingerd99b8d32010-07-29 16:32:24 +0000125#define JEDEC_AAI_WORD_PROGRAM 0xad
126#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06
127#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03
128#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000129
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000130/* Error codes */
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000131#define SPI_GENERIC_ERROR -1
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000132#define SPI_INVALID_OPCODE -2
133#define SPI_INVALID_ADDRESS -3
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000134#define SPI_INVALID_LENGTH -4
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000135#define SPI_FLASHROM_BUG -5
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000136#define SPI_PROGRAMMER_ERROR -6
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000137
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000138#endif /* !__SPI_H__ */